//Aula 13/07/17

module teste(SW, LEDR)

input [2:0] SW;
output [1:0] LEDR;


module somador4bits(output [4:0]LEDR, input [8:0]SW);
wire w1,w2,w3;

somador a1(SW[0], SW[2], SW[4], w1, LEDR[0]);
somador a2(SW[1], SW[3], w1, w2, LEDR[1]);

reg dado;

assign dado = SW[0];
assign reset = SW[1];
assign clock = SW[2];

always @(negedge reset & posedge clock)
begin
    if (clock)
        dado = ~dado;
end

assign LEDR[0] = dado;
endmodule