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Datablock

MBJ Apr 22nd, 2019 106 Never
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  1. `timescale 1ns / 1ps
  2.  
  3. // EXECUTE phase of pipeline
  4. // asynchronous (memory write is posedge sync)
  5. // make it 32-bits by 255 (so width is 32 bits, have 255 of them)
  6.  
  7. // 'clock and reset goes to all registers'
  8.  
  9. module Data_block(
  10.                 input [31:0] Address,   // comes from bus-A
  11.                 input [31:0] Data_in,       // comes from bus-B
  12.                 input clk, MW, rst,
  13.                 output reg [31:0] Data_out  // technically, bus-B bits mapped from bus-A
  14.                 );
  15.  
  16. // need to have a register of all of the data
  17.  
  18. reg [31:0] DATA [255:0]; // external memory
  19.  
  20. integer i;
  21.  
  22. initial begin // initialize all to zero
  23.     for(i = 0; i <256; i = i + 1) begin
  24.         DATA[i] = 0;
  25.     end
  26. end
  27.  
  28.  
  29. // both blocks work off of data register
  30. always@(*) begin    // Data_read block, asynchronous
  31.     Data_out = DATA[Address];   // address is 32 bit number, so can only map to 32 bits
  32. end
  33.  
  34. always@(posedge clk, posedge rst) begin     // data_write block, rising edge of clock
  35.     if(rst) begin
  36.         for(i = 0; i < 256; i = i + 1) begin
  37.             DATA[i] = 0;
  38.         end
  39.     end
  40.     else if(Address > 254)
  41.         DATA[254] = (MW)? Data_in : DATA[254];  // if address value is greater than maximum memory allocation
  42.     else
  43.         DATA[Address] = (MW)? Data_in : DATA[Address];  // dependent on MEMORY WRITE bit, if so writes over, else keeps data
  44. end
  45.  
  46. endmodule
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