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- module prova(select, SW, LEDR);
- input[1:0] select;
- input[3:0] SW;
- output[0:0] LEDR;
- reg LEDR[0];
- wire[1:0] select;
- wire[3:0] SW;
- always@(SW or select)
- LEDR = d[select];
- endmodule
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