/*
    Interface for accelerated vgg16 IP Core
*/
module vgg16Interface (
    // Avalon Clock Input
    input logic CLK,

    // Avalon Reset Input
    input logic RESET,

    // Avalon-MM Slave Signals
    input  logic AVL_READ,                  // Avalon-MM Read
    input  logic AVL_WRITE,                 // Avalon-MM Write
    input  logic AVL_CS,                        // Avalon-MM Chip Select
    input  logic [3:0] AVL_BYTE_EN,     // Avalon-MM Byte Enable
    input  logic [13:0] AVL_ADDR,           // Avalon-MM Address
    input  logic [31:0] AVL_WRITEDATA,  // Avalon-MM Write Data
    output logic [31:0] AVL_READDATA,   // Avalon-MM Read Data

    // Exported Conduit
    output logic [31:0] EXPORT_DATA     // Exported Conduit Signal to LEDs
);

// 3*3*128 = 1152

// an unpacked array of 32-bit registers
logic [31:0] reggy [4607:0];

// register for Done Signal
logic [31:0] startReg;

// register for Start Signal
logic [31:0] doneReg;

// Assign variables for the AES interface variables
logic [127:0] AES_MSG_DEC;
// just for debugging
logic VGG16_DONE;
logic VGG16_START;
logic [127:0] AES_KEY;
logic [127:0] AES_MSG_ENC;

assign AES_MSG_ENC = {reggy[4], reggy[5], reggy[6], reggy[7]};
assign VGG16_START = startReg[0];


// Instantiate AES interface to get AES_MSG_DEC

//AES aes(.*);

//convMult(.*);

always_ff @ (posedge CLK)
begin
    // Reset is active HIGH
    if(RESET)
    begin
        // initialize register contents to 0
        reggy[0] <= 32'b0;
    end
    else if(AVL_CS)
    begin
        if(AVL_WRITE)
        begin
            // depending on which register is the destination register, load contents from data bus into
            // that register
            case(AVL_ADDR)
                14'd9216 : startReg <= AVL_WRITEDATA;
                default: reggy[AVL_ADDR] <= AVL_WRITEDATA;
            endcase


        end
        else if(VGG16_DONE)
        begin
            // change to reggy <= output of convMult
            reggy[11] <= AES_MSG_DEC[127:96];
            reggy[10] <= AES_MSG_DEC[95:64];
            reggy[9] <= AES_MSG_DEC[63:32];
            reggy[8] <= AES_MSG_DEC[31:0];
        end
        else
        begin
            reggy <= reggy;
        end
    end
end


always_comb
begin

            if(AVL_READ && AVL_CS)
            begin
                case(AVL_ADDR)
                    14'd9217 : AVL_READDATA = doneReg;
                    default : AVL_READDATA = reggy[AVL_ADDR];
                endcase
            end
            else
                AVL_READDATA = 32'bx;
end




// this doesn't matter simply for LEDs
assign EXPORT_DATA = {reggy[4][31:16] , reggy[7][15:0]};

assign doneReg = {31'b0, VGG16_DONE};

endmodule