library ieee;
use ieee.std_logic_1164.all;

entity Lab5Part1 is
			port (SW : IN std_logic_vecTOR(9 DOWNTO 0);
		 	LEDR : OUT std_logic_vector(9 downto 0));
END Lab5Part1;

Architecture Behavior OF Lab5Part1 is
					Begin
					LEDR <= SW;
	End Behavior;