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Feb 23rd, 2018
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ARM 1.46 KB | None | 0 0
  1.     b reset
  2.     b hang
  3.     b hang
  4.     b hang
  5.  
  6.     b hang
  7.     b hang
  8.     b hang
  9.     b hang
  10.  
  11.     b hang
  12.     b hang
  13.     b hang
  14.     b hang
  15.  
  16.     b hang
  17.     b hang
  18.     b hang
  19.     b hang
  20.  
  21.     TIMER_CR     EQU 8   ; Control Register, TimerXControl
  22.     TIMER_INTCLR EQU 0xC ; Interrupt Clear Register, TimerXIntClr
  23. reset:
  24.     mov sp, #0x20000
  25. ;****************************************
  26. ;*         Enable Timer0 and IRQs       *
  27. ;****************************************
  28.     ldr r0, [TIMER_COUNT]
  29.     str r0, [TIMER_BASE]
  30.     ldr r1, [TIMER_BASE]
  31.     add r1, TIMER_INTCLR
  32.     mov r2, #0
  33.     str r2, [r1]
  34.  
  35.     mov r0, #0xE2 ; Timer Enable, Periodic Mode, IRQ ON, Prescale = 0, 32 bit, Wrapping Mode
  36.     ldr r1, [TIMER_BASE]
  37.     add r1, TIMER_CR
  38.     str r0, [r1]
  39.  
  40.     mrs r0, cpsr
  41.     bic r0, r0, #0x80 ; Clear IRQ Disable
  42.     msr cpsr_c, r0
  43.  
  44.     b  mainloop
  45.     TIMER_BASE: dd 0x101E2000
  46.     TIMER_COUNT: dd 1000000
  47. hang:
  48.     b hang
  49. ;****************************************
  50. ;*            Kernel Mainloop           *
  51. ;****************************************
  52. mainloop:
  53.     ldr r1, [pc, 4]
  54.     bl uart_put32
  55.     b mainloop
  56.     dd 0x50505050
  57. ;****************************************
  58. ;* UART Write 32 Bit Value              *
  59. ;* Input: R1 Value to be written        *
  60. ;* Output: None                         *
  61. ;****************************************
  62. uart_put32:
  63.     ldr r0, [pc, 4]   ; PC + 16
  64.     str r1, [r0]
  65.     bx lr
  66.     dd 0x101f1000
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