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Apr 3rd, 2013
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  1. module clock_divider(
  2. input clk_50MHz,
  3. output reg clk_1Hz
  4. );
  5.  
  6. reg [25:0] count;
  7. initial count = 0;
  8. initial clk_1Hz = 0;
  9. always @(posedge clk_50MHz)
  10. begin
  11. if(count < 25'd25000000)
  12. count=count+1;
  13. else
  14. begin
  15. count = 25'd0;
  16. clk_1Hz = !clk_1Hz;
  17. end
  18. end
  19. endmodule
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