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  1. Bail out if s_fence is no longer fresh.
  2. https://patchwork.freedesktop.org/patch/333645/
  3. --- a/drivers/gpu/drm/scheduler/sched_main.c
  4. +++ b/drivers/gpu/drm/scheduler/sched_main.c
  5. @@ -333,6 +333,10 @@ void drm_sched_increase_karma(struct drm
  6.  
  7. spin_lock(&rq->lock);
  8. list_for_each_entry_safe(entity, tmp, &rq->entities, list) {
  9. + if (!smp_load_acquire(&bad->s_fence)) {
  10. + spin_unlock(&rq->lock);
  11. + return;
  12. + }
  13. if (bad->s_fence->scheduled.context ==
  14. entity->fence_context) {
  15. if (atomic_read(&bad->karma) >
  16. @@ -543,7 +547,7 @@ EXPORT_SYMBOL(drm_sched_job_init);
  17. void drm_sched_job_cleanup(struct drm_sched_job *job)
  18. {
  19. dma_fence_put(&job->s_fence->finished);
  20. - job->s_fence = NULL;
  21. + smp_store_release(&job->s_fence, 0);
  22. }
  23. EXPORT_SYMBOL(drm_sched_job_cleanup);
  24.  
  25.  
  26. Panfrost uses multiple schedulers (one for each slot, so 2 in reality),
  27. and on a timeout has to stop all the schedulers to safely perform a
  28. reset. However more than one scheduler can trigger a timeout at the same
  29. time. This race condition results in jobs being freed while they are
  30. still in use.
  31.  
  32. Modify drm_sched_stop() to call cancel_delayed_work_sync() when stopping
  33. a different scheduler to the one belonging to the passed in job.
  34. panfrost_job_timedout() is also modified to only allow one thread at a
  35. time to handle the reset. Any subsequent threads simply return assuming
  36. that the first thread will handle the situation.
  37. https://patchwork.freedesktop.org/patch/333258/
  38. MRFIXIT had to adjust
  39. diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
  40. index f503c566e99f..6441c7fba6c4 100644
  41. --- a/drivers/gpu/drm/panfrost/panfrost_device.h
  42. +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
  43. @@ -99,6 +99,8 @@ struct panfrost_device {
  44. unsigned long cur_volt;
  45. struct panfrost_devfreq_slot slot[NUM_JOB_SLOTS];
  46. } devfreq;
  47. +
  48. + bool is_resetting;
  49. };
  50.  
  51. struct panfrost_mmu {
  52. diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c
  53. index 05c85f45a0de..1b2019e08b43 100644
  54. --- a/drivers/gpu/drm/panfrost/panfrost_job.c
  55. +++ b/drivers/gpu/drm/panfrost/panfrost_job.c
  56. @@ -392,6 +392,11 @@
  57. job_read(pfdev, JS_TAIL_LO(js)),
  58. sched_job);
  59.  
  60. + if (pfdev->is_resetting) {
  61. + return;
  62. + }
  63. + pfdev->is_resetting = true;
  64. +
  65. if (!mutex_trylock(&pfdev->reset_lock))
  66. return;
  67.  
  68. @@ -425,6 +430,7 @@
  69. for (i = 0; i < NUM_JOB_SLOTS; i++)
  70. drm_sched_start(&pfdev->js->queue[i].sched, true);
  71.  
  72. + pfdev->is_resetting = false;
  73. mutex_unlock(&pfdev->reset_lock);
  74. }
  75.  
  76.  
  77. diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
  78. index 148468447ba9..bc6d1862ec8a 100644
  79. --- a/drivers/gpu/drm/scheduler/sched_main.c
  80. +++ b/drivers/gpu/drm/scheduler/sched_main.c
  81. @@ -415,7 +415,10 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad)
  82. * this TDR finished and before the newly restarted jobs had a
  83. * chance to complete.
  84. */
  85. - cancel_delayed_work(&sched->work_tdr);
  86. + if (bad->sched != sched)
  87. + cancel_delayed_work_sync(&sched->work_tdr);
  88. + else
  89. + cancel_delayed_work(&sched->work_tdr);
  90. }
  91.  
  92. EXPORT_SYMBOL(drm_sched_stop);
  93.  
  94.  
  95. From 199ee71f2ef17372e3e788e129cbf61536fe9fa3 Mon Sep 17 00:00:00 2001
  96. From: Robin Murphy <robin.murphy@arm.com>
  97. Date: Wed, 11 Sep 2019 15:42:09 +0100
  98. Subject: [PATCH] iommu/io-pgtable-arm: Allow coherent walks for Mali
  99.  
  100. Midgard GPUs have ACE-Lite master interfaces which allows systems to
  101. integrate them in an I/O-coherent manner. It seems that from the GPU's
  102. viewpoint, the rest of the system is its outer shareable domain, and it
  103. will only emit snoop signals for outer shareable accesses. As such,
  104. setting the TTBR_SHARE_OUTER bit does indeed get coherent pagetable
  105. walks working nicely.
  106.  
  107. Making data accesses coherent seems to be more of a challenge...
  108.  
  109. Signed-off-by: Robin Murphy <robin.murphy@arm.com>
  110. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
  111. ---
  112. drivers/iommu/io-pgtable-arm.c | 3 +++
  113. 1 file changed, 3 insertions(+)
  114.  
  115. diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
  116. index 77f41c9dd9be7..2794d46613392 100644
  117. --- a/drivers/iommu/io-pgtable-arm.c
  118. +++ b/drivers/iommu/io-pgtable-arm.c
  119. @@ -1061,6 +1061,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
  120. cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
  121. ARM_MALI_LPAE_TTBR_READ_INNER |
  122. ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
  123. + if (cfg->coherent_walk)
  124. + cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
  125. +
  126. return &data->iop;
  127.  
  128. out_free_data:
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