bcd7seg

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BCDto7seg is
port (wej: in std_logic_vector (3 downto 0);
		sevenseg: out std_logic_vector(6 downto 0));
		end BCDto7seg;

architecture ledy of BCDto7seg is
begin
	process(wej)
		begin
			case wej is
				when "0000" => sevenseg <= "1000000";
				when "0001" => sevenseg <= "1111001";
				when "0010" => sevenseg <= "0100100";
				when "0011" => sevenseg <= "0110000";
				when "0100" => sevenseg <= "0011001";
				when "0101" => sevenseg <= "0010010";
				when "0110" => sevenseg <= "0000010";
				when "0111" => sevenseg <= "1111000";
				when "1000" => sevenseg <= "0000000";
				when "1001" => sevenseg <= "0010000";
				when others => sevenseg <= "-------";
			end case;
	end process;
end ledy;