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STANAANDREY

sadd

Nov 2nd, 2023
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  1. module sadd(
  2.     input clk, rst,
  3.     input x, y,
  4.     output reg z
  5. );
  6.     localparam S0 = 0, S1 = 1;
  7.     reg st, st_nxt;
  8.     always @(*)
  9.         case (st)
  10.         S0:
  11.             if (x & y) st_nxt = S1;
  12.             else st_nxt = S0;
  13.         S1:
  14.             if ((~x) & (~y)) st_nxt = S0;
  15.             else st_nxt = S1;
  16.         endcase
  17.  
  18.     always @(*) begin
  19.         z = 0;
  20.         case (st)
  21.         S0:
  22.             if (x ^ y) z = 1;
  23.         S1:
  24.             if (x ~^ y) z = 1;
  25.         endcase
  26.     end
  27.        
  28.     always @(posedge clk, negedge rst)
  29.         if (!rst) st <= S0;
  30.         else st <= st_nxt;
  31. endmodule
  32.  
  33.  
  34. module sadd_tb;
  35.     reg clk, rst, x, y;
  36.     wire z;
  37.     sadd inst(.clk(clk), .rst(rst), .x(x), .y(y));
  38.     localparam CLK_PERIOD = 100, RST_PULSE = 10, CLK_CYCLES = 5;
  39.     initial begin
  40.         clk = 0;
  41.         repeat (2*CLK_CYCLES)
  42.             #(CLK_PERIOD/2) clk=~clk;
  43.     end
  44.     initial begin
  45.         rst = 0;
  46.         #(RST_PULSE) rst = 1;
  47.     end
  48.     initial begin
  49.         {x,y}='b01;
  50.         #(1*CLK_PERIOD) {x,y}='b10;
  51.         #(1*CLK_PERIOD) {x,y}='b11;
  52.         #(1*CLK_PERIOD) {x,y}='b00;
  53.     end
  54.    
  55. endmodule
  56.  
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