Dedicated IOs: 0
('muxed cells', [['0', 'vsse_0', ''], ['1', 'vdde_0', ''], ['2', 'vddi_0', ''], ['3', 'vssi_0', ''], ['4', 'sdr_dqm0', ''], ['5', 'sdr_d0', ''], ['6', 'sdr_d1', ''], ['7', 'sdr_d2', ''], ['8', 'sdr_d3', ''], ['9', 'sdr_d4', ''], ['10', 'sdr_d5', ''], ['11', 'sdr_d6', ''], ['12', 'sdr_d7', ''], ['13', 'sdr_ba0', ''], ['14', 'sdr_ba1', ''], ['15', 'sdr_ad0', ''], ['16', 'sdr_ad1', ''], ['17', 'sdr_ad2', ''], ['18', 'sdr_ad3', ''], ['19', 'sdr_ad4', ''], ['20', 'sdr_ad5', ''], ['21', 'sdr_ad6', ''], ['22', 'sdr_ad7', ''], ['23', 'sdr_ad8', ''], ['24', 'sdr_ad9', ''], ['25', 'sdr_clk', ''], ['26', 'sdr_cke', ''], ['27', 'sdr_rasn', ''], ['28', 'sdr_casn', ''], ['29', 'sdr_wen', ''], ['30', 'sdr_csn0', ''], ['54', 'vssi_0', ''], ['55', 'vddi_0', ''], ['56', 'vsse_0', ''], ['57', 'vdde_0', ''], ['59', 'sys_rst', ''], ['60', 'sys_pllclk', ''], ['61', 'sys_pllsela0', ''], ['62', 'sys_pllsela1', ''], ['63', 'sys_plltestout', ''], ['64', 'vsse_0', ''], ['65', 'vdde_0', ''], ['66', 'rg2_erxd0', ''], ['67', 'rg2_erxd1', ''], ['68', 'rg2_erxd2', ''], ['69', 'rg2_erxd3', ''], ['70', 'rg2_etxd0', ''], ['71', 'rg2_etxd1', ''], ['72', 'rg2_etxd2', ''], ['73', 'rg2_etxd3', ''], ['74', 'rg2_erxck', ''], ['75', 'rg2_erxerr', ''], ['76', 'rg2_erxdv', ''], ['77', 'rg2_emdc', ''], ['78', 'rg2_emdio', ''], ['79', 'rg2_etxen', ''], ['80', 'rg2_etxck', ''], ['81', 'rg2_ecrs', ''], ['82', 'rg2_ecol', ''], ['83', 'rg2_etxerr', ''], ['84', 'vsse_4', ''], ['85', 'vdde_4', ''], ['86', 'rg1_erxd0', ''], ['87', 'rg1_erxd1', ''], ['88', 'rg1_erxd2', ''], ['89', 'rg1_erxd3', ''], ['90', 'rg1_etxd0', ''], ['91', 'rg1_etxd1', ''], ['92', 'rg1_etxd2', ''], ['93', 'rg1_etxd3', ''], ['94', 'rg1_erxck', ''], ['95', 'rg1_erxerr', ''], ['96', 'rg1_erxdv', ''], ['97', 'rg1_emdc', ''], ['98', 'rg1_emdio', ''], ['99', 'rg1_etxen', ''], ['100', 'rg1_etxck', ''], ['101', 'rg1_ecrs', ''], ['102', 'rg1_ecol', ''], ['103', 'rg1_etxerr', ''], ['104', 'vsse_4', ''], ['105', 'vdde_4', ''], ['106', 'rg0_erxd0', ''], ['107', 'rg0_erxd1', ''], ['108', 'rg0_erxd2', ''], ['109', 'rg0_erxd3', ''], ['110', 'rg0_etxd0', ''], ['111', 'rg0_etxd1', ''], ['112', 'rg0_etxd2', ''], ['113', 'rg0_etxd3', ''], ['114', 'rg0_erxck', ''], ['115', 'rg0_erxerr', ''], ['116', 'rg0_erxdv', ''], ['117', 'rg0_emdc', ''], ['118', 'rg0_emdio', ''], ['119', 'rg0_etxen', ''], ['120', 'rg0_etxck', ''], ['121', 'rg0_ecrs', ''], ['122', 'rg0_ecol', ''], ['123', 'rg0_etxerr', ''], ['124', 'vssi_4', ''], ['125', 'vddi_4', ''], ['127', 'sys_pllvcout', ''], ['132', 'vdde_2', ''], ['133', 'vsse_2', ''], ['134', 'vddi_2', ''], ['135', 'vssi_2', ''], ['152', 'rg4_erxd0', ''], ['153', 'rg4_erxd1', ''], ['154', 'rg4_erxd2', ''], ['155', 'rg4_erxd3', ''], ['156', 'rg4_etxd0', ''], ['157', 'rg4_etxd1', ''], ['158', 'rg4_etxd2', ''], ['159', 'rg4_etxd3', ''], ['160', 'rg4_erxck', ''], ['161', 'rg4_erxerr', ''], ['162', 'rg4_erxdv', ''], ['163', 'rg4_emdc', ''], ['164', 'rg4_emdio', ''], ['165', 'rg4_etxen', ''], ['166', 'rg4_etxck', ''], ['167', 'rg4_ecrs', ''], ['168', 'rg4_ecol', ''], ['169', 'rg4_etxerr', ''], ['172', 'rg3_erxd0', ''], ['173', 'rg3_erxd1', ''], ['174', 'rg3_erxd2', ''], ['175', 'rg3_erxd3', ''], ['176', 'rg3_etxd0', ''], ['177', 'rg3_etxd1', ''], ['178', 'rg3_etxd2', ''], ['179', 'rg3_etxd3', ''], ['180', 'rg3_erxck', ''], ['181', 'rg3_erxerr', ''], ['182', 'rg3_erxdv', ''], ['183', 'rg3_emdc', ''], ['184', 'rg3_emdio', ''], ['185', 'rg3_etxen', ''], ['186', 'rg3_etxck', ''], ['187', 'rg3_ecrs', ''], ['188', 'rg3_ecol', ''], ['189', 'rg3_etxerr', ''], ['192', 'vddi_0', ''], ['193', 'vssi_0', ''], ['194', 'vdde_0', ''], ['195', 'vsse_0', ''], ['196', 'ulpi0_ck', ''], ['197', 'ulpi0_dir', ''], ['198', 'ulpi0_stp', ''], ['199', 'ulpi0_nxt', ''], ['200', 'ulpi0_d0', ''], ['201', 'ulpi0_d1', ''], ['202', 'ulpi0_d2', ''], ['203', 'ulpi0_d3', ''], ['204', 'ulpi0_d4', ''], ['205', 'ulpi0_d5', ''], ['206', 'ulpi0_d6', ''], ['207', 'ulpi0_d7', ''], ['208', 'vddi_1', ''], ['209', 'vssi_1', ''], ['210', 'ulpi1_ck', ''], ['211', 'ulpi1_dir', ''], ['212', 'ulpi1_stp', ''], ['213', 'ulpi1_nxt', ''], ['214', 'ulpi1_d0', ''], ['215', 'ulpi1_d1', ''], ['216', 'ulpi1_d2', ''], ['217', 'ulpi1_d3', ''], ['218', 'ulpi1_d4', ''], ['219', 'ulpi1_d5', ''], ['220', 'ulpi1_d6', ''], ['221', 'ulpi1_d7', ''], ['222', 'vdde_1', ''], ['223', 'vsse_1', ''], ['224', 'uart0_tx', ''], ['225', 'uart0_rx', ''], ['226', 'vddi_2', ''], ['227', 'vssi_2', ''], ['228', 'eint_0', ''], ['229', 'eint_1', ''], ['230', 'eint_2', ''], ['234', 'vdde_2', ''], ['235', 'vsse_2', ''], ['236', 'gpiow_w0', ''], ['237', 'gpiow_w1', ''], ['238', 'gpiow_w2', ''], ['239', 'gpiow_w3', ''], ['240', 'gpiow_w4', ''], ['241', 'gpiow_w5', ''], ['242', 'gpiow_w6', ''], ['243', 'gpiow_w7', ''], ['244', 'gpiow_w8', ''], ['245', 'gpiow_w9', ''], ['246', 'gpiow_w10', ''], ['247', 'gpiow_w11', ''], ['248', 'gpiow_w12', ''], ['249', 'gpiow_w13', ''], ['250', 'gpiow_w14', ''], ['251', 'gpiow_w15', ''], ['252', 'vddi_3', ''], ['253', 'vssi_3', ''], ['254', 'vdde_3', ''], ['255', 'vsse_3', '']])
('muxed cell banks', ['N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'N', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'E', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'S', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W', 'W'])
('cell', ['0', 'vsse_0', ''], 'N')
('bank', 'N', 0, 'padname', 'vsse_0', 0, '')
('cell', ['1', 'vdde_0', ''], 'N')
('bank', 'N', 1, 'padname', 'vdde_0', 1, '')
('cell', ['2', 'vddi_0', ''], 'N')
('bank', 'N', 2, 'padname', 'vddi_0', 2, '')
Traceback (most recent call last):
  File "src/pinmux_generator.py", line 101, in <module>
    pm, chip = jsoncreate.pinparse(ps, pinspec)
  File "/home/ghostmansd/src/soc/pinmux/src/jsoncreate.py", line 217, in pinparse
    padbank[banknum] = name
IndexError: list assignment index out of range
make: *** [Makefile:10: mkpinmux] Error 1