20130515_DigitalDesign_Test

module counter(input ck,re,output [7:0]seg,led);

reg [24:0]div;
reg [2:0]count ;
reg ck_1;


always @(posedge ck,negedge re)
begin
    if(!re) begin div <= 0 ; ck_1 <= 0 ; end
    else if(div == 24999999) begin div <= 0 ; ck_1 <= ~ck_1 ; end
    else div <= div + 1 ;
end

always @(posedge ck_1,negedge re)
begin
    if(!re) count <= 3'b111 ;
    else if(count == 0) count <= 3'b111;
    else count <= count - 1 ;
end

assign led[7:0] = (count==0) ? 8'b11111110 :
                  (count==1) ? 8'b11111101 :
                  (count==2) ? 8'b11111011 :
                  (count==3) ? 8'b11110111 :
                  (count==4) ? 8'b11101111 :
                  (count==5) ? 8'b11011111 :
                  (count==6) ? 8'b10111111 :
                  8'b01111111 ;

assign seg[7:0] = (count==0) ? 8'b00000010 :
                  (count==1) ? 8'b10011110 :
                  (count==2) ? 8'b00100100 :
                  (count==3) ? 8'b00001100 :
                  (count==4) ? 8'b10011000 :
                  (count==5) ? 8'b01001000 :
                  (count==6) ? 8'b01000000 :
                  8'b00011110 ;



endmodule