08jun17

*module teste(a,b,sel,out);

input a,b,sel;
output out;

assing out = (sel & a) | (~ sel & b);

endmodule;

====================[

VERILOG

*module teste (SW,LEDR);

input [2:0] SW;
output [0:0] LEDR;

assing LEDR[0] = (SW[O] & SW[1]) | (~ SW[0] & SW[2]);

endmodule;


====================[

VERILOG 2


*module teste (SW,LEDR);

input [2:0] SW;
output [0:0] LEDR;

reg saida; // reg LEDR[0]

always @ (1)    //(O que tiver dentro do parenteses for verdadeiro faça [1] autoriza)

begin
if (SW[0] == 0)
    begin
        saida = SW[2];
    end
    else if (SW[0] == 1)
    begin
        saida = SW[1];
    end
end

assign LEDR[0] = saida; //LEDR[0] = bit de saida

endmodule


====================[


VERILOG 3


module teste (SW,LEDR);

input [2:0] SW;
output [0:0] LEDR;
reg soma, co;

always @ (1)
begin
soma = SW[0]^SW[1]^SW[2];
co = SW[0]&SW[1] | SW[0] & SW[2] | SW[1] & SW[2];
end

assign LEDR = {co,soma};

endmodule