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stm8 UART code

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Feb 25th, 2021
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  1. //FCPU = 2mhz and baudrate =9600, so 0x0C on BRR2 and BRR1
  2. void uart_init(void)
  3. {
  4. /*clock enable for UART and GPIO peripheral is set by default */
  5.  
  6. //PD5-Tx, PD6-RX
  7. // Set Tx pin as output pushpull
  8. GPIOD-> DDR |= (1<<5);
  9. GPIOD-> CR1 |= ((1<<5));
  10.  
  11. //Set Rx pin as Input floating
  12. /*by default all pins are input floating only*/
  13.  
  14. // Clear the Idle Line Detected bit in the status register by a read
  15. // to the UART1_SR register followed by a write to the UART1_DR register.
  16. uint8_t tmp;
  17. tmp = UART1->SR;
  18. UART1->DR = tmp;
  19.  
  20. //Reset the UART registers
  21. UART1_SR_RESET_VALUE;
  22. UART1_CR1_RESET_VALUE;
  23. UART1_CR2_RESET_VALUE;
  24. UART1_CR3_RESET_VALUE;
  25. UART1_BRR2_RESET_VALUE;
  26. UART1_BRR1_RESET_VALUE;
  27.  
  28. //disable TE and RE
  29. UART1-> CR2 &= (~((1<<3)|(1<<2)));
  30. //Set word legth :8 bit,1 startbit
  31. UART1-> CR1 &= (~(1<<4));
  32. //Parity disable
  33. UART1-> CR1 &= (~(1<<2));
  34. //UART stop bit: 1
  35. UART1-> CR3 &= (~(1<<5)|(1<<4));
  36.  
  37. //UART_baudrate
  38. UART1 ->BRR2 = 0x0C;
  39. UART1 ->BRR1 = 0x0C;
  40. //Word length : by default it is 8 data bits
  41.  
  42. //enable UART1 , Bit 5 of CR1
  43. UART1-> CR1 |= (1<<5);
  44.  
  45. //Transmitter enable, TE bit is at 3 of CR2
  46. UART1-> CR2 |= ((1<<3)|(1<<2));
  47. //Receiver enable, RE bit is at 2 of CR2
  48. //UART1-> CR2 |= (1<<2);
  49.  
  50. }
  51. void uart_transmit_byte(uint8_t byte)
  52. {
  53.  
  54. //write single byte to DATA register as TDR register is empty now
  55. //UART1->DR = byte;
  56. //UART1->DR = byte;
  57. while(!(UART1->SR & UART1_SR_TXE));
  58. UART1->DR = byte;
  59. while(!(UART1->SR & UART1_SR_TC));
  60. // wait till TDR register move byte to shift regster
  61. //while(!(USART2->SR & USART_SR_TXE));
  62.  
  63. //wait for transmission to complete
  64. //while(!(USART2->SR & USART_SR_TXE));
  65. //USART2->SR &= ~USART_SR_TXE;
  66.  
  67. }
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