diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 06a90438838e..50c36e3a5aad 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1653,6 +1653,17 @@ def : Pat<(trap), (UNIMP)>;
 // debugger if possible.
 def : Pat<(debugtrap), (EBREAK)>;

+// FIXME: replace GRP with other GPR class which excludes X6, X7, X28, X5 as ARM did
+let Predicates = [IsRV64], Uses = [ X5 ],
+    Defs = [ X1, X6, X7, X28, X29, X30, X31 ] in {
+def HWASAN_CHECK_MEMACCESS : Pseudo<
+ (outs), (ins GPRNoX1X6X7X28X29X30X31:$ptr, i32imm:$accessinfo),
+ [(int_hwasan_check_memaccess X5, GPRNoX1X6X7X28X29X30X31:$ptr, (i32 timm:$accessinfo))]>;
+def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
+ (outs), (ins GPRNoX1X6X7X28X29X30X31:$ptr, i32imm:$accessinfo),
+ [(int_hwasan_check_memaccess_shortgranules X5, GPRNoX1X6X7X28X29X30X31:$ptr , (i32 timm:$accessinfo))]>;
+}
+
 /// Simple optimization
 def : Pat<(add GPR:$rs1, (AddiPair:$rs2)),
           (ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 4ff60ebda5aa..e614c5fff347 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -146,6 +146,10 @@ def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X0, X2)> {
   let RegInfos = XLenRI;
 }

+def GPRNoX1X6X7X28X29X30X31 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X1, X6, X7, X28, X29, X30, X30)> {
+  let RegInfos = XLenRI;
+}
+
 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
 // stack on some microarchitectures. Also remove the reserved registers X0, X2,
 // X3, and X4 as it reduces the number of register classes that get synthesized