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plt1065g.dts

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Jan 5th, 2017
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. compatible = "rockchip,rk3126";
  7. rockchip,sram = <0x1>;
  8. interrupt-parent = <0x2>;
  9.  
  10. chosen {
  11. bootargs = "vmalloc=496M cma=4M rockchip_jtag";
  12. };
  13.  
  14. aliases {
  15. serial0 = "/serial@20060000";
  16. serial1 = "/serial@20064000";
  17. serial2 = "/serial@20068000";
  18. i2c0 = "/i2c@20072000";
  19. i2c1 = "/i2c@20056000";
  20. i2c2 = "/i2c@2005a000";
  21. i2c3 = "/i2c@2005e000";
  22. lcdc = "/lcdc@1010e000";
  23. spi0 = "/spi@20074000";
  24. };
  25.  
  26. memory {
  27. device_type = "memory";
  28. reg = <0x0 0x0>;
  29. };
  30.  
  31. clocks {
  32. compatible = "rockchip,rk-clocks";
  33. #address-cells = <0x1>;
  34. #size-cells = <0x1>;
  35. ranges = <0x0 0x20000000 0x1f0>;
  36.  
  37. fixed_rate_cons {
  38. compatible = "rockchip,rk-fixed-rate-cons";
  39.  
  40. xin24m {
  41. compatible = "rockchip,rk-fixed-clock";
  42. clock-output-names = "xin24m";
  43. clock-frequency = <0x16e3600>;
  44. #clock-cells = <0x0>;
  45. linux,phandle = <0x3>;
  46. phandle = <0x3>;
  47. };
  48.  
  49. xin12m {
  50. compatible = "rockchip,rk-fixed-clock";
  51. clocks = <0x3>;
  52. clock-output-names = "xin12m";
  53. clock-frequency = <0xb71b00>;
  54. #clock-cells = <0x0>;
  55. linux,phandle = <0x19>;
  56. phandle = <0x19>;
  57. };
  58.  
  59. gmac_clkin {
  60. compatible = "rockchip,rk-fixed-clock";
  61. clock-output-names = "gmac_clkin";
  62. clock-frequency = <0x7735940>;
  63. #clock-cells = <0x0>;
  64. linux,phandle = <0x1e>;
  65. phandle = <0x1e>;
  66. };
  67.  
  68. usb480m {
  69. compatible = "rockchip,rk-fixed-clock";
  70. clock-output-names = "usb480m";
  71. clock-frequency = <0x1c9c3800>;
  72. #clock-cells = <0x0>;
  73. linux,phandle = <0x2c>;
  74. phandle = <0x2c>;
  75. };
  76.  
  77. i2s_clkin {
  78. compatible = "rockchip,rk-fixed-clock";
  79. clock-output-names = "i2s_clkin";
  80. clock-frequency = <0x0>;
  81. #clock-cells = <0x0>;
  82. linux,phandle = <0x18>;
  83. phandle = <0x18>;
  84. };
  85.  
  86. jtag_tck {
  87. compatible = "rockchip,rk-fixed-clock";
  88. clock-output-names = "jtag_tck";
  89. clock-frequency = <0x0>;
  90. #clock-cells = <0x0>;
  91. linux,phandle = <0x3f>;
  92. phandle = <0x3f>;
  93. };
  94.  
  95. pclkin_cif {
  96. compatible = "rockchip,rk-fixed-clock";
  97. clock-output-names = "pclkin_cif";
  98. clock-frequency = <0x0>;
  99. #clock-cells = <0x0>;
  100. linux,phandle = <0x3a>;
  101. phandle = <0x3a>;
  102. };
  103.  
  104. clk_tsp_in {
  105. compatible = "rockchip,rk-fixed-clock";
  106. clock-output-names = "clk_tsp_in";
  107. clock-frequency = <0x0>;
  108. #clock-cells = <0x0>;
  109. linux,phandle = <0x4c>;
  110. phandle = <0x4c>;
  111. };
  112.  
  113. dummy {
  114. compatible = "rockchip,rk-fixed-clock";
  115. clock-output-names = "dummy";
  116. clock-frequency = <0x0>;
  117. #clock-cells = <0x0>;
  118. linux,phandle = <0x4>;
  119. phandle = <0x4>;
  120. };
  121.  
  122. dummy_cpll {
  123. compatible = "rockchip,rk-fixed-clock";
  124. clock-output-names = "dummy_cpll";
  125. clock-frequency = <0x0>;
  126. #clock-cells = <0x0>;
  127. };
  128. };
  129.  
  130. fixed_factor_cons {
  131. compatible = "rockchip,rk-fixed-factor-cons";
  132.  
  133. clk_gpll_div2 {
  134. compatible = "rockchip,rk-fixed-factor-clock";
  135. clocks = <0x4>;
  136. clock-output-names = "clk_gpll_div2";
  137. clock-div = <0x2>;
  138. clock-mult = <0x1>;
  139. #clock-cells = <0x0>;
  140. linux,phandle = <0xe>;
  141. phandle = <0xe>;
  142. };
  143.  
  144. clk_gpll_div3 {
  145. compatible = "rockchip,rk-fixed-factor-clock";
  146. clocks = <0x4>;
  147. clock-output-names = "clk_gpll_div3";
  148. clock-div = <0x3>;
  149. clock-mult = <0x1>;
  150. #clock-cells = <0x0>;
  151. linux,phandle = <0x11>;
  152. phandle = <0x11>;
  153. };
  154.  
  155. g_clk_pvtm_func {
  156. compatible = "rockchip,rk-fixed-factor-clock";
  157. clocks = <0x3>;
  158. clock-output-names = "g_clk_pvtm_func";
  159. clock-div = <0x1>;
  160. clock-mult = <0x1>;
  161. #clock-cells = <0x0>;
  162. linux,phandle = <0x12>;
  163. phandle = <0x12>;
  164. };
  165.  
  166. hclk_vepu {
  167. compatible = "rockchip,rk-fixed-factor-clock";
  168. clocks = <0x5>;
  169. clock-output-names = "hclk_vepu";
  170. clock-div = <0x4>;
  171. clock-mult = <0x1>;
  172. #clock-cells = <0x0>;
  173. };
  174.  
  175. hclk_vdpu {
  176. compatible = "rockchip,rk-fixed-factor-clock";
  177. clocks = <0x6>;
  178. clock-output-names = "hclk_vdpu";
  179. clock-div = <0x4>;
  180. clock-mult = <0x1>;
  181. #clock-cells = <0x0>;
  182. linux,phandle = <0x45>;
  183. phandle = <0x45>;
  184. };
  185.  
  186. pclkin_cif_inv {
  187. compatible = "rockchip,rk-fixed-factor-clock";
  188. clocks = <0x7 0x3>;
  189. clock-output-names = "pclkin_cif_inv";
  190. clock-div = <0x1>;
  191. clock-mult = <0x1>;
  192. #clock-cells = <0x0>;
  193. linux,phandle = <0x3b>;
  194. phandle = <0x3b>;
  195. };
  196.  
  197. hclk_vio_niu {
  198. compatible = "rockchip,rk-fixed-factor-clock";
  199. clocks = <0x8>;
  200. clock-output-names = "hclk_vio_niu";
  201. clock-div = <0x1>;
  202. clock-mult = <0x1>;
  203. #clock-cells = <0x0>;
  204. linux,phandle = <0x49>;
  205. phandle = <0x49>;
  206. };
  207.  
  208. aclk_vio0_niu {
  209. compatible = "rockchip,rk-fixed-factor-clock";
  210. clocks = <0x9>;
  211. clock-output-names = "aclk_vio0_niu";
  212. clock-div = <0x1>;
  213. clock-mult = <0x1>;
  214. #clock-cells = <0x0>;
  215. linux,phandle = <0x48>;
  216. phandle = <0x48>;
  217. };
  218.  
  219. aclk_vio1_niu {
  220. compatible = "rockchip,rk-fixed-factor-clock";
  221. clocks = <0xa>;
  222. clock-output-names = "aclk_vio1_niu";
  223. clock-div = <0x1>;
  224. clock-mult = <0x1>;
  225. #clock-cells = <0x0>;
  226. linux,phandle = <0x4b>;
  227. phandle = <0x4b>;
  228. };
  229. };
  230.  
  231. pd_cons {
  232. compatible = "rockchip,rk-pd-cons";
  233.  
  234. pd_gpu {
  235. compatible = "rockchip,rk-pd-clock";
  236. clock-output-names = "pd_gpu";
  237. rockchip,pd-id = <0x8>;
  238. #clock-cells = <0x0>;
  239. };
  240.  
  241. pd_video {
  242. compatible = "rockchip,rk-pd-clock";
  243. clock-output-names = "pd_video";
  244. rockchip,pd-id = <0xc>;
  245. #clock-cells = <0x0>;
  246. };
  247.  
  248. pd_vio {
  249. compatible = "rockchip,rk-pd-clock";
  250. clock-output-names = "pd_vio";
  251. rockchip,pd-id = <0xd>;
  252. #clock-cells = <0x0>;
  253. linux,phandle = <0xb>;
  254. phandle = <0xb>;
  255. };
  256.  
  257. pd_vop {
  258. compatible = "rockchip,rk-pd-clock";
  259. clocks = <0xb>;
  260. clock-output-names = "pd_vop";
  261. rockchip,pd-id = <0xff>;
  262. #clock-cells = <0x0>;
  263. linux,phandle = <0x9e>;
  264. phandle = <0x9e>;
  265. };
  266.  
  267. pd_vip {
  268. compatible = "rockchip,rk-pd-clock";
  269. clocks = <0xb>;
  270. clock-output-names = "pd_vip";
  271. rockchip,pd-id = <0xff>;
  272. #clock-cells = <0x0>;
  273. linux,phandle = <0xaa>;
  274. phandle = <0xaa>;
  275. };
  276.  
  277. pd_iep {
  278. compatible = "rockchip,rk-pd-clock";
  279. clocks = <0xb>;
  280. clock-output-names = "pd_iep";
  281. rockchip,pd-id = <0xff>;
  282. #clock-cells = <0x0>;
  283. };
  284.  
  285. pd_rga {
  286. compatible = "rockchip,rk-pd-clock";
  287. clocks = <0xb>;
  288. clock-output-names = "pd_rga";
  289. rockchip,pd-id = <0xff>;
  290. #clock-cells = <0x0>;
  291. };
  292.  
  293. pd_ebc {
  294. compatible = "rockchip,rk-pd-clock";
  295. clocks = <0xb>;
  296. clock-output-names = "pd_ebc";
  297. rockchip,pd-id = <0xff>;
  298. #clock-cells = <0x0>;
  299. };
  300.  
  301. pd_mipidsi {
  302. compatible = "rockchip,rk-pd-clock";
  303. clocks = <0xb>;
  304. clock-output-names = "pd_mipidsi";
  305. rockchip,pd-id = <0xff>;
  306. #clock-cells = <0x0>;
  307. linux,phandle = <0x84>;
  308. phandle = <0x84>;
  309. };
  310.  
  311. pd_hdmi {
  312. compatible = "rockchip,rk-pd-clock";
  313. clocks = <0xb>;
  314. clock-output-names = "pd_hdmi";
  315. rockchip,pd-id = <0xff>;
  316. #clock-cells = <0x0>;
  317. linux,phandle = <0xa7>;
  318. phandle = <0xa7>;
  319. };
  320. };
  321.  
  322. clock_regs {
  323. compatible = "rockchip,rk-clock-regs";
  324. #address-cells = <0x1>;
  325. #size-cells = <0x1>;
  326. reg = <0x0 0x1f0>;
  327. ranges;
  328.  
  329. pll_cons {
  330. compatible = "rockchip,rk-pll-cons";
  331. #address-cells = <0x1>;
  332. #size-cells = <0x1>;
  333. ranges;
  334.  
  335. pll-clk@0000 {
  336. compatible = "rockchip,rk3188-pll-clk";
  337. reg = <0x0 0x10>;
  338. mode-reg = <0x40 0x0>;
  339. status-reg = <0x4 0xa>;
  340. clocks = <0x3>;
  341. clock-output-names = "clk_apll";
  342. rockchip,pll-type = <0x40>;
  343. #clock-cells = <0x0>;
  344. linux,phandle = <0xd>;
  345. phandle = <0xd>;
  346. };
  347.  
  348. pll-clk@0010 {
  349. compatible = "rockchip,rk3188-pll-clk";
  350. reg = <0x10 0x10>;
  351. mode-reg = <0x40 0x4>;
  352. status-reg = <0x14 0xa>;
  353. clocks = <0x3>;
  354. clock-output-names = "clk_dpll";
  355. rockchip,pll-type = <0x80>;
  356. #clock-cells = <0x0>;
  357. linux,phandle = <0x35>;
  358. phandle = <0x35>;
  359. };
  360.  
  361. pll-clk@0020 {
  362. compatible = "rockchip,rk3188-pll-clk";
  363. reg = <0x20 0x10>;
  364. mode-reg = <0x40 0x8>;
  365. status-reg = <0x24 0xa>;
  366. clocks = <0x3>;
  367. clock-output-names = "clk_cpll";
  368. rockchip,pll-type = <0x100>;
  369. #clock-cells = <0x0>;
  370. #clock-init-cells = <0x1>;
  371. linux,phandle = <0x14>;
  372. phandle = <0x14>;
  373. };
  374.  
  375. pll-clk@0030 {
  376. compatible = "rockchip,rk3188-pll-clk";
  377. reg = <0x30 0x10>;
  378. mode-reg = <0x40 0xc>;
  379. status-reg = <0x34 0xa>;
  380. clocks = <0x3>;
  381. clock-output-names = "clk_gpll";
  382. rockchip,pll-type = <0x80>;
  383. #clock-cells = <0x0>;
  384. #clock-init-cells = <0x1>;
  385. linux,phandle = <0x10>;
  386. phandle = <0x10>;
  387. };
  388. };
  389.  
  390. clk_sel_cons {
  391. compatible = "rockchip,rk-sel-cons";
  392. #address-cells = <0x1>;
  393. #size-cells = <0x1>;
  394. ranges;
  395.  
  396. sel-con@0044 {
  397. compatible = "rockchip,rk3188-selcon";
  398. reg = <0x44 0x4>;
  399. #address-cells = <0x1>;
  400. #size-cells = <0x1>;
  401.  
  402. clk_core_div {
  403. compatible = "rockchip,rk3188-div-con";
  404. rockchip,bits = <0x0 0x5>;
  405. clocks = <0xc>;
  406. clock-output-names = "clk_core";
  407. rockchip,div-type = <0x0>;
  408. #clock-cells = <0x0>;
  409. rockchip,clkops-idx = <0xb>;
  410. rockchip,flags = <0xc0>;
  411. };
  412.  
  413. clk_core_mux {
  414. compatible = "rockchip,rk3188-mux-con";
  415. rockchip,bits = <0x7 0x1>;
  416. clocks = <0xd 0xe>;
  417. clock-output-names = "clk_core";
  418. #clock-cells = <0x0>;
  419. #clock-init-cells = <0x1>;
  420. linux,phandle = <0xc>;
  421. phandle = <0xc>;
  422. };
  423.  
  424. aclk_cpu_div {
  425. compatible = "rockchip,rk3188-div-con";
  426. rockchip,bits = <0x8 0x5>;
  427. clocks = <0xf>;
  428. clock-output-names = "aclk_cpu";
  429. rockchip,div-type = <0x0>;
  430. #clock-cells = <0x0>;
  431. rockchip,clkops-idx = <0x1>;
  432. rockchip,flags = <0x80>;
  433. };
  434.  
  435. aclk_cpu_mux {
  436. compatible = "rockchip,rk3188-mux-con";
  437. rockchip,bits = <0xd 0x2>;
  438. clocks = <0xd 0x10 0xe 0x11>;
  439. clock-output-names = "aclk_cpu";
  440. #clock-cells = <0x0>;
  441. #clock-init-cells = <0x1>;
  442. linux,phandle = <0xf>;
  443. phandle = <0xf>;
  444. };
  445. };
  446.  
  447. sel-con@0048 {
  448. compatible = "rockchip,rk3188-selcon";
  449. reg = <0x48 0x4>;
  450. #address-cells = <0x1>;
  451. #size-cells = <0x1>;
  452.  
  453. pclk_dbg_div {
  454. compatible = "rockchip,rk3188-div-con";
  455. rockchip,bits = <0x0 0x4>;
  456. clocks = <0xc>;
  457. clock-output-names = "pclk_dbg";
  458. rockchip,div-type = <0x0>;
  459. #clock-cells = <0x0>;
  460. rockchip,clkops-idx = <0xc>;
  461. };
  462.  
  463. aclk_core_pre_div {
  464. compatible = "rockchip,rk3188-div-con";
  465. rockchip,bits = <0x4 0x3>;
  466. clocks = <0xc>;
  467. clock-output-names = "aclk_core_pre";
  468. rockchip,div-type = <0x0>;
  469. #clock-cells = <0x0>;
  470. rockchip,clkops-idx = <0xc>;
  471. };
  472.  
  473. hclk_cpu_pre_div {
  474. compatible = "rockchip,rk3188-div-con";
  475. rockchip,bits = <0x8 0x2>;
  476. clocks = <0xf>;
  477. clock-output-names = "hclk_cpu_pre";
  478. rockchip,div-type = <0x0>;
  479. #clock-cells = <0x0>;
  480. #clock-init-cells = <0x1>;
  481. linux,phandle = <0x42>;
  482. phandle = <0x42>;
  483. };
  484.  
  485. pclk_cpu_pre_div {
  486. compatible = "rockchip,rk3188-div-con";
  487. rockchip,bits = <0xc 0x3>;
  488. clocks = <0xf>;
  489. clock-output-names = "pclk_cpu_pre";
  490. rockchip,div-type = <0x0>;
  491. #clock-cells = <0x0>;
  492. #clock-init-cells = <0x1>;
  493. linux,phandle = <0x44>;
  494. phandle = <0x44>;
  495. };
  496. };
  497.  
  498. sel-con@004c {
  499. compatible = "rockchip,rk3188-selcon";
  500. reg = <0x4c 0x4>;
  501. #address-cells = <0x1>;
  502. #size-cells = <0x1>;
  503.  
  504. clk_pvtm_div {
  505. compatible = "rockchip,rk3188-mux-con";
  506. rockchip,bits = <0x0 0x7>;
  507. clocks = <0x12>;
  508. clock-output-names = "clk_pvtm";
  509. rockchip,div-type = <0x0>;
  510. #clock-cells = <0x0>;
  511. #clock-init-cells = <0x1>;
  512. };
  513.  
  514. clk_nandc_div {
  515. compatible = "rockchip,rk3188-div-con";
  516. rockchip,bits = <0x8 0x5>;
  517. clocks = <0x13>;
  518. clock-output-names = "clk_nandc";
  519. rockchip,div-type = <0x0>;
  520. #clock-cells = <0x0>;
  521. rockchip,clkops-idx = <0x1>;
  522. };
  523.  
  524. clk_nandc_mux {
  525. compatible = "rockchip,rk3188-mux-con";
  526. rockchip,bits = <0xe 0x2>;
  527. clocks = <0x14 0x10 0xe>;
  528. clock-output-names = "clk_nandc";
  529. #clock-cells = <0x0>;
  530. #clock-init-cells = <0x1>;
  531. linux,phandle = <0x13>;
  532. phandle = <0x13>;
  533. };
  534. };
  535.  
  536. sel-con@0050 {
  537. compatible = "rockchip,rk3188-selcon";
  538. reg = <0x50 0x4>;
  539. #address-cells = <0x1>;
  540. #size-cells = <0x1>;
  541.  
  542. clk_i2s_2ch_pll_div {
  543. compatible = "rockchip,rk3188-div-con";
  544. rockchip,bits = <0x0 0x7>;
  545. clocks = <0x15>;
  546. clock-output-names = "clk_i2s_2ch_pll";
  547. rockchip,div-type = <0x0>;
  548. #clock-cells = <0x0>;
  549. rockchip,clkops-idx = <0x1>;
  550. rockchip,flags = <0x80>;
  551. linux,phandle = <0x16>;
  552. phandle = <0x16>;
  553. };
  554.  
  555. clk_i2s_2ch_mux {
  556. compatible = "rockchip,rk3188-mux-con";
  557. rockchip,bits = <0x8 0x2>;
  558. clocks = <0x16 0x17 0x18 0x19>;
  559. clock-output-names = "clk_i2s_2ch";
  560. #clock-cells = <0x0>;
  561. rockchip,clkops-idx = <0xe>;
  562. rockchip,flags = <0x4>;
  563. linux,phandle = <0x1a>;
  564. phandle = <0x1a>;
  565. };
  566.  
  567. clk_i2s_2ch_out_mux {
  568. compatible = "rockchip,rk3188-mux-con";
  569. rockchip,bits = <0xc 0x1>;
  570. clocks = <0x1a 0x19>;
  571. clock-output-names = "i2s_clkout";
  572. #clock-cells = <0x0>;
  573. linux,phandle = <0x3e>;
  574. phandle = <0x3e>;
  575. };
  576.  
  577. i2s_2ch_pll_mux {
  578. compatible = "rockchip,rk3188-mux-con";
  579. rockchip,bits = <0xe 0x2>;
  580. clocks = <0x14 0x10 0xe>;
  581. clock-output-names = "clk_i2s_2ch_pll";
  582. #clock-cells = <0x0>;
  583. #clock-init-cells = <0x1>;
  584. linux,phandle = <0x15>;
  585. phandle = <0x15>;
  586. };
  587. };
  588.  
  589. sel-con@0054 {
  590. compatible = "rockchip,rk3188-selcon";
  591. reg = <0x54 0x4>;
  592. #address-cells = <0x1>;
  593. #size-cells = <0x1>;
  594.  
  595. clk_tsp_div {
  596. compatible = "rockchip,rk3188-div-con";
  597. rockchip,bits = <0x0 0x5>;
  598. clocks = <0x1b>;
  599. clock-output-names = "clk_tsp";
  600. rockchip,div-type = <0x0>;
  601. #clock-cells = <0x0>;
  602. rockchip,clkops-idx = <0x1>;
  603. };
  604.  
  605. clk_tsp_mux {
  606. compatible = "rockchip,rk3188-mux-con";
  607. rockchip,bits = <0x6 0x2>;
  608. clocks = <0x14 0x10 0xe>;
  609. clock-output-names = "clk_tsp";
  610. #clock-cells = <0x0>;
  611. #clock-init-cells = <0x1>;
  612. linux,phandle = <0x1b>;
  613. phandle = <0x1b>;
  614. };
  615.  
  616. clk_24m_div {
  617. compatible = "rockchip,rk3188-div-con";
  618. rockchip,bits = <0x8 0x5>;
  619. clocks = <0x3>;
  620. clock-output-names = "clk_24m";
  621. rockchip,div-type = <0x0>;
  622. #clock-cells = <0x0>;
  623. };
  624. };
  625.  
  626. sel-con@0058 {
  627. compatible = "rockchip,rk3188-selcon";
  628. reg = <0x58 0x4>;
  629. #address-cells = <0x1>;
  630. #size-cells = <0x1>;
  631.  
  632. clk_mac_pll_div {
  633. compatible = "rockchip,rk3188-div-con";
  634. rockchip,bits = <0x0 0x5>;
  635. clocks = <0x1c>;
  636. clock-output-names = "clk_mac_pll";
  637. rockchip,div-type = <0x0>;
  638. #clock-cells = <0x0>;
  639. rockchip,clkops-idx = <0x1>;
  640. #clock-init-cells = <0x1>;
  641. linux,phandle = <0x1d>;
  642. phandle = <0x1d>;
  643. };
  644.  
  645. clk_mac_pll_mux {
  646. compatible = "rockchip,rk3188-mux-con";
  647. rockchip,bits = <0x6 0x2>;
  648. clocks = <0x14 0x10 0xe>;
  649. clock-output-names = "clk_mac_pll";
  650. #clock-cells = <0x0>;
  651. #clock-init-cells = <0x1>;
  652. linux,phandle = <0x1c>;
  653. phandle = <0x1c>;
  654. };
  655.  
  656. clk_mac_ref_mux {
  657. compatible = "rockchip,rk3188-mux-con";
  658. rockchip,bits = <0xf 0x1>;
  659. clocks = <0x1d 0x1e>;
  660. clock-output-names = "clk_mac_ref";
  661. #clock-cells = <0x0>;
  662. rockchip,clkops-idx = <0xa>;
  663. rockchip,flags = <0x4>;
  664. #clock-init-cells = <0x1>;
  665. linux,phandle = <0x40>;
  666. phandle = <0x40>;
  667. };
  668. };
  669.  
  670. sel-con@005c {
  671. compatible = "rockchip,rk3188-selcon";
  672. reg = <0x5c 0x4>;
  673. #address-cells = <0x1>;
  674. #size-cells = <0x1>;
  675.  
  676. spdif_div {
  677. compatible = "rockchip,rk3188-div-con";
  678. rockchip,bits = <0x0 0x7>;
  679. clocks = <0x1f>;
  680. clock-output-names = "clk_spdif_pll";
  681. rockchip,div-type = <0x0>;
  682. #clock-cells = <0x0>;
  683. rockchip,clkops-idx = <0x1>;
  684. rockchip,flags = <0x80>;
  685. linux,phandle = <0x20>;
  686. phandle = <0x20>;
  687. };
  688.  
  689. spdif_mux {
  690. compatible = "rockchip,rk3188-mux-con";
  691. rockchip,bits = <0x8 0x2>;
  692. clocks = <0x20 0x21 0x19>;
  693. clock-output-names = "clk_spdif";
  694. #clock-cells = <0x0>;
  695. rockchip,clkops-idx = <0xe>;
  696. rockchip,flags = <0x4>;
  697. linux,phandle = <0x82>;
  698. phandle = <0x82>;
  699. };
  700.  
  701. spdif_pll_mux {
  702. compatible = "rockchip,rk3188-mux-con";
  703. rockchip,bits = <0xe 0x2>;
  704. clocks = <0x14 0x10 0xe>;
  705. clock-output-names = "clk_spdif_pll";
  706. #clock-cells = <0x0>;
  707. #clock-init-cells = <0x1>;
  708. linux,phandle = <0x1f>;
  709. phandle = <0x1f>;
  710. };
  711. };
  712.  
  713. sel-con@0060 {
  714. compatible = "rockchip,rk3188-selcon";
  715. reg = <0x60 0x4>;
  716. #address-cells = <0x1>;
  717. #size-cells = <0x1>;
  718.  
  719. i2s_2ch_frac {
  720. compatible = "rockchip,rk3188-frac-con";
  721. clocks = <0x15>;
  722. clock-output-names = "i2s_2ch_frac";
  723. rockchip,bits = <0x0 0x20>;
  724. rockchip,clkops-idx = <0x5>;
  725. #clock-cells = <0x0>;
  726. linux,phandle = <0x17>;
  727. phandle = <0x17>;
  728. };
  729. };
  730.  
  731. sel-con@0064 {
  732. compatible = "rockchip,rk3188-selcon";
  733. reg = <0x64 0x4>;
  734. #address-cells = <0x1>;
  735. #size-cells = <0x1>;
  736.  
  737. i2s_8ch_frac {
  738. compatible = "rockchip,rk3188-frac-con";
  739. clocks = <0x22>;
  740. clock-output-names = "i2s_8ch_frac";
  741. rockchip,bits = <0x0 0x20>;
  742. rockchip,clkops-idx = <0x5>;
  743. #clock-cells = <0x0>;
  744. linux,phandle = <0x24>;
  745. phandle = <0x24>;
  746. };
  747. };
  748.  
  749. sel-con@0068 {
  750. compatible = "rockchip,rk3188-selcon";
  751. reg = <0x68 0x4>;
  752. #address-cells = <0x1>;
  753. #size-cells = <0x1>;
  754.  
  755. clk_i2s_8ch_pll_div {
  756. compatible = "rockchip,rk3188-div-con";
  757. rockchip,bits = <0x0 0x7>;
  758. clocks = <0x22>;
  759. clock-output-names = "clk_i2s_8ch_pll";
  760. rockchip,div-type = <0x0>;
  761. #clock-cells = <0x0>;
  762. rockchip,clkops-idx = <0x1>;
  763. rockchip,flags = <0x80>;
  764. linux,phandle = <0x23>;
  765. phandle = <0x23>;
  766. };
  767.  
  768. clk_i2s_8ch_mux {
  769. compatible = "rockchip,rk3188-mux-con";
  770. rockchip,bits = <0x8 0x2>;
  771. clocks = <0x23 0x24 0x18 0x19>;
  772. clock-output-names = "clk_i2s_8ch";
  773. #clock-cells = <0x0>;
  774. rockchip,clkops-idx = <0xe>;
  775. rockchip,flags = <0x4>;
  776. linux,phandle = <0x47>;
  777. phandle = <0x47>;
  778. };
  779.  
  780. i2s_8ch_pll_mux {
  781. compatible = "rockchip,rk3188-mux-con";
  782. rockchip,bits = <0xe 0x2>;
  783. clocks = <0x14 0x10 0xe>;
  784. clock-output-names = "clk_i2s_8ch_pll";
  785. #clock-cells = <0x0>;
  786. #clock-init-cells = <0x1>;
  787. linux,phandle = <0x22>;
  788. phandle = <0x22>;
  789. };
  790. };
  791.  
  792. sel-con@006c {
  793. compatible = "rockchip,rk3188-selcon";
  794. reg = <0x6c 0x4>;
  795. #address-cells = <0x1>;
  796. #size-cells = <0x1>;
  797.  
  798. aclk_peri_div {
  799. compatible = "rockchip,rk3188-div-con";
  800. rockchip,bits = <0x0 0x5>;
  801. clocks = <0x25>;
  802. clock-output-names = "aclk_peri";
  803. rockchip,div-type = <0x0>;
  804. #clock-cells = <0x0>;
  805. rockchip,clkops-idx = <0x1>;
  806. rockchip,flags = <0x80>;
  807. };
  808.  
  809. hclk_peri_pre_div {
  810. compatible = "rockchip,rk3188-div-con";
  811. rockchip,bits = <0x8 0x2>;
  812. clocks = <0x25>;
  813. clock-output-names = "hclk_peri_pre";
  814. rockchip,div-type = <0x80>;
  815. rockchip,div-relations = <0x0 0x1 0x1 0x2 0x2 0x4>;
  816. #clock-cells = <0x0>;
  817. #clock-init-cells = <0x1>;
  818. linux,phandle = <0x43>;
  819. phandle = <0x43>;
  820. };
  821.  
  822. pclk_peri_div {
  823. compatible = "rockchip,rk3188-div-con";
  824. rockchip,bits = <0xc 0x2>;
  825. clocks = <0x25>;
  826. clock-output-names = "pclk_peri_pre";
  827. rockchip,div-type = <0x80>;
  828. rockchip,div-relations = <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>;
  829. #clock-cells = <0x0>;
  830. #clock-init-cells = <0x1>;
  831. linux,phandle = <0x46>;
  832. phandle = <0x46>;
  833. };
  834.  
  835. aclk_peri_mux {
  836. compatible = "rockchip,rk3188-mux-con";
  837. rockchip,bits = <0xe 0x2>;
  838. clocks = <0x10 0x14 0xe 0x11>;
  839. clock-output-names = "aclk_peri";
  840. #clock-cells = <0x0>;
  841. #clock-init-cells = <0x1>;
  842. linux,phandle = <0x25>;
  843. phandle = <0x25>;
  844. };
  845. };
  846.  
  847. sel-con@0070 {
  848. compatible = "rockchip,rk3188-selcon";
  849. reg = <0x70 0x4>;
  850. #address-cells = <0x1>;
  851. #size-cells = <0x1>;
  852.  
  853. clk_sdmmc0_div {
  854. compatible = "rockchip,rk3188-div-con";
  855. rockchip,bits = <0x0 0x6>;
  856. clocks = <0x26>;
  857. clock-output-names = "clk_sdmmc0";
  858. rockchip,div-type = <0x0>;
  859. #clock-cells = <0x0>;
  860. rockchip,clkops-idx = <0x3>;
  861. };
  862.  
  863. clk_sdmmc0_mux {
  864. compatible = "rockchip,rk3188-mux-con";
  865. rockchip,bits = <0x6 0x2>;
  866. clocks = <0x14 0x10 0xe 0x3>;
  867. clock-output-names = "clk_sdmmc0";
  868. #clock-cells = <0x0>;
  869. #clock-init-cells = <0x1>;
  870. linux,phandle = <0x26>;
  871. phandle = <0x26>;
  872. };
  873.  
  874. clk_sfc_div {
  875. compatible = "rockchip,rk3188-div-con";
  876. rockchip,bits = <0x8 0x5>;
  877. clocks = <0x27>;
  878. clock-output-names = "clk_sfc";
  879. rockchip,div-type = <0x0>;
  880. #clock-cells = <0x0>;
  881. rockchip,clkops-idx = <0x3>;
  882. };
  883.  
  884. clk_sfc_mux {
  885. compatible = "rockchip,rk3188-mux-con";
  886. rockchip,bits = <0xe 0x2>;
  887. clocks = <0x14 0x10 0xe 0x3>;
  888. clock-output-names = "clk_sfc";
  889. #clock-cells = <0x0>;
  890. #clock-init-cells = <0x1>;
  891. linux,phandle = <0x27>;
  892. phandle = <0x27>;
  893. };
  894. };
  895.  
  896. sel-con@0074 {
  897. compatible = "rockchip,rk3188-selcon";
  898. reg = <0x74 0x4>;
  899. #address-cells = <0x1>;
  900. #size-cells = <0x1>;
  901.  
  902. clk_sdio_div {
  903. compatible = "rockchip,rk3188-div-con";
  904. rockchip,bits = <0x0 0x6>;
  905. clocks = <0x28>;
  906. clock-output-names = "clk_sdio";
  907. rockchip,div-type = <0x0>;
  908. #clock-cells = <0x0>;
  909. rockchip,clkops-idx = <0x3>;
  910. };
  911.  
  912. clk_sdio_mux {
  913. compatible = "rockchip,rk3188-mux-con";
  914. rockchip,bits = <0x6 0x2>;
  915. clocks = <0x14 0x10 0xe 0x3>;
  916. clock-output-names = "clk_sdio";
  917. #clock-cells = <0x0>;
  918. #clock-init-cells = <0x1>;
  919. linux,phandle = <0x28>;
  920. phandle = <0x28>;
  921. };
  922.  
  923. clk_emmc_div {
  924. compatible = "rockchip,rk3188-div-con";
  925. rockchip,bits = <0x8 0x6>;
  926. clocks = <0x29>;
  927. clock-output-names = "clk_emmc";
  928. rockchip,div-type = <0x0>;
  929. #clock-cells = <0x0>;
  930. rockchip,clkops-idx = <0x3>;
  931. };
  932.  
  933. clk_emmc_mux {
  934. compatible = "rockchip,rk3188-mux-con";
  935. rockchip,bits = <0xe 0x2>;
  936. clocks = <0x14 0x10 0xe 0x3>;
  937. clock-output-names = "clk_emmc";
  938. #clock-cells = <0x0>;
  939. #clock-init-cells = <0x1>;
  940. linux,phandle = <0x29>;
  941. phandle = <0x29>;
  942. };
  943. };
  944.  
  945. sel-con@0078 {
  946. compatible = "rockchip,rk3188-selcon";
  947. reg = <0x78 0x4>;
  948. #address-cells = <0x1>;
  949. #size-cells = <0x1>;
  950.  
  951. clk_uart0_pll_div {
  952. compatible = "rockchip,rk3188-div-con";
  953. rockchip,bits = <0x0 0x7>;
  954. clocks = <0x2a>;
  955. clock-output-names = "clk_uart0_pll";
  956. rockchip,div-type = <0x0>;
  957. #clock-cells = <0x0>;
  958. };
  959.  
  960. clk_uart0_mux {
  961. compatible = "rockchip,rk3188-mux-con";
  962. rockchip,bits = <0x8 0x2>;
  963. clocks = <0x2a 0x2b 0x3>;
  964. clock-output-names = "clk_uart0";
  965. #clock-cells = <0x0>;
  966. rockchip,clkops-idx = <0xe>;
  967. rockchip,flags = <0x4>;
  968. linux,phandle = <0x50>;
  969. phandle = <0x50>;
  970. };
  971.  
  972. clk_uart0_pll_mux {
  973. compatible = "rockchip,rk3188-mux-con";
  974. rockchip,bits = <0xc 0x2>;
  975. clocks = <0x14 0x10 0xe 0x2c>;
  976. clock-output-names = "clk_uart0_pll";
  977. #clock-cells = <0x0>;
  978. #clock-init-cells = <0x1>;
  979. linux,phandle = <0x2a>;
  980. phandle = <0x2a>;
  981. };
  982.  
  983. clk_uart2_pll_mux {
  984. compatible = "rockchip,rk3188-mux-con";
  985. rockchip,bits = <0xe 0x2>;
  986. clocks = <0x14 0x10 0xe 0x2c>;
  987. clock-output-names = "clk_uart2_pll";
  988. #clock-cells = <0x0>;
  989. #clock-init-cells = <0x1>;
  990. linux,phandle = <0x2d>;
  991. phandle = <0x2d>;
  992. };
  993. };
  994.  
  995. sel-con@007c {
  996. compatible = "rockchip,rk3188-selcon";
  997. reg = <0x7c 0x4>;
  998. #address-cells = <0x1>;
  999. #size-cells = <0x1>;
  1000.  
  1001. clk_uart1_div {
  1002. compatible = "rockchip,rk3188-div-con";
  1003. rockchip,bits = <0x0 0x7>;
  1004. clocks = <0x2d>;
  1005. clock-output-names = "clk_uart1_div";
  1006. rockchip,div-type = <0x0>;
  1007. #clock-cells = <0x0>;
  1008. linux,phandle = <0x2e>;
  1009. phandle = <0x2e>;
  1010. };
  1011.  
  1012. clk_uart1_mux {
  1013. compatible = "rockchip,rk3188-mux-con";
  1014. rockchip,bits = <0x8 0x2>;
  1015. clocks = <0x2e 0x2f 0x3>;
  1016. clock-output-names = "clk_uart1";
  1017. #clock-cells = <0x0>;
  1018. rockchip,clkops-idx = <0xe>;
  1019. rockchip,flags = <0x4>;
  1020. linux,phandle = <0x55>;
  1021. phandle = <0x55>;
  1022. };
  1023. };
  1024.  
  1025. sel-con@0080 {
  1026. compatible = "rockchip,rk3188-selcon";
  1027. reg = <0x80 0x4>;
  1028. #address-cells = <0x1>;
  1029. #size-cells = <0x1>;
  1030.  
  1031. clk_uart2_div {
  1032. compatible = "rockchip,rk3188-div-con";
  1033. rockchip,bits = <0x0 0x7>;
  1034. clocks = <0x2d>;
  1035. clock-output-names = "clk_uart2_div";
  1036. rockchip,div-type = <0x0>;
  1037. #clock-cells = <0x0>;
  1038. linux,phandle = <0x30>;
  1039. phandle = <0x30>;
  1040. };
  1041.  
  1042. clk_uart2_mux {
  1043. compatible = "rockchip,rk3188-mux-con";
  1044. rockchip,bits = <0x8 0x2>;
  1045. clocks = <0x30 0x31 0x3>;
  1046. clock-output-names = "clk_uart2";
  1047. #clock-cells = <0x0>;
  1048. rockchip,clkops-idx = <0xe>;
  1049. rockchip,flags = <0x4>;
  1050. linux,phandle = <0x59>;
  1051. phandle = <0x59>;
  1052. };
  1053. };
  1054.  
  1055. sel-con@0088 {
  1056. compatible = "rockchip,rk3188-selcon";
  1057. reg = <0x88 0x4>;
  1058. #address-cells = <0x1>;
  1059. #size-cells = <0x1>;
  1060.  
  1061. uart0_frac {
  1062. compatible = "rockchip,rk3188-frac-con";
  1063. clocks = <0x2a>;
  1064. clock-output-names = "uart0_frac";
  1065. rockchip,bits = <0x0 0x20>;
  1066. rockchip,clkops-idx = <0x5>;
  1067. #clock-cells = <0x0>;
  1068. linux,phandle = <0x2b>;
  1069. phandle = <0x2b>;
  1070. };
  1071. };
  1072.  
  1073. sel-con@008c {
  1074. compatible = "rockchip,rk3188-selcon";
  1075. reg = <0x8c 0x4>;
  1076. #address-cells = <0x1>;
  1077. #size-cells = <0x1>;
  1078.  
  1079. uart1_frac {
  1080. compatible = "rockchip,rk3188-frac-con";
  1081. clocks = <0x2e>;
  1082. clock-output-names = "uart1_frac";
  1083. rockchip,bits = <0x0 0x20>;
  1084. rockchip,clkops-idx = <0x5>;
  1085. #clock-cells = <0x0>;
  1086. linux,phandle = <0x2f>;
  1087. phandle = <0x2f>;
  1088. };
  1089. };
  1090.  
  1091. sel-con@0090 {
  1092. compatible = "rockchip,rk3188-selcon";
  1093. reg = <0x90 0x4>;
  1094. #address-cells = <0x1>;
  1095. #size-cells = <0x1>;
  1096.  
  1097. uart2_frac {
  1098. compatible = "rockchip,rk3188-frac-con";
  1099. clocks = <0x30>;
  1100. clock-output-names = "uart2_frac";
  1101. rockchip,bits = <0x0 0x20>;
  1102. rockchip,clkops-idx = <0x5>;
  1103. #clock-cells = <0x0>;
  1104. linux,phandle = <0x31>;
  1105. phandle = <0x31>;
  1106. };
  1107. };
  1108.  
  1109. sel-con@0094 {
  1110. compatible = "rockchip,rk3188-selcon";
  1111. reg = <0x94 0x4>;
  1112. #address-cells = <0x1>;
  1113. #size-cells = <0x1>;
  1114.  
  1115. spdif_frac {
  1116. compatible = "rockchip,rk3188-frac-con";
  1117. clocks = <0x20>;
  1118. clock-output-names = "spdif_frac";
  1119. rockchip,bits = <0x0 0x20>;
  1120. rockchip,clkops-idx = <0x5>;
  1121. #clock-cells = <0x0>;
  1122. linux,phandle = <0x21>;
  1123. phandle = <0x21>;
  1124. };
  1125. };
  1126.  
  1127. sel-con@00a0 {
  1128. compatible = "rockchip,rk3188-selcon";
  1129. reg = <0xa0 0x4>;
  1130. #address-cells = <0x1>;
  1131. #size-cells = <0x1>;
  1132.  
  1133. dclk_ebc_mux {
  1134. compatible = "rockchip,rk3188-mux-con";
  1135. rockchip,bits = <0x0 0x2>;
  1136. clocks = <0x14 0x10 0xe>;
  1137. clock-output-names = "dclk_ebc";
  1138. #clock-cells = <0x0>;
  1139. #clock-init-cells = <0x1>;
  1140. linux,phandle = <0x32>;
  1141. phandle = <0x32>;
  1142. };
  1143.  
  1144. dclk_ebc_div {
  1145. compatible = "rockchip,rk3188-div-con";
  1146. rockchip,bits = <0x8 0x8>;
  1147. clocks = <0x32>;
  1148. clock-output-names = "dclk_ebc";
  1149. rockchip,div-type = <0x0>;
  1150. #clock-cells = <0x0>;
  1151. rockchip,clkops-idx = <0x1>;
  1152. };
  1153. };
  1154.  
  1155. sel-con@00a4 {
  1156. compatible = "rockchip,rk3188-selcon";
  1157. reg = <0xa4 0x4>;
  1158. #address-cells = <0x1>;
  1159. #size-cells = <0x1>;
  1160.  
  1161. clk_crypto_div {
  1162. compatible = "rockchip,rk3188-div-con";
  1163. rockchip,bits = <0x0 0x2>;
  1164. clocks = <0xf>;
  1165. clock-output-names = "clk_crypto";
  1166. rockchip,div-type = <0x0>;
  1167. #clock-cells = <0x0>;
  1168. #clock-init-cells = <0x1>;
  1169. };
  1170.  
  1171. clk_saradc_div {
  1172. compatible = "rockchip,rk3188-div-con";
  1173. rockchip,bits = <0x8 0x8>;
  1174. clocks = <0x3>;
  1175. clock-output-names = "clk_saradc";
  1176. rockchip,div-type = <0x0>;
  1177. #clock-cells = <0x0>;
  1178. #clock-init-cells = <0x1>;
  1179. linux,phandle = <0x41>;
  1180. phandle = <0x41>;
  1181. };
  1182. };
  1183.  
  1184. sel-con@00a8 {
  1185. compatible = "rockchip,rk3188-selcon";
  1186. reg = <0xa8 0x4>;
  1187. #address-cells = <0x1>;
  1188. #size-cells = <0x1>;
  1189.  
  1190. clk_spi0_div {
  1191. compatible = "rockchip,rk3188-div-con";
  1192. rockchip,bits = <0x0 0x7>;
  1193. clocks = <0x33>;
  1194. clock-output-names = "clk_spi0";
  1195. rockchip,div-type = <0x0>;
  1196. #clock-cells = <0x0>;
  1197. rockchip,clkops-idx = <0x1>;
  1198. };
  1199.  
  1200. clk_spi0_mux {
  1201. compatible = "rockchip,rk3188-mux-con";
  1202. rockchip,bits = <0x8 0x2>;
  1203. clocks = <0x14 0x10 0xe>;
  1204. clock-output-names = "clk_spi0";
  1205. #clock-cells = <0x0>;
  1206. linux,phandle = <0x33>;
  1207. phandle = <0x33>;
  1208. };
  1209. };
  1210.  
  1211. sel-con@00ac {
  1212. compatible = "rockchip,rk3188-selcon";
  1213. reg = <0xac 0x4>;
  1214. #address-cells = <0x1>;
  1215. #size-cells = <0x1>;
  1216.  
  1217. ddr_div {
  1218. compatible = "rockchip,rk3188-div-con";
  1219. rockchip,bits = <0x0 0x2>;
  1220. clocks = <0x34>;
  1221. clock-output-names = "clk_ddr";
  1222. rockchip,div-type = <0x80>;
  1223. rockchip,div-relations = <0x0 0x1 0x1 0x2 0x3 0x4>;
  1224. #clock-cells = <0x0>;
  1225. rockchip,flags = <0xc0>;
  1226. rockchip,clkops-idx = <0x12>;
  1227. };
  1228.  
  1229. ddr_clk_pll_mux {
  1230. compatible = "rockchip,rk3188-mux-con";
  1231. rockchip,bits = <0x8 0x1>;
  1232. clocks = <0x35 0x4>;
  1233. clock-output-names = "clk_ddr";
  1234. #clock-cells = <0x0>;
  1235. linux,phandle = <0x34>;
  1236. phandle = <0x34>;
  1237. };
  1238. };
  1239.  
  1240. sel-con@00b0 {
  1241. compatible = "rockchip,rk3188-selcon";
  1242. reg = <0xb0 0x4>;
  1243. #address-cells = <0x1>;
  1244. #size-cells = <0x1>;
  1245.  
  1246. dclk_lcdc0_mux {
  1247. compatible = "rockchip,rk3188-mux-con";
  1248. rockchip,bits = <0x0 0x2>;
  1249. clocks = <0x14 0x10 0xe 0x11>;
  1250. clock-output-names = "dclk_lcdc0";
  1251. #clock-cells = <0x0>;
  1252. #clock-init-cells = <0x1>;
  1253. linux,phandle = <0x36>;
  1254. phandle = <0x36>;
  1255. };
  1256.  
  1257. dclk_lcdc0_div {
  1258. compatible = "rockchip,rk3188-div-con";
  1259. rockchip,bits = <0x8 0x8>;
  1260. clocks = <0x36>;
  1261. clock-output-names = "dclk_lcdc0";
  1262. rockchip,div-type = <0x0>;
  1263. #clock-cells = <0x0>;
  1264. rockchip,clkops-idx = <0x1>;
  1265. rockchip,flags = <0x80>;
  1266. };
  1267. };
  1268.  
  1269. sel-con@00b4 {
  1270. compatible = "rockchip,rk3188-selcon";
  1271. reg = <0xb4 0x4>;
  1272. #address-cells = <0x1>;
  1273. #size-cells = <0x1>;
  1274.  
  1275. sclk_lcdc0_mux {
  1276. compatible = "rockchip,rk3188-mux-con";
  1277. rockchip,bits = <0x0 0x2>;
  1278. clocks = <0x14 0x10 0xe 0x11>;
  1279. clock-output-names = "sclk_lcdc0";
  1280. #clock-cells = <0x0>;
  1281. #clock-init-cells = <0x1>;
  1282. linux,phandle = <0x37>;
  1283. phandle = <0x37>;
  1284. };
  1285.  
  1286. sclk_lcdc0_div {
  1287. compatible = "rockchip,rk3188-div-con";
  1288. rockchip,bits = <0x8 0x8>;
  1289. clocks = <0x37>;
  1290. clock-output-names = "sclk_lcdc0";
  1291. rockchip,div-type = <0x0>;
  1292. #clock-cells = <0x0>;
  1293. rockchip,clkops-idx = <0x1>;
  1294. rockchip,flags = <0x80>;
  1295. };
  1296. };
  1297.  
  1298. sel-con@00b8 {
  1299. compatible = "rockchip,rk3188-selcon";
  1300. reg = <0xb8 0x4>;
  1301. #address-cells = <0x1>;
  1302. #size-cells = <0x1>;
  1303.  
  1304. clk_cif_pll_mux {
  1305. compatible = "rockchip,rk3188-mux-con";
  1306. rockchip,bits = <0x0 0x2>;
  1307. clocks = <0x14 0x10 0xe 0x2c>;
  1308. clock-output-names = "clk_cif_pll";
  1309. #clock-cells = <0x0>;
  1310. #clock-init-cells = <0x1>;
  1311. linux,phandle = <0x39>;
  1312. phandle = <0x39>;
  1313. };
  1314.  
  1315. clk_cif_out_div {
  1316. compatible = "rockchip,rk3188-div-con";
  1317. rockchip,bits = <0x2 0x5>;
  1318. clocks = <0x38>;
  1319. clock-output-names = "clk_cif_out";
  1320. rockchip,div-type = <0x0>;
  1321. #clock-cells = <0x0>;
  1322. rockchip,clkops-idx = <0x1>;
  1323. };
  1324.  
  1325. clk_cif_out_mux {
  1326. compatible = "rockchip,rk3188-mux-con";
  1327. rockchip,bits = <0x7 0x1>;
  1328. clocks = <0x39 0x3>;
  1329. clock-output-names = "clk_cif_out";
  1330. #clock-cells = <0x0>;
  1331. #clock-init-cells = <0x1>;
  1332. linux,phandle = <0x38>;
  1333. phandle = <0x38>;
  1334. };
  1335.  
  1336. pclk_pmu_pre_div {
  1337. compatible = "rockchip,rk3188-div-con";
  1338. rockchip,bits = <0x8 0x6>;
  1339. clocks = <0x14>;
  1340. clock-output-names = "pclk_pmu_pre";
  1341. rockchip,div-type = <0x0>;
  1342. #clock-cells = <0x0>;
  1343. #clock-init-cells = <0x1>;
  1344. linux,phandle = <0x4a>;
  1345. phandle = <0x4a>;
  1346. };
  1347. };
  1348.  
  1349. sel-con@00bc {
  1350. compatible = "rockchip,rk3188-selcon";
  1351. reg = <0xbc 0x4>;
  1352. #address-cells = <0x1>;
  1353. #size-cells = <0x1>;
  1354.  
  1355. clk_testout_div {
  1356. compatible = "rockchip,rk3188-div-con";
  1357. rockchip,bits = <0x0 0x5>;
  1358. clocks = <0x4>;
  1359. clock-output-names = "clk_testout";
  1360. rockchip,div-type = <0x0>;
  1361. #clock-cells = <0x0>;
  1362. #clock-init-cells = <0x1>;
  1363. };
  1364.  
  1365. clk_cif0_in_mux {
  1366. compatible = "rockchip,rk3188-mux-con";
  1367. rockchip,bits = <0x7 0x1>;
  1368. clocks = <0x3a 0x3b>;
  1369. clock-output-names = "clk_cif0_in";
  1370. #clock-cells = <0x0>;
  1371. #clock-init-cells = <0x1>;
  1372. linux,phandle = <0xab>;
  1373. phandle = <0xab>;
  1374. };
  1375.  
  1376. hclk_vio_pre_div {
  1377. compatible = "rockchip,rk3188-div-con";
  1378. rockchip,bits = <0x8 0x5>;
  1379. clocks = <0x8>;
  1380. clock-output-names = "hclk_vio_pre";
  1381. rockchip,div-type = <0x0>;
  1382. #clock-cells = <0x0>;
  1383. rockchip,clkops-idx = <0x1>;
  1384. rockchip,flags = <0x100>;
  1385. };
  1386.  
  1387. hclk_vio_pre_mux {
  1388. compatible = "rockchip,rk3188-mux-con";
  1389. rockchip,bits = <0xe 0x2>;
  1390. clocks = <0x14 0x10 0xe 0x2c>;
  1391. clock-output-names = "hclk_vio_pre";
  1392. #clock-cells = <0x0>;
  1393. #clock-init-cells = <0x1>;
  1394. linux,phandle = <0x8>;
  1395. phandle = <0x8>;
  1396. };
  1397. };
  1398.  
  1399. sel-con@00c0 {
  1400. compatible = "rockchip,rk3188-selcon";
  1401. reg = <0xc0 0x4>;
  1402. #address-cells = <0x1>;
  1403. #size-cells = <0x1>;
  1404.  
  1405. aclk_vio0_pre_div {
  1406. compatible = "rockchip,rk3188-div-con";
  1407. rockchip,bits = <0x0 0x5>;
  1408. clocks = <0x9>;
  1409. clock-output-names = "aclk_vio0_pre";
  1410. rockchip,div-type = <0x0>;
  1411. #clock-cells = <0x0>;
  1412. rockchip,clkops-idx = <0x1>;
  1413. rockchip,flags = <0x100>;
  1414. };
  1415.  
  1416. aclk_vio0_pre_mux {
  1417. compatible = "rockchip,rk3188-mux-con";
  1418. rockchip,bits = <0x5 0x3>;
  1419. clocks = <0x14 0x10 0xe 0x11 0x2c>;
  1420. clock-output-names = "aclk_vio0_pre";
  1421. #clock-cells = <0x0>;
  1422. #clock-init-cells = <0x1>;
  1423. linux,phandle = <0x9>;
  1424. phandle = <0x9>;
  1425. };
  1426.  
  1427. aclk_vio1_pre_div {
  1428. compatible = "rockchip,rk3188-div-con";
  1429. rockchip,bits = <0x8 0x5>;
  1430. clocks = <0xa>;
  1431. clock-output-names = "aclk_vio1_pre";
  1432. rockchip,div-type = <0x0>;
  1433. #clock-cells = <0x0>;
  1434. rockchip,clkops-idx = <0x1>;
  1435. rockchip,flags = <0x100>;
  1436. };
  1437.  
  1438. aclk_vio1_pre_mux {
  1439. compatible = "rockchip,rk3188-mux-con";
  1440. rockchip,bits = <0xd 0x3>;
  1441. clocks = <0x14 0x10 0xe 0x11 0x2c>;
  1442. clock-output-names = "aclk_vio1_pre";
  1443. #clock-cells = <0x0>;
  1444. #clock-init-cells = <0x1>;
  1445. linux,phandle = <0xa>;
  1446. phandle = <0xa>;
  1447. };
  1448. };
  1449.  
  1450. sel-con@00c4 {
  1451. compatible = "rockchip,rk3188-selcon";
  1452. reg = <0xc4 0x4>;
  1453. #address-cells = <0x1>;
  1454. #size-cells = <0x1>;
  1455.  
  1456. clk_vepu_div {
  1457. compatible = "rockchip,rk3188-div-con";
  1458. rockchip,bits = <0x0 0x5>;
  1459. clocks = <0x5>;
  1460. clock-output-names = "clk_vepu";
  1461. rockchip,div-type = <0x0>;
  1462. #clock-cells = <0x0>;
  1463. rockchip,clkops-idx = <0x1>;
  1464. rockchip,flags = <0x80>;
  1465. };
  1466.  
  1467. clk_vepu_mux {
  1468. compatible = "rockchip,rk3188-mux-con";
  1469. rockchip,bits = <0x5 0x3>;
  1470. clocks = <0x14 0x10 0xe 0x11 0x2c>;
  1471. clock-output-names = "clk_vepu";
  1472. #clock-cells = <0x0>;
  1473. #clock-init-cells = <0x1>;
  1474. linux,phandle = <0x5>;
  1475. phandle = <0x5>;
  1476. };
  1477.  
  1478. clk_vdpu_div {
  1479. compatible = "rockchip,rk3188-div-con";
  1480. rockchip,bits = <0x8 0x5>;
  1481. clocks = <0x6>;
  1482. clock-output-names = "clk_vdpu";
  1483. rockchip,div-type = <0x0>;
  1484. #clock-cells = <0x0>;
  1485. rockchip,clkops-idx = <0x1>;
  1486. rockchip,flags = <0x80>;
  1487. };
  1488.  
  1489. clk_vdpu_mux {
  1490. compatible = "rockchip,rk3188-mux-con";
  1491. rockchip,bits = <0xd 0x3>;
  1492. clocks = <0x14 0x10 0xe 0x11 0x2c>;
  1493. clock-output-names = "clk_vdpu";
  1494. #clock-cells = <0x0>;
  1495. #clock-init-cells = <0x1>;
  1496. linux,phandle = <0x6>;
  1497. phandle = <0x6>;
  1498. };
  1499. };
  1500.  
  1501. sel-con@00cc {
  1502. compatible = "rockchip,rk3188-selcon";
  1503. reg = <0xcc 0x4>;
  1504. #address-cells = <0x1>;
  1505. #size-cells = <0x1>;
  1506.  
  1507. clk_gpu_div {
  1508. compatible = "rockchip,rk3188-div-con";
  1509. rockchip,bits = <0x0 0x5>;
  1510. clocks = <0x3c>;
  1511. clock-output-names = "clk_gpu";
  1512. rockchip,div-type = <0x0>;
  1513. #clock-cells = <0x0>;
  1514. rockchip,clkops-idx = <0x1>;
  1515. rockchip,flags = <0x100>;
  1516. };
  1517.  
  1518. clk_gpu_mux {
  1519. compatible = "rockchip,rk3188-mux-con";
  1520. rockchip,bits = <0x5 0x3>;
  1521. clocks = <0x14 0x10 0xe 0x11 0x2c>;
  1522. clock-output-names = "clk_gpu";
  1523. #clock-cells = <0x0>;
  1524. #clock-init-cells = <0x1>;
  1525. linux,phandle = <0x3c>;
  1526. phandle = <0x3c>;
  1527. };
  1528.  
  1529. clk_hevc_core_div {
  1530. compatible = "rockchip,rk3188-div-con";
  1531. rockchip,bits = <0x8 0x5>;
  1532. clocks = <0x3d>;
  1533. clock-output-names = "clk_hevc_core";
  1534. rockchip,div-type = <0x0>;
  1535. #clock-cells = <0x0>;
  1536. rockchip,clkops-idx = <0x1>;
  1537. rockchip,flags = <0x80>;
  1538. };
  1539.  
  1540. clk_hevc_core_mux {
  1541. compatible = "rockchip,rk3188-mux-con";
  1542. rockchip,bits = <0xd 0x3>;
  1543. clocks = <0x14 0x10 0xe 0x11 0x2c>;
  1544. clock-output-names = "clk_hevc_core";
  1545. #clock-cells = <0x0>;
  1546. #clock-init-cells = <0x1>;
  1547. linux,phandle = <0x3d>;
  1548. phandle = <0x3d>;
  1549. };
  1550. };
  1551. };
  1552.  
  1553. clk_gate_cons {
  1554. compatible = "rockchip,rk-gate-cons";
  1555. #address-cells = <0x1>;
  1556. #size-cells = <0x1>;
  1557. ranges;
  1558.  
  1559. gate-clk@00d0 {
  1560. compatible = "rockchip,rk3188-gate-clk";
  1561. reg = <0xd0 0x4>;
  1562. clocks = <0xc 0x4 0x4 0xf 0xf 0xf 0x4 0xc 0x4 0x15 0x17 0x8 0xf 0x3e 0x1a 0x4>;
  1563. clock-output-names = "pclk_dbg", "aclk_cpu", "reserved", "aclk_cpu_pre", "hclk_cpu_pre", "pclk_cpu_pre", "clk_core", "aclk_core_pre", "reserved", "clk_i2s_2ch_pll", "i2s_2ch_frac", "hclk_vio_pre", "clk_crypto", "clk_i2s_2ch_out", "clk_i2s_2ch", "clk_testout";
  1564. rockchip,suspend-clkgating-setting = <0x11ff 0x0>;
  1565. #clock-cells = <0x1>;
  1566. linux,phandle = <0x6e>;
  1567. phandle = <0x6e>;
  1568. };
  1569.  
  1570. gate-clk@00d4 {
  1571. compatible = "rockchip,rk3188-gate-clk";
  1572. reg = <0xd4 0x4>;
  1573. clocks = <0x14 0x4 0x4 0x3f 0xa 0x19 0x19 0x1c 0x2a 0x2b 0x2e 0x2f 0x30 0x31 0x1b 0x4>;
  1574. clock-output-names = "pclk_pmu_pre", "reserved", "reserved", "clk_jtag", "aclk_vio1_pre", "clk_otgphy0", "clk_otgphy1", "clk_mac_pll", "clk_uart0_pll", "uart0_frac", "clk_uart1_div", "uart1_frac", "clk_uart2_div", "uart2_frac", "clk_tsp", "reserved";
  1575. rockchip,suspend-clkgating-setting = <0xf 0x0>;
  1576. #clock-cells = <0x1>;
  1577. linux,phandle = <0x71>;
  1578. phandle = <0x71>;
  1579. };
  1580.  
  1581. gate-clk@00d8 {
  1582. compatible = "rockchip,rk3188-gate-clk";
  1583. reg = <0xd8 0x4>;
  1584. clocks = <0x25 0x25 0x25 0x25 0x40 0x40 0x40 0x40 0x41 0x33 0x1f 0x26 0x21 0x28 0x29 0x3>;
  1585. clock-output-names = "aclk_peri", "aclk_peri_pre", "hclk_peri_pre", "pclk_peri_pre", "clk_mac_ref", "clk_mac_refout", "clk_mac_rx", "clk_mac_tx", "clk_saradc", "clk_spi0", "clk_spdif_pll", "clk_sdmmc0", "spdif_frac", "clk_sdio", "clk_emmc", "clk_mipi_24m";
  1586. rockchip,suspend-clkgating-setting = <0xf 0x0>;
  1587. #clock-cells = <0x1>;
  1588. linux,phandle = <0x5b>;
  1589. phandle = <0x5b>;
  1590. };
  1591.  
  1592. gate-clk@00dc {
  1593. compatible = "rockchip,rk3188-gate-clk";
  1594. reg = <0xdc 0x4>;
  1595. clocks = <0x9 0x36 0x37 0x3a 0x32 0x42 0x43 0x39 0x44 0x5 0x3d 0x6 0x45 0x3c 0x25 0x27>;
  1596. clock-output-names = "aclk_vio0_pre", "dclk_lcdc0", "sclk_lcdc0", "pclkin_cif", "dclk_ebc", "g_hclk_crypto", "g_hclk_em_peri", "clk_cif_pll", "g_pclk_hdmi", "clk_vepu", "clk_hevc_core", "clk_vdpu", "hclk_vdpu", "clk_gpu", "g_hclk_gps", "clk_sfc";
  1597. rockchip,suspend-clkgating-setting = <0x60 0x0>;
  1598. #clock-cells = <0x1>;
  1599. linux,phandle = <0x7>;
  1600. phandle = <0x7>;
  1601. };
  1602.  
  1603. gate-clk@00e0 {
  1604. compatible = "rockchip,rk3188-gate-clk";
  1605. reg = <0xe0 0x4>;
  1606. clocks = <0x43 0x46 0x25 0x25 0x22 0x24 0x47 0x4 0x4 0x4 0xf 0x4 0xf 0x4 0x4 0x4>;
  1607. clock-output-names = "g_hp_axi_matrix", "g_pp_axi_matrix", "g_aclk_cpu_peri", "g_ap_axi_matrix", "clk_i2s_8ch_pll", "i2s_8ch_frac", "clk_i2s_8ch", "reserved", "reserved", "reserved", "g_aclk_strc_sys", "reserved", "g_aclk_intmem", "reserved", "reserved", "reserved";
  1608. rockchip,suspend-clkgating-setting = <0xff8f 0x0>;
  1609. #clock-cells = <0x1>;
  1610. linux,phandle = <0x6f>;
  1611. phandle = <0x6f>;
  1612. };
  1613.  
  1614. gate-clk@00e4 {
  1615. compatible = "rockchip,rk3188-gate-clk";
  1616. reg = <0xe4 0x4>;
  1617. clocks = <0x44 0x25 0x46 0x4 0x44 0x4 0x42 0x44 0x4 0x43 0x43 0x43 0x4 0x43 0x44 0x4>;
  1618. clock-output-names = "g_pclk_mipiphy", "g_aclk_dmac", "g_pclk_efuse", "reserved", "g_pclk_grf", "reserved", "g_hclk_rom", "g_pclk_ddrupctl", "reserved", "g_hclk_nandc", "g_hclk_sdmmc0", "g_hclk_sdio", "reserved", "g_hclk_otg0", "g_pclk_acodec", "reserved";
  1619. rockchip,suspend-clkgating-setting = <0xf0 0x0>;
  1620. #clock-cells = <0x1>;
  1621. linux,phandle = <0x4e>;
  1622. phandle = <0x4e>;
  1623. };
  1624.  
  1625. gate-clk@00e8 {
  1626. compatible = "rockchip,rk3188-gate-clk";
  1627. reg = <0xe8 0x4>;
  1628. clocks = <0x48 0x49 0x4 0x4 0x49 0x48 0x4 0x4 0x4 0x4 0x49 0x48 0x8 0x9 0x4 0x4>;
  1629. clock-output-names = "g_aclk_lcdc0", "g_hclk_lcdc0", "reserved", "reserved", "g_hclk_cif", "g_aclk_cif", "reserved", "reserved", "reserved", "reserved", "g_hclk_rga", "g_aclk_rga", "hclk_vio_niu", "aclk_vio0_niu", "reserved", "reserved";
  1630. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  1631. #clock-cells = <0x1>;
  1632. linux,phandle = <0x9d>;
  1633. phandle = <0x9d>;
  1634. };
  1635.  
  1636. gate-clk@00ec {
  1637. compatible = "rockchip,rk3188-gate-clk";
  1638. reg = <0xec 0x4>;
  1639. clocks = <0x43 0x43 0x43 0x43 0x43 0x4 0x4 0x46 0x4 0x4 0x46 0x4 0x46 0x4 0x46 0x46>;
  1640. clock-output-names = "g_hclk_emmc", "g_hclk_sfc", "g_hclk_i2s_2ch", "g_hclk_host", "g_hclk_i2s_8ch", "reserved", "reserved", "g_pclk_timer", "reserved", "reserved", "g_pclk_pwm", "reserved", "g_pclk_spi0", "reserved", "g_pclk_saradc", "g_pclk_wdt";
  1641. rockchip,suspend-clkgating-setting = <0x8480 0x0>;
  1642. #clock-cells = <0x1>;
  1643. linux,phandle = <0x81>;
  1644. phandle = <0x81>;
  1645. };
  1646.  
  1647. gate-clk@00f0 {
  1648. compatible = "rockchip,rk3188-gate-clk";
  1649. reg = <0xf0 0x4>;
  1650. clocks = <0x46 0x46 0x46 0x4 0x46 0x46 0x46 0x46 0x4 0x46 0x46 0x46 0x46 0x4 0x4 0x4>;
  1651. clock-output-names = "g_pclk_uart0", "g_pclk_uart1", "g_pclk_uart2", "reserved", "g_pclk_i2c0", "g_pclk_i2c1", "g_pclk_i2c2", "g_pclk_i2c3", "reserved", "g_pclk_gpio0", "g_pclk_gpio1", "g_pclk_gpio2", "g_pclk_gpio3", "reserved", "reserved", "reserved";
  1652. rockchip,suspend-clkgating-setting = <0xff0f 0x0>;
  1653. #clock-cells = <0x1>;
  1654. linux,phandle = <0x4d>;
  1655. phandle = <0x4d>;
  1656. };
  1657.  
  1658. gate-clk@00f4 {
  1659. compatible = "rockchip,rk3188-gate-clk";
  1660. reg = <0xf4 0x4>;
  1661. clocks = <0x4 0x4 0x4a 0x4a 0x4 0x49 0x49 0x49 0x4b 0x49 0xa 0x4 0x46 0x43 0x43 0x25>;
  1662. clock-output-names = "reserved", "reserved", "g_pclk_pmu", "g_pclk_pmu_noc", "reserved", "g_hclk_vio_h2p", "g_pclk_mipi", "g_hclk_iep", "g_aclk_iep", "g_hclk_ebc", "aclk_vio1_niu", "reserved", "g_pclk_sim_card", "g_hclk_usb_peri", "g_hclk_pe_arbi", "g_aclk_peri_niu";
  1663. rockchip,suspend-clkgating-setting = <0xf00f 0x0>;
  1664. #clock-cells = <0x1>;
  1665. linux,phandle = <0x70>;
  1666. phandle = <0x70>;
  1667. };
  1668.  
  1669. gate-clk@00f8 {
  1670. compatible = "rockchip,rk3188-gate-clk";
  1671. reg = <0xf8 0x4>;
  1672. clocks = <0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x43 0x25 0x46 0x43 0x4c 0x43 0x13>;
  1673. clock-output-names = "g_clk_pvtm_core", "g_clk_pvtm_gpu", "g_clk_pvtm_func", "clk_timer0", "clk_timer1", "clk_timer2", "clk_timer3", "clk_timer4", "clk_timer5", "g_hclk_spdif", "g_aclk_gmac", "g_pclk_gmac", "g_hclk_tsp", "g_clkin0_tsp", "g_hclk_usbhost", "clk_nandc";
  1674. rockchip,suspend-clkgating-setting = <0x0 0x0>;
  1675. #clock-cells = <0x1>;
  1676. linux,phandle = <0x4f>;
  1677. phandle = <0x4f>;
  1678. };
  1679. };
  1680. };
  1681. };
  1682.  
  1683. pinctrl@20008000 {
  1684. compatible = "rockchip,rk312x-pinctrl";
  1685. reg = <0x20008000 0xa8 0x200080a8 0x4c 0x20008118 0x20 0x20008100 0x4>;
  1686. reg-names = "base", "mux", "pull", "drv";
  1687. #address-cells = <0x1>;
  1688. #size-cells = <0x1>;
  1689. ranges;
  1690.  
  1691. gpio0@2007c000 {
  1692. compatible = "rockchip,gpio-bank";
  1693. reg = <0x2007c000 0x100>;
  1694. interrupts = <0x0 0x24 0x4>;
  1695. clocks = <0x4d 0x9>;
  1696. gpio-controller;
  1697. #gpio-cells = <0x2>;
  1698. interrupt-controller;
  1699. #interrupt-cells = <0x2>;
  1700. linux,phandle = <0x75>;
  1701. phandle = <0x75>;
  1702. };
  1703.  
  1704. gpio1@20080000 {
  1705. compatible = "rockchip,gpio-bank";
  1706. reg = <0x20080000 0x100>;
  1707. interrupts = <0x0 0x25 0x4>;
  1708. clocks = <0x4d 0xa>;
  1709. gpio-controller;
  1710. #gpio-cells = <0x2>;
  1711. interrupt-controller;
  1712. #interrupt-cells = <0x2>;
  1713. linux,phandle = <0x77>;
  1714. phandle = <0x77>;
  1715. };
  1716.  
  1717. gpio2@20084000 {
  1718. compatible = "rockchip,gpio-bank";
  1719. reg = <0x20084000 0x100>;
  1720. interrupts = <0x0 0x26 0x4>;
  1721. clocks = <0x4d 0xb>;
  1722. gpio-controller;
  1723. #gpio-cells = <0x2>;
  1724. interrupt-controller;
  1725. #interrupt-cells = <0x2>;
  1726. linux,phandle = <0x76>;
  1727. phandle = <0x76>;
  1728. };
  1729.  
  1730. gpio3@20088000 {
  1731. compatible = "rockchip,gpio-bank";
  1732. reg = <0x20088000 0x100>;
  1733. interrupts = <0x0 0x27 0x4>;
  1734. clocks = <0x4d 0xc>;
  1735. gpio-controller;
  1736. #gpio-cells = <0x2>;
  1737. interrupt-controller;
  1738. #interrupt-cells = <0x2>;
  1739. linux,phandle = <0xb0>;
  1740. phandle = <0xb0>;
  1741. };
  1742.  
  1743. gpio15@2008A000 {
  1744. compatible = "rockchip,gpio-bank";
  1745. reg = <0x20086000 0x100>;
  1746. interrupts = <0x0 0x7f 0x4>;
  1747. clocks = <0x4d 0xc>;
  1748. gpio-controller;
  1749. #gpio-cells = <0x2>;
  1750. interrupt-controller;
  1751. #interrupt-cells = <0x2>;
  1752. };
  1753.  
  1754. pcfg_pull_up {
  1755. bias-pull-up;
  1756. };
  1757.  
  1758. pcfg_pull_down {
  1759. bias-pull-down;
  1760. };
  1761.  
  1762. pcfg_pull_none {
  1763. bias-disable;
  1764. };
  1765.  
  1766. gpio0_uart0 {
  1767.  
  1768. uart0-xfer {
  1769. rockchip,pins = <0x2d32 0x2d22>;
  1770. rockchip,pull = <0x0>;
  1771. linux,phandle = <0x52>;
  1772. phandle = <0x52>;
  1773. };
  1774.  
  1775. uart0-cts {
  1776. rockchip,pins = <0x2d52>;
  1777. rockchip,pull = <0x4>;
  1778. linux,phandle = <0x53>;
  1779. phandle = <0x53>;
  1780. };
  1781.  
  1782. uart0-rts {
  1783. rockchip,pins = <0xc12>;
  1784. rockchip,pull = <0x4>;
  1785. linux,phandle = <0x54>;
  1786. phandle = <0x54>;
  1787. };
  1788.  
  1789. uart0-rts-gpio {
  1790. rockchip,pins = <0xc10>;
  1791. rockchip,pull = <0x4>;
  1792. };
  1793. };
  1794.  
  1795. gpio1_uart1 {
  1796.  
  1797. uart1-xfer {
  1798. rockchip,pins = <0x1b22 0x1b12>;
  1799. rockchip,pull = <0x4>;
  1800. linux,phandle = <0x56>;
  1801. phandle = <0x56>;
  1802. };
  1803.  
  1804. uart1-cts {
  1805. rockchip,pins = <0x1b02>;
  1806. rockchip,pull = <0x4>;
  1807. linux,phandle = <0x57>;
  1808. phandle = <0x57>;
  1809. };
  1810.  
  1811. uart1-rts {
  1812. rockchip,pins = <0x1b32>;
  1813. rockchip,pull = <0x4>;
  1814. linux,phandle = <0x58>;
  1815. phandle = <0x58>;
  1816. };
  1817.  
  1818. uart1-rts-gpio {
  1819. rockchip,pins = <0x1b30>;
  1820. rockchip,pull = <0x4>;
  1821. };
  1822. };
  1823.  
  1824. gpio1_uart2 {
  1825.  
  1826. uart2-xfer {
  1827. rockchip,pins = <0x1c32 0x1c22>;
  1828. rockchip,pull = <0x4>;
  1829. linux,phandle = <0x5a>;
  1830. phandle = <0x5a>;
  1831. };
  1832.  
  1833. uart2-cts {
  1834. rockchip,pins = <0xd11>;
  1835. rockchip,pull = <0x4>;
  1836. };
  1837.  
  1838. uart2-rts {
  1839. rockchip,pins = <0xd01>;
  1840. rockchip,pull = <0x4>;
  1841. };
  1842.  
  1843. uart2-rts-gpio {
  1844. rockchip,pins = <0xd00>;
  1845. rockchip,pull = <0x4>;
  1846. };
  1847. };
  1848.  
  1849. gpio0_i2c0 {
  1850.  
  1851. i2c0-sda {
  1852. rockchip,pins = <0xa11>;
  1853. rockchip,pull = <0x4>;
  1854. linux,phandle = <0x72>;
  1855. phandle = <0x72>;
  1856. };
  1857.  
  1858. i2c0-scl {
  1859. rockchip,pins = <0xa01>;
  1860. rockchip,pull = <0x4>;
  1861. linux,phandle = <0x73>;
  1862. phandle = <0x73>;
  1863. };
  1864.  
  1865. i2c0-gpio {
  1866. rockchip,pins = <0xa10 0xa00>;
  1867. rockchip,pull = <0x4>;
  1868. linux,phandle = <0x74>;
  1869. phandle = <0x74>;
  1870. };
  1871. };
  1872.  
  1873. gpio0_i2c1 {
  1874.  
  1875. i2c1-sda {
  1876. rockchip,pins = <0xa31>;
  1877. rockchip,pull = <0x4>;
  1878. linux,phandle = <0x78>;
  1879. phandle = <0x78>;
  1880. };
  1881.  
  1882. i2c1-scl {
  1883. rockchip,pins = <0xa21>;
  1884. rockchip,pull = <0x4>;
  1885. linux,phandle = <0x79>;
  1886. phandle = <0x79>;
  1887. };
  1888.  
  1889. i2c1-gpio {
  1890. rockchip,pins = <0xa30 0xa20>;
  1891. rockchip,pull = <0x4>;
  1892. linux,phandle = <0x7a>;
  1893. phandle = <0x7a>;
  1894. };
  1895. };
  1896.  
  1897. gpio1_i2c2 {
  1898.  
  1899. i2c2-sda {
  1900. rockchip,pins = <0x2c43>;
  1901. rockchip,pull = <0x4>;
  1902. linux,phandle = <0x7b>;
  1903. phandle = <0x7b>;
  1904. };
  1905.  
  1906. i2c2-scl {
  1907. rockchip,pins = <0x2c53>;
  1908. rockchip,pull = <0x4>;
  1909. linux,phandle = <0x7c>;
  1910. phandle = <0x7c>;
  1911. };
  1912.  
  1913. i2c2-gpio {
  1914. rockchip,pins = <0x2c40 0x2c50>;
  1915. rockchip,pull = <0x4>;
  1916. linux,phandle = <0x7d>;
  1917. phandle = <0x7d>;
  1918. };
  1919. };
  1920.  
  1921. gpio0_i2c3 {
  1922.  
  1923. i2c3-sda {
  1924. rockchip,pins = <0xa71>;
  1925. rockchip,pull = <0x4>;
  1926. linux,phandle = <0x7e>;
  1927. phandle = <0x7e>;
  1928. };
  1929.  
  1930. i2c3-scl {
  1931. rockchip,pins = <0xa61>;
  1932. rockchip,pull = <0x4>;
  1933. linux,phandle = <0x7f>;
  1934. phandle = <0x7f>;
  1935. };
  1936.  
  1937. i2c3-gpio {
  1938. rockchip,pins = <0xa70 0xa60>;
  1939. rockchip,pull = <0x4>;
  1940. linux,phandle = <0x80>;
  1941. phandle = <0x80>;
  1942. };
  1943. };
  1944.  
  1945. gpio1_spi0 {
  1946.  
  1947. spi0-txd-mux0 {
  1948. rockchip,pins = <0x1b11>;
  1949. rockchip,pull = <0x4>;
  1950. linux,phandle = <0x90>;
  1951. phandle = <0x90>;
  1952. };
  1953.  
  1954. spi0-rxd-mux0 {
  1955. rockchip,pins = <0x1b21>;
  1956. rockchip,pull = <0x4>;
  1957. linux,phandle = <0x91>;
  1958. phandle = <0x91>;
  1959. };
  1960.  
  1961. spi0-clk-mux0 {
  1962. rockchip,pins = <0x1b01>;
  1963. rockchip,pull = <0x4>;
  1964. linux,phandle = <0x92>;
  1965. phandle = <0x92>;
  1966. };
  1967.  
  1968. spi0-cs0-mux0 {
  1969. rockchip,pins = <0x1b31>;
  1970. rockchip,pull = <0x4>;
  1971. linux,phandle = <0x93>;
  1972. phandle = <0x93>;
  1973. };
  1974.  
  1975. spi0-cs1-mux0 {
  1976. rockchip,pins = <0x1b41>;
  1977. rockchip,pull = <0x4>;
  1978. linux,phandle = <0x94>;
  1979. phandle = <0x94>;
  1980. };
  1981.  
  1982. spi0-txd-mux1 {
  1983. rockchip,pins = <0x1d53>;
  1984. rockchip,pull = <0x4>;
  1985. };
  1986.  
  1987. spi0-rxd-mux1 {
  1988. rockchip,pins = <0x1d43>;
  1989. rockchip,pull = <0x4>;
  1990. };
  1991.  
  1992. spi0-clk-mux1 {
  1993. rockchip,pins = <0x2a02>;
  1994. rockchip,pull = <0x4>;
  1995. };
  1996.  
  1997. spi0-cs0-mux1 {
  1998. rockchip,pins = <0x1d63>;
  1999. rockchip,pull = <0x4>;
  2000. };
  2001.  
  2002. spi0-cs1-mux1 {
  2003. rockchip,pins = <0x1d73>;
  2004. rockchip,pull = <0x4>;
  2005. };
  2006.  
  2007. spi0-txd-mux2 {
  2008. rockchip,pins = <0xb32>;
  2009. rockchip,pull = <0x4>;
  2010. };
  2011.  
  2012. spi0-rxd-mux2 {
  2013. rockchip,pins = <0xb52>;
  2014. rockchip,pull = <0x4>;
  2015. };
  2016.  
  2017. spi0-clk-mux2 {
  2018. rockchip,pins = <0xb12>;
  2019. rockchip,pull = <0x4>;
  2020. };
  2021.  
  2022. spi0-cs0-mux2 {
  2023. rockchip,pins = <0xb62>;
  2024. rockchip,pull = <0x4>;
  2025. };
  2026. };
  2027.  
  2028. gpio1_hdmi {
  2029.  
  2030. hdmi-cec {
  2031. rockchip,pins = <0xc41>;
  2032. rockchip,pull = <0x4>;
  2033. linux,phandle = <0xa2>;
  2034. phandle = <0xa2>;
  2035. };
  2036.  
  2037. hdmi-sda {
  2038. rockchip,pins = <0xa72>;
  2039. rockchip,pull = <0x4>;
  2040. linux,phandle = <0xa3>;
  2041. phandle = <0xa3>;
  2042. };
  2043.  
  2044. hdmi-scl {
  2045. rockchip,pins = <0xa62>;
  2046. rockchip,pull = <0x4>;
  2047. linux,phandle = <0xa4>;
  2048. phandle = <0xa4>;
  2049. };
  2050.  
  2051. hdmi-hpd {
  2052. rockchip,pins = <0xb71>;
  2053. rockchip,pull = <0x4>;
  2054. linux,phandle = <0xa5>;
  2055. phandle = <0xa5>;
  2056. };
  2057.  
  2058. hdmi-gpio {
  2059. rockchip,pins = <0xc40 0xa70 0xa60 0xb70>;
  2060. rockchip,pull = <0x4>;
  2061. linux,phandle = <0xa6>;
  2062. phandle = <0xa6>;
  2063. };
  2064. };
  2065.  
  2066. gpio1_i2s0 {
  2067.  
  2068. i2s0-mclk-mux0 {
  2069. rockchip,pins = <0xb01>;
  2070. rockchip,pull = <0x4>;
  2071. };
  2072.  
  2073. i2s0-sclk-mux0 {
  2074. rockchip,pins = <0xb11>;
  2075. rockchip,pull = <0x4>;
  2076. };
  2077.  
  2078. i2s0-lrckrx-mux0 {
  2079. rockchip,pins = <0xb31>;
  2080. rockchip,pull = <0x4>;
  2081. };
  2082.  
  2083. i2s0-lrcktx-mux0 {
  2084. rockchip,pins = <0xb41>;
  2085. rockchip,pull = <0x4>;
  2086. };
  2087.  
  2088. i2s0-sdo-mux0 {
  2089. rockchip,pins = <0xb51>;
  2090. rockchip,pull = <0x4>;
  2091. };
  2092.  
  2093. i2s0-sdi-mux0 {
  2094. rockchip,pins = <0xb61>;
  2095. rockchip,pull = <0x4>;
  2096. };
  2097.  
  2098. i2s0-gpio-mux0 {
  2099. rockchip,pins = <0xb00 0xb10 0xb30 0xb40 0xb50 0xb60>;
  2100. rockchip,pull = <0x4>;
  2101. };
  2102.  
  2103. i2s0-mclk-mux1 {
  2104. rockchip,pins = <0x1a01>;
  2105. rockchip,pull = <0x4>;
  2106. };
  2107.  
  2108. i2s0-sclk-mux1 {
  2109. rockchip,pins = <0x1a11>;
  2110. rockchip,pull = <0x4>;
  2111. };
  2112.  
  2113. i2s0-lrckrx-mux1 {
  2114. rockchip,pins = <0x1a21>;
  2115. rockchip,pull = <0x4>;
  2116. };
  2117.  
  2118. i2s0-lrcktx-mux1 {
  2119. rockchip,pins = <0x1a31>;
  2120. rockchip,pull = <0x4>;
  2121. };
  2122.  
  2123. i2s0-sdo-mux1 {
  2124. rockchip,pins = <0x1a41>;
  2125. rockchip,pull = <0x4>;
  2126. };
  2127.  
  2128. i2s0-sdi-mux1 {
  2129. rockchip,pins = <0x1a51>;
  2130. rockchip,pull = <0x4>;
  2131. };
  2132.  
  2133. i2s0-gpio-mux1 {
  2134. rockchip,pins = <0x1a00 0x1a10 0x1a20 0x1a30 0x1a40 0x1a50>;
  2135. rockchip,pull = <0x4>;
  2136. };
  2137. };
  2138.  
  2139. gpio0_spdif {
  2140.  
  2141. spdif-tx {
  2142. rockchip,pins = <0x3d31>;
  2143. rockchip,pull = <0x4>;
  2144. linux,phandle = <0x83>;
  2145. phandle = <0x83>;
  2146. };
  2147. };
  2148.  
  2149. gpio0_emmc0 {
  2150.  
  2151. emmc0-clk {
  2152. rockchip,pins = <0x2a72>;
  2153. rockchip,pull = <0x4>;
  2154. };
  2155.  
  2156. emmc0-cmd-mux0 {
  2157. rockchip,pins = <0x1c62>;
  2158. rockchip,pull = <0x1>;
  2159. };
  2160.  
  2161. emmc0-cmd-mux1 {
  2162. rockchip,pins = <0x2a42>;
  2163. rockchip,pull = <0x1>;
  2164. };
  2165.  
  2166. emmc0-bus-width1 {
  2167. rockchip,pins = <0x1d02>;
  2168. rockchip,pull = <0x1>;
  2169. };
  2170.  
  2171. emmc0-bus-width4 {
  2172. rockchip,pins = <0x1d02 0x1d12 0x1d22 0x1d32>;
  2173. rockchip,pull = <0x1>;
  2174. };
  2175. };
  2176.  
  2177. gpio1_sdmmc0 {
  2178.  
  2179. sdmmc0-clk {
  2180. rockchip,pins = <0x1c01>;
  2181. rockchip,pull = <0x4>;
  2182. linux,phandle = <0x85>;
  2183. phandle = <0x85>;
  2184. };
  2185.  
  2186. sdmmc0-cmd {
  2187. rockchip,pins = <0x1b71>;
  2188. rockchip,pull = <0x1>;
  2189. linux,phandle = <0x86>;
  2190. phandle = <0x86>;
  2191. };
  2192.  
  2193. sdmmc0-dectn {
  2194. rockchip,pins = <0x1c11>;
  2195. rockchip,pull = <0x1>;
  2196. linux,phandle = <0x87>;
  2197. phandle = <0x87>;
  2198. };
  2199.  
  2200. sdmmc0-pwren {
  2201. rockchip,pins = <0x1b61>;
  2202. rockchip,pull = <0x1>;
  2203. };
  2204.  
  2205. sdmmc0-bus-width1 {
  2206. rockchip,pins = <0x1c21>;
  2207. rockchip,pull = <0x1>;
  2208. };
  2209.  
  2210. sdmmc0-bus-width4 {
  2211. rockchip,pins = <0x1c21 0x1c31 0x1c41 0x1c51>;
  2212. rockchip,pull = <0x1>;
  2213. linux,phandle = <0x88>;
  2214. phandle = <0x88>;
  2215. };
  2216.  
  2217. sdmmc0_gpio {
  2218. rockchip,pins = <0x1b70 0x1c00 0x1c10 0x1b60 0x1c20 0x1c30 0x1c40 0x1c50>;
  2219. rockchip,pull = <0x1>;
  2220. linux,phandle = <0x89>;
  2221. phandle = <0x89>;
  2222. };
  2223. };
  2224.  
  2225. gpio2_nandc {
  2226.  
  2227. nandc-ale {
  2228. rockchip,pins = <0x2a01>;
  2229. rockchip,pull = <0x4>;
  2230. };
  2231.  
  2232. nandc-cle {
  2233. rockchip,pins = <0x2a11>;
  2234. rockchip,pull = <0x4>;
  2235. };
  2236.  
  2237. nandc-wrn {
  2238. rockchip,pins = <0x2a21>;
  2239. rockchip,pull = <0x4>;
  2240. };
  2241.  
  2242. nandc-rdn {
  2243. rockchip,pins = <0x2a31>;
  2244. rockchip,pull = <0x4>;
  2245. };
  2246.  
  2247. nandc-rdy {
  2248. rockchip,pins = <0x2a41>;
  2249. rockchip,pull = <0x4>;
  2250. };
  2251.  
  2252. nandc-cs0 {
  2253. rockchip,pins = <0x2a61>;
  2254. rockchip,pull = <0x4>;
  2255. };
  2256.  
  2257. nandc-data {
  2258. rockchip,pins = <0x1d01 0x1d11 0x1d21 0x1d31 0x1d41 0x1d51 0x1d61 0x1d71>;
  2259. rockchip,pull = <0x4>;
  2260. };
  2261. };
  2262.  
  2263. gpio0_sdio0 {
  2264.  
  2265. sdio0_pwren {
  2266. rockchip,pins = <0xd61>;
  2267. rockchip,pull = <0x4>;
  2268. linux,phandle = <0x8b>;
  2269. phandle = <0x8b>;
  2270. };
  2271.  
  2272. sdio0_cmd {
  2273. rockchip,pins = <0xa32>;
  2274. rockchip,pull = <0x4>;
  2275. linux,phandle = <0x8c>;
  2276. phandle = <0x8c>;
  2277. };
  2278.  
  2279. sdio0_clk {
  2280. rockchip,pins = <0x1a02>;
  2281. rockchip,pull = <0x4>;
  2282. linux,phandle = <0x8d>;
  2283. phandle = <0x8d>;
  2284. };
  2285.  
  2286. sdio0-bus-width1 {
  2287. rockchip,pins = <0x1a12>;
  2288. rockchip,pull = <0x4>;
  2289. };
  2290.  
  2291. sdio0-bus-width4 {
  2292. rockchip,pins = <0x1a12 0x1a22 0x1a42 0x1a52>;
  2293. rockchip,pull = <0x4>;
  2294. linux,phandle = <0x8e>;
  2295. phandle = <0x8e>;
  2296. };
  2297.  
  2298. sdio0_gpio {
  2299. rockchip,pins = <0xd60 0xa30 0x1a00 0x1a10 0x1a20 0x1a40 0x1a50>;
  2300. rockchip,pull = <0x4>;
  2301. linux,phandle = <0x8f>;
  2302. phandle = <0x8f>;
  2303. };
  2304. };
  2305.  
  2306. gpio0_pwm {
  2307.  
  2308. pwm0 {
  2309. rockchip,pins = <0xd21>;
  2310. rockchip,pull = <0x4>;
  2311. linux,phandle = <0x96>;
  2312. phandle = <0x96>;
  2313. };
  2314.  
  2315. pwm1 {
  2316. rockchip,pins = <0xd31>;
  2317. rockchip,pull = <0x4>;
  2318. linux,phandle = <0x97>;
  2319. phandle = <0x97>;
  2320. };
  2321.  
  2322. pwm2 {
  2323. rockchip,pins = <0xd41>;
  2324. rockchip,pull = <0x4>;
  2325. linux,phandle = <0x98>;
  2326. phandle = <0x98>;
  2327. };
  2328.  
  2329. pwm3 {
  2330. rockchip,pins = <0x3d21>;
  2331. rockchip,pull = <0x4>;
  2332. linux,phandle = <0x99>;
  2333. phandle = <0x99>;
  2334. };
  2335. };
  2336.  
  2337. gpio2_gmac {
  2338.  
  2339. gmac-rxdv {
  2340. rockchip,pins = <0x2b03>;
  2341. rockchip,pull = <0x4>;
  2342. linux,phandle = <0x5c>;
  2343. phandle = <0x5c>;
  2344. };
  2345.  
  2346. gmac-txclk {
  2347. rockchip,pins = <0x2b13>;
  2348. rockchip,pull = <0x4>;
  2349. linux,phandle = <0x5d>;
  2350. phandle = <0x5d>;
  2351. };
  2352.  
  2353. gmac-crs {
  2354. rockchip,pins = <0x2b23>;
  2355. rockchip,pull = <0x4>;
  2356. linux,phandle = <0x5e>;
  2357. phandle = <0x5e>;
  2358. };
  2359.  
  2360. gmac-rxclk {
  2361. rockchip,pins = <0x2b33>;
  2362. rockchip,pull = <0x4>;
  2363. linux,phandle = <0x5f>;
  2364. phandle = <0x5f>;
  2365. };
  2366.  
  2367. gmac-mdio {
  2368. rockchip,pins = <0x2b43>;
  2369. rockchip,pull = <0x4>;
  2370. linux,phandle = <0x60>;
  2371. phandle = <0x60>;
  2372. };
  2373.  
  2374. gmac-txen {
  2375. rockchip,pins = <0x2b53>;
  2376. rockchip,pull = <0x4>;
  2377. linux,phandle = <0x61>;
  2378. phandle = <0x61>;
  2379. };
  2380.  
  2381. gmac-clk {
  2382. rockchip,pins = <0x2b63>;
  2383. rockchip,pull = <0x4>;
  2384. linux,phandle = <0x62>;
  2385. phandle = <0x62>;
  2386. };
  2387.  
  2388. gmac-rxer {
  2389. rockchip,pins = <0x2b73>;
  2390. rockchip,pull = <0x4>;
  2391. linux,phandle = <0x63>;
  2392. phandle = <0x63>;
  2393. };
  2394.  
  2395. gmac-rxd1 {
  2396. rockchip,pins = <0x2c03>;
  2397. rockchip,pull = <0x4>;
  2398. linux,phandle = <0x64>;
  2399. phandle = <0x64>;
  2400. };
  2401.  
  2402. gmac-rxd0 {
  2403. rockchip,pins = <0x2c13>;
  2404. rockchip,pull = <0x4>;
  2405. linux,phandle = <0x65>;
  2406. phandle = <0x65>;
  2407. };
  2408.  
  2409. gmac-txd1 {
  2410. rockchip,pins = <0x2c23>;
  2411. rockchip,pull = <0x4>;
  2412. linux,phandle = <0x66>;
  2413. phandle = <0x66>;
  2414. };
  2415.  
  2416. gmac-txd0 {
  2417. rockchip,pins = <0x2c33>;
  2418. rockchip,pull = <0x4>;
  2419. linux,phandle = <0x67>;
  2420. phandle = <0x67>;
  2421. };
  2422.  
  2423. gmac-rxd3 {
  2424. rockchip,pins = <0x2c44>;
  2425. rockchip,pull = <0x4>;
  2426. linux,phandle = <0x68>;
  2427. phandle = <0x68>;
  2428. };
  2429.  
  2430. gmac-rxd2 {
  2431. rockchip,pins = <0x2c54>;
  2432. rockchip,pull = <0x4>;
  2433. linux,phandle = <0x69>;
  2434. phandle = <0x69>;
  2435. };
  2436.  
  2437. gmac-txd2 {
  2438. rockchip,pins = <0x2c64>;
  2439. rockchip,pull = <0x4>;
  2440. linux,phandle = <0x6a>;
  2441. phandle = <0x6a>;
  2442. };
  2443.  
  2444. gmac-txd3 {
  2445. rockchip,pins = <0x2c74>;
  2446. rockchip,pull = <0x4>;
  2447. linux,phandle = <0x6b>;
  2448. phandle = <0x6b>;
  2449. };
  2450.  
  2451. gmac-col {
  2452. rockchip,pins = <0x2d04>;
  2453. rockchip,pull = <0x4>;
  2454. };
  2455.  
  2456. gmac-col-gpio {
  2457. rockchip,pins = <0x2d00>;
  2458. rockchip,pull = <0x4>;
  2459. linux,phandle = <0x6c>;
  2460. phandle = <0x6c>;
  2461. };
  2462.  
  2463. gmac-mdc {
  2464. rockchip,pins = <0x2d13>;
  2465. rockchip,pull = <0x4>;
  2466. linux,phandle = <0x6d>;
  2467. phandle = <0x6d>;
  2468. };
  2469. };
  2470.  
  2471. gpio2_lcdc0 {
  2472.  
  2473. lcdc0-lcdc {
  2474. rockchip,pins = <0x2b01 0x2b31 0x2b11 0x2b21>;
  2475. rockchip,pull = <0x4>;
  2476. linux,phandle = <0xa0>;
  2477. phandle = <0xa0>;
  2478. };
  2479.  
  2480. lcdc0-gpio {
  2481. rockchip,pins = <0x2b00 0x2b30 0x2b10 0x2b20>;
  2482. rockchip,pull = <0x4>;
  2483. linux,phandle = <0xa1>;
  2484. phandle = <0xa1>;
  2485. };
  2486. };
  2487.  
  2488. gpio2_lcdc0_d {
  2489.  
  2490. lcdc0-lcdc_d {
  2491. rockchip,pins = <0x2b41 0x2b51 0x2b61 0x2b71 0x2c01 0x2c11 0x2c21 0x2c31>;
  2492. rockchip,pull = <0x4>;
  2493. linux,phandle = <0x9c>;
  2494. phandle = <0x9c>;
  2495. };
  2496.  
  2497. lcdc0-lcdc_gpio {
  2498. rockchip,pins = <0x2b40 0x2b50 0x2b60 0x2b70 0x2c00 0x2c10 0x2c20 0x2c30>;
  2499. rockchip,pull = <0x2>;
  2500. };
  2501. };
  2502. };
  2503.  
  2504. cpus {
  2505. #address-cells = <0x1>;
  2506. #size-cells = <0x0>;
  2507.  
  2508. cpu@0 {
  2509. device_type = "cpu";
  2510. compatible = "arm,cortex-a7";
  2511. reg = <0xf00>;
  2512. };
  2513.  
  2514. cpu@1 {
  2515. device_type = "cpu";
  2516. compatible = "arm,cortex-a7";
  2517. reg = <0xf01>;
  2518. };
  2519.  
  2520. cpu@2 {
  2521. device_type = "cpu";
  2522. compatible = "arm,cortex-a7";
  2523. reg = <0xf02>;
  2524. };
  2525.  
  2526. cpu@3 {
  2527. device_type = "cpu";
  2528. compatible = "arm,cortex-a7";
  2529. reg = <0xf03>;
  2530. };
  2531. };
  2532.  
  2533. interrupt-controller@10139000 {
  2534. compatible = "arm,cortex-a15-gic";
  2535. interrupt-controller;
  2536. #interrupt-cells = <0x3>;
  2537. #address-cells = <0x0>;
  2538. reg = <0x10139000 0x1000 0x1013a000 0x1000>;
  2539. linux,phandle = <0x2>;
  2540. phandle = <0x2>;
  2541. };
  2542.  
  2543. arm-pmu {
  2544. compatible = "arm,cortex-a7-pmu";
  2545. interrupts = <0x0 0x4c 0x4 0x0 0x4d 0x4 0x0 0x4e 0x4 0x0 0x4f 0x4>;
  2546. };
  2547.  
  2548. cpu_axi_bus {
  2549. compatible = "rockchip,cpu_axi_bus";
  2550. #address-cells = <0x1>;
  2551. #size-cells = <0x1>;
  2552. ranges;
  2553.  
  2554. qos {
  2555. #address-cells = <0x1>;
  2556. #size-cells = <0x1>;
  2557. ranges;
  2558.  
  2559. crypto {
  2560. reg = <0x10128080 0x20>;
  2561. };
  2562.  
  2563. core {
  2564. reg = <0x1012a000 0x20>;
  2565. };
  2566.  
  2567. peri {
  2568. reg = <0x1012c000 0x20>;
  2569. };
  2570.  
  2571. gpu {
  2572. reg = <0x1012d000 0x20>;
  2573. };
  2574.  
  2575. vpu {
  2576. reg = <0x1012e000 0x20>;
  2577. };
  2578.  
  2579. rga {
  2580. reg = <0x1012f000 0x20>;
  2581. };
  2582.  
  2583. ebc {
  2584. reg = <0x1012f080 0x20>;
  2585. };
  2586.  
  2587. iep {
  2588. reg = <0x1012f100 0x20>;
  2589. };
  2590.  
  2591. lcdc {
  2592. reg = <0x1012f180 0x20>;
  2593. rockchip,priority = <0x3 0x3>;
  2594. };
  2595.  
  2596. vip {
  2597. reg = <0x1012f200 0x20>;
  2598. rockchip,priority = <0x3 0x3>;
  2599. };
  2600. };
  2601.  
  2602. msch {
  2603. #address-cells = <0x1>;
  2604. #size-cells = <0x1>;
  2605. ranges;
  2606.  
  2607. msch@10128000 {
  2608. reg = <0x10128000 0x20>;
  2609. rockchip,read-latency = <0x3f>;
  2610. };
  2611. };
  2612. };
  2613.  
  2614. sram@10080400 {
  2615. compatible = "mmio-sram";
  2616. reg = <0x10080400 0x1c00>;
  2617. map-exec;
  2618. map-cacheable;
  2619. linux,phandle = <0x1>;
  2620. phandle = <0x1>;
  2621. };
  2622.  
  2623. timer {
  2624. compatible = "arm,armv7-timer";
  2625. interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04>;
  2626. clock-frequency = <0x16e3600>;
  2627. };
  2628.  
  2629. timer@20044000 {
  2630. compatible = "rockchip,timer";
  2631. reg = <0x20044000 0x20>;
  2632. interrupts = <0x0 0x1c 0x4>;
  2633. rockchip,broadcast = <0x1>;
  2634. };
  2635.  
  2636. wdt@2004c000 {
  2637. compatible = "rockchip,watch dog";
  2638. reg = <0x2004c000 0x100>;
  2639. clock-names = "pclk_wdt";
  2640. interrupts = <0x0 0x22 0x4>;
  2641. rockchip,irq = <0x1>;
  2642. rockchip,timeout = <0x3c>;
  2643. rockchip,atboot = <0x1>;
  2644. rockchip,debug = <0x0>;
  2645. status = "disabled";
  2646. };
  2647.  
  2648. amba {
  2649. #address-cells = <0x1>;
  2650. #size-cells = <0x1>;
  2651. compatible = "arm,amba-bus";
  2652. interrupt-parent = <0x2>;
  2653. ranges;
  2654.  
  2655. pdma@20078000 {
  2656. compatible = "arm,pl330", "arm,primecell";
  2657. reg = <0x20078000 0x4000>;
  2658. interrupts = <0x0 0x0 0x4 0x0 0x1 0x4>;
  2659. #dma-cells = <0x1>;
  2660. linux,phandle = <0x51>;
  2661. phandle = <0x51>;
  2662. };
  2663. };
  2664.  
  2665. reset@20000110 {
  2666. compatible = "rockchip,reset";
  2667. reg = <0x20000110 0x24>;
  2668. rockchip,reset-flag = <0x1>;
  2669. #reset-cells = <0x1>;
  2670. linux,phandle = <0x9a>;
  2671. phandle = <0x9a>;
  2672. };
  2673.  
  2674. nandc@10500000 {
  2675. compatible = "rockchip,rk-nandc";
  2676. reg = <0x10500000 0x4000>;
  2677. interrupts = <0x0 0x12 0x4>;
  2678. nandc_id = <0x0>;
  2679. clocks = <0x13 0x4e 0x9 0x4f 0xf>;
  2680. clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
  2681. status = "okay";
  2682. };
  2683.  
  2684. nandc0@10500000 {
  2685. compatible = "rockchip,rk-nandc";
  2686. reg = <0x10500000 0x4000>;
  2687. status = "disabled";
  2688. };
  2689.  
  2690. serial@20060000 {
  2691. compatible = "rockchip,serial";
  2692. reg = <0x20060000 0x100>;
  2693. interrupts = <0x0 0x14 0x4>;
  2694. clock-frequency = <0x16e3600>;
  2695. clocks = <0x50 0x4d 0x0>;
  2696. clock-names = "sclk_uart", "pclk_uart";
  2697. reg-shift = <0x2>;
  2698. reg-io-width = <0x4>;
  2699. dmas = <0x51 0x2 0x51 0x3>;
  2700. #dma-cells = <0x2>;
  2701. pinctrl-names = "default";
  2702. pinctrl-0 = <0x52 0x53 0x54>;
  2703. status = "disabled";
  2704. };
  2705.  
  2706. serial@20064000 {
  2707. compatible = "rockchip,serial";
  2708. reg = <0x20064000 0x100>;
  2709. interrupts = <0x0 0x15 0x4>;
  2710. clock-frequency = <0x16e3600>;
  2711. clocks = <0x55 0x4d 0x1>;
  2712. clock-names = "sclk_uart", "pclk_uart";
  2713. reg-shift = <0x2>;
  2714. reg-io-width = <0x4>;
  2715. dmas = <0x51 0x4 0x51 0x5>;
  2716. #dma-cells = <0x2>;
  2717. pinctrl-names = "default";
  2718. pinctrl-0 = <0x56 0x57 0x58>;
  2719. status = "disabled";
  2720. };
  2721.  
  2722. serial@20068000 {
  2723. compatible = "rockchip,serial";
  2724. reg = <0x20068000 0x100>;
  2725. interrupts = <0x0 0x16 0x4>;
  2726. clock-frequency = <0x16e3600>;
  2727. clocks = <0x59 0x4d 0x2>;
  2728. clock-names = "sclk_uart", "pclk_uart";
  2729. reg-shift = <0x2>;
  2730. reg-io-width = <0x4>;
  2731. dmas = <0x51 0x6 0x51 0x7>;
  2732. #dma-cells = <0x2>;
  2733. pinctrl-names = "default";
  2734. pinctrl-0 = <0x5a>;
  2735. status = "disabled";
  2736. };
  2737.  
  2738. eth@2008c000 {
  2739. compatible = "rockchip,rk312x-gmac";
  2740. reg = <0x2008c000 0x4000>;
  2741. interrupts = <0x0 0x38 0x4>;
  2742. interrupt-names = "macirq";
  2743. clocks = <0x40 0x5b 0x6 0x5b 0x7 0x5b 0x4 0x5b 0x5 0x4f 0xa 0x4f 0xb>;
  2744. clock-names = "clk_mac", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac";
  2745. phy-mode = "rgmii";
  2746. pinctrl-names = "default";
  2747. pinctrl-0 = <0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d>;
  2748. status = "disabled";
  2749. };
  2750.  
  2751. fiq-debugger {
  2752. compatible = "rockchip,fiq-debugger";
  2753. rockchip,serial-id = <0x2>;
  2754. rockchip,signal-irq = <0x6a>;
  2755. rockchip,wake-irq = <0x0>;
  2756. status = "okay";
  2757. };
  2758.  
  2759. clocks-init {
  2760. compatible = "rockchip,clocks-init";
  2761. rockchip,clocks-init-parent = <0xc 0xd 0xf 0x10 0x25 0x10 0x2a 0x10 0x2d 0x10 0x15 0x10 0x22 0x10 0x1f 0x10 0x5 0x10 0x6 0x10 0x3d 0x10 0x37 0x14 0x3c 0x10 0x39 0x10 0x32 0x10 0x29 0x10 0x28 0x10 0x27 0x10 0x26 0x10 0x1b 0x10 0x13 0x10 0x1c 0x14>;
  2762. rockchip,clocks-init-rate = <0xc 0x23c34600 0x10 0x2367b880 0x14 0x17d78400 0xf 0x11e1a300 0x42 0x8f0d180 0x44 0x47868c0 0x25 0x11e1a300 0x43 0x8f0d180 0x46 0x47868c0 0x3c 0x11e1a300 0x9 0x11e1a300 0x8 0x8f0d180 0xa 0x11e1a300 0x5 0x11e1a300 0x6 0x11e1a300 0x3d 0xbebc200 0x40 0x7735940>;
  2763. };
  2764.  
  2765. gpu {
  2766. compatible = "arm,mali400";
  2767. reg = <0x10091000 0x200 0x10090000 0x100 0x10093000 0x100 0x10098000 0x1100 0x10094000 0x100 0x1009a000 0x1100 0x10095000 0x100>;
  2768. reg-names = "Mali_L2", "Mali_GP", "Mali_GP_MMU", "Mali_PP0", "Mali_PP0_MMU", "Mali_PP1", "Mali_PP1_MMU";
  2769. interrupts = <0x0 0x3 0x4 0x0 0x4 0x4 0x0 0x5 0x4 0x0 0x4 0x4 0x0 0x5 0x4 0x0 0x4 0x4>;
  2770. interrupt-names = "Mali_GP_IRQ", "Mali_GP_MMU_IRQ", "Mali_PP0_IRQ", "Mali_PP0_MMU_IRQ", "Mali_PP1_IRQ", "Mali_PP1_MMU_IRQ";
  2771. };
  2772.  
  2773. clocks-enable {
  2774. compatible = "rockchip,clocks-enable";
  2775. clocks = <0x6e 0x6 0x6e 0x0 0x6e 0x7 0x6e 0x1 0x6e 0x3 0x6e 0x4 0x6e 0x5 0x6e 0xc 0x4f 0x3 0x4f 0x4 0x4f 0x5 0x4f 0x6 0x4f 0x7 0x4f 0x8 0x5b 0x0 0x43 0x46 0x5b 0x1 0x6f 0xc 0x6f 0xa 0x7 0x5 0x4e 0x4 0x4e 0x7 0x6f 0x3 0x4e 0x1 0x70 0xf 0x70 0x2 0x70 0x3 0x6f 0x2 0x6f 0x0 0x70 0xe 0x6f 0x1 0x71 0xc 0x71 0xd 0x4d 0x2 0x71 0x0>;
  2776. };
  2777.  
  2778. i2c@20072000 {
  2779. compatible = "rockchip,rk30-i2c";
  2780. reg = <0x20072000 0x1000>;
  2781. interrupts = <0x0 0x18 0x4>;
  2782. #address-cells = <0x1>;
  2783. #size-cells = <0x0>;
  2784. pinctrl-names = "default", "gpio";
  2785. pinctrl-0 = <0x72 0x73>;
  2786. pinctrl-1 = <0x74>;
  2787. gpios = <0x75 0x1 0x1 0x75 0x0 0x1>;
  2788. clocks = <0x4d 0x4>;
  2789. rockchip,check-idle = <0x1>;
  2790. status = "okay";
  2791.  
  2792. rk818@1c {
  2793. reg = <0x1c>;
  2794. status = "disabled";
  2795. compatible = "rockchip,rk818";
  2796. rk818,system-power-controller;
  2797. rk818,support_dc_chg = <0x1>;
  2798.  
  2799. regulators {
  2800. #address-cells = <0x1>;
  2801. #size-cells = <0x0>;
  2802.  
  2803. regulator@0 {
  2804. reg = <0x0>;
  2805. regulator-compatible = "rk818_dcdc1";
  2806. regulator-always-on;
  2807. regulator-boot-on;
  2808. regulator-name = "vdd_arm";
  2809. regulator-min-microvolt = <0xaae60>;
  2810. regulator-max-microvolt = <0x16e360>;
  2811. regulator-initial-mode = <0x2>;
  2812. regulator-initial-state = <0x3>;
  2813.  
  2814. regulator-state-mem {
  2815. regulator-state-mode = <0x2>;
  2816. regulator-state-disabled;
  2817. regulator-state-uv = <0xdbba0>;
  2818. };
  2819. };
  2820.  
  2821. regulator@1 {
  2822. reg = <0x1>;
  2823. regulator-compatible = "rk818_dcdc2";
  2824. regulator-always-on;
  2825. regulator-boot-on;
  2826. regulator-name = "vdd_logic";
  2827. regulator-min-microvolt = <0xaae60>;
  2828. regulator-max-microvolt = <0x16e360>;
  2829. regulator-initial-mode = <0x2>;
  2830. regulator-initial-state = <0x3>;
  2831.  
  2832. regulator-state-mem {
  2833. regulator-state-mode = <0x2>;
  2834. regulator-state-enabled;
  2835. regulator-state-uv = <0xdbba0>;
  2836. };
  2837. };
  2838.  
  2839. regulator@2 {
  2840. reg = <0x2>;
  2841. regulator-compatible = "rk818_dcdc3";
  2842. regulator-always-on;
  2843. regulator-boot-on;
  2844. regulator-name = "rk818_dcdc3";
  2845. regulator-min-microvolt = <0x124f80>;
  2846. regulator-max-microvolt = <0x124f80>;
  2847. regulator-initial-mode = <0x2>;
  2848. regulator-initial-state = <0x3>;
  2849.  
  2850. regulator-state-mem {
  2851. regulator-state-mode = <0x2>;
  2852. regulator-state-enabled;
  2853. regulator-state-uv = <0x124f80>;
  2854. };
  2855. };
  2856.  
  2857. regulator@3 {
  2858. reg = <0x3>;
  2859. regulator-compatible = "rk818_dcdc4";
  2860. regulator-always-on;
  2861. regulator-boot-on;
  2862. regulator-name = "vccio";
  2863. regulator-min-microvolt = <0x1b7740>;
  2864. regulator-max-microvolt = <0x325aa0>;
  2865. regulator-initial-mode = <0x2>;
  2866. regulator-initial-state = <0x3>;
  2867.  
  2868. regulator-state-mem {
  2869. regulator-state-mode = <0x2>;
  2870. regulator-state-enabled;
  2871. regulator-state-uv = <0x2ab980>;
  2872. };
  2873. };
  2874.  
  2875. regulator@4 {
  2876. reg = <0x4>;
  2877. regulator-compatible = "rk818_ldo1";
  2878. regulator-always-on;
  2879. regulator-boot-on;
  2880. regulator-name = "rk818_ldo1";
  2881. regulator-min-microvolt = <0x325aa0>;
  2882. regulator-max-microvolt = <0x325aa0>;
  2883. regulator-initial-state = <0x3>;
  2884.  
  2885. regulator-state-mem {
  2886. regulator-state-enabled;
  2887. regulator-state-uv = <0x325aa0>;
  2888. };
  2889. };
  2890.  
  2891. regulator@5 {
  2892. reg = <0x5>;
  2893. regulator-compatible = "rk818_ldo2";
  2894. regulator-always-on;
  2895. regulator-boot-on;
  2896. regulator-name = "rk818_ldo2";
  2897. regulator-min-microvolt = <0x2dc6c0>;
  2898. regulator-max-microvolt = <0x2dc6c0>;
  2899. regulator-initial-state = <0x3>;
  2900.  
  2901. regulator-state-mem {
  2902. regulator-state-enabled;
  2903. regulator-state-uv = <0x2dc6c0>;
  2904. };
  2905. };
  2906.  
  2907. regulator@6 {
  2908. reg = <0x6>;
  2909. regulator-compatible = "rk818_ldo3";
  2910. regulator-always-on;
  2911. regulator-boot-on;
  2912. regulator-name = "rk818_ldo3";
  2913. regulator-min-microvolt = <0x10c8e0>;
  2914. regulator-max-microvolt = <0x10c8e0>;
  2915. regulator-initial-state = <0x3>;
  2916.  
  2917. regulator-state-mem {
  2918. regulator-state-enabled;
  2919. regulator-state-uv = <0x10c8e0>;
  2920. };
  2921. };
  2922.  
  2923. regulator@7 {
  2924. reg = <0x7>;
  2925. regulator-compatible = "rk818_ldo4";
  2926. regulator-always-on;
  2927. regulator-boot-on;
  2928. regulator-name = "rk818_ldo4";
  2929. regulator-min-microvolt = <0x2ab980>;
  2930. regulator-max-microvolt = <0x2ab980>;
  2931. regulator-initial-state = <0x3>;
  2932.  
  2933. regulator-state-mem {
  2934. regulator-state-enabled;
  2935. regulator-state-uv = <0x2625a0>;
  2936. };
  2937. };
  2938.  
  2939. regulator@8 {
  2940. reg = <0x8>;
  2941. regulator-compatible = "rk818_ldo5";
  2942. regulator-always-on;
  2943. regulator-boot-on;
  2944. regulator-name = "rk818_ldo5";
  2945. regulator-min-microvolt = <0x2dc6c0>;
  2946. regulator-max-microvolt = <0x2dc6c0>;
  2947. regulator-initial-state = <0x3>;
  2948.  
  2949. regulator-state-mem {
  2950. regulator-state-enabled;
  2951. regulator-state-uv = <0x2dc6c0>;
  2952. };
  2953. };
  2954.  
  2955. regulator@9 {
  2956. reg = <0x9>;
  2957. regulator-compatible = "rk818_ldo6";
  2958. regulator-always-on;
  2959. regulator-boot-on;
  2960. regulator-name = "rk818_ldo6";
  2961. regulator-min-microvolt = <0x124f80>;
  2962. regulator-max-microvolt = <0x124f80>;
  2963. regulator-initial-state = <0x3>;
  2964.  
  2965. regulator-state-mem {
  2966. regulator-state-enabled;
  2967. regulator-state-uv = <0x124f80>;
  2968. };
  2969. };
  2970.  
  2971. regulator@10 {
  2972. reg = <0xa>;
  2973. regulator-compatible = "rk818_ldo7";
  2974. regulator-always-on;
  2975. regulator-boot-on;
  2976. regulator-name = "rk818_ldo7";
  2977. regulator-min-microvolt = <0x1b7740>;
  2978. regulator-max-microvolt = <0x1b7740>;
  2979. regulator-initial-state = <0x3>;
  2980.  
  2981. regulator-state-mem {
  2982. regulator-state-enabled;
  2983. regulator-state-uv = <0x1b7740>;
  2984. };
  2985. };
  2986.  
  2987. regulator@11 {
  2988. reg = <0xb>;
  2989. regulator-compatible = "rk818_ldo8";
  2990. regulator-always-on;
  2991. regulator-boot-on;
  2992. regulator-name = "rk818_ldo8";
  2993. regulator-min-microvolt = <0x1b7740>;
  2994. regulator-max-microvolt = <0x1b7740>;
  2995. regulator-initial-state = <0x3>;
  2996.  
  2997. regulator-state-mem {
  2998. regulator-state-enabled;
  2999. regulator-state-uv = <0x1b7740>;
  3000. };
  3001. };
  3002.  
  3003. regulator@12 {
  3004. reg = <0xc>;
  3005. regulator-compatible = "rk818_ldo9";
  3006. regulator-always-on;
  3007. regulator-boot-on;
  3008. regulator-name = "vcc_sd";
  3009. regulator-min-microvolt = <0x1b7740>;
  3010. regulator-max-microvolt = <0x2dc6c0>;
  3011. regulator-initial-state = <0x3>;
  3012. linux,phandle = <0x8a>;
  3013. phandle = <0x8a>;
  3014.  
  3015. regulator-state-mem {
  3016. regulator-state-enabled;
  3017. regulator-state-uv = <0x2dc6c0>;
  3018. };
  3019. };
  3020.  
  3021. regulator@13 {
  3022. reg = <0xd>;
  3023. regulator-compatible = "rk818_ldo10";
  3024. regulator-always-on;
  3025. regulator-boot-on;
  3026. regulator-name = "rk818_ldo10";
  3027.  
  3028. regulator-state-mem {
  3029. regulator-state-disabled;
  3030. };
  3031. };
  3032. };
  3033.  
  3034. battery {
  3035. ocv_table = <0xd16 0xe5d 0xe6d 0xe87 0xea8 0xeba 0xebf 0xec2 0xec9 0xed4 0xee4 0xeff 0xf29 0xf43 0xf5d 0xf76 0xf8a 0xfc1 0xff7 0x101b 0x104e>;
  3036. design_capacity = <0x834>;
  3037. design_qmax = <0x898>;
  3038. max_overcharge = <0x64>;
  3039. max_charge_currentmA = <0x5dc>;
  3040. max_charge_voltagemV = <0x10a4>;
  3041. max_bat_voltagemV = <0x1068>;
  3042. sleep_enter_current = <0x64>;
  3043. sleep_exit_current = <0x82>;
  3044. support_uboot_chrg = <0x0>;
  3045. };
  3046. };
  3047.  
  3048. act8931@5b {
  3049. reg = <0x5b>;
  3050. status = "okay";
  3051. compatible = "act,act8931";
  3052. gpios = <0x76 0x9 0x0 0x77 0x2 0x0>;
  3053. act8931,system-power-controller;
  3054.  
  3055. regulators {
  3056. #address-cells = <0x1>;
  3057. #size-cells = <0x0>;
  3058.  
  3059. regulator@0 {
  3060. reg = <0x0>;
  3061. regulator-compatible = "act_dcdc1";
  3062. regulator-always-on;
  3063. regulator-boot-on;
  3064. regulator-name = "vccio";
  3065. regulator-min-microvolt = <0x1b7740>;
  3066. regulator-max-microvolt = <0x325aa0>;
  3067. regulator-initial-mode = <0x2>;
  3068. };
  3069.  
  3070. regulator@1 {
  3071. reg = <0x1>;
  3072. regulator-compatible = "act_dcdc2";
  3073. regulator-always-on;
  3074. regulator-boot-on;
  3075. regulator-name = "act_dcdc2";
  3076. regulator-min-microvolt = <0x16e360>;
  3077. regulator-max-microvolt = <0x16e360>;
  3078. regulator-initial-mode = <0x2>;
  3079. };
  3080.  
  3081. regulator@2 {
  3082. reg = <0x2>;
  3083. regulator-compatible = "act_dcdc3";
  3084. regulator-always-on;
  3085. regulator-boot-on;
  3086. regulator-name = "vdd_arm";
  3087. regulator-min-microvolt = <0xaae60>;
  3088. regulator-max-microvolt = <0x16e360>;
  3089. regulator-initial-mode = <0x2>;
  3090. };
  3091.  
  3092. regulator@3 {
  3093. reg = <0x3>;
  3094. regulator-compatible = "act_ldo1";
  3095. regulator-always-on;
  3096. regulator-boot-on;
  3097. regulator-name = "act_ldo1";
  3098. regulator-min-microvolt = <0x2ab980>;
  3099. regulator-max-microvolt = <0x2ab980>;
  3100. };
  3101.  
  3102. regulator@4 {
  3103. reg = <0x4>;
  3104. regulator-compatible = "act_ldo2";
  3105. regulator-always-on;
  3106. regulator-boot-on;
  3107. regulator-name = "act_ldo2";
  3108. regulator-min-microvolt = <0x1b7740>;
  3109. regulator-max-microvolt = <0x1b7740>;
  3110. };
  3111.  
  3112. regulator@5 {
  3113. reg = <0x5>;
  3114. regulator-compatible = "act_ldo3";
  3115. regulator-always-on;
  3116. regulator-boot-on;
  3117. regulator-name = "act_ldo3";
  3118. regulator-min-microvolt = <0x325aa0>;
  3119. regulator-max-microvolt = <0x325aa0>;
  3120. };
  3121.  
  3122. regulator@6 {
  3123. reg = <0x6>;
  3124. regulator-compatible = "act_ldo4";
  3125. regulator-always-on;
  3126. regulator-boot-on;
  3127. regulator-name = "act_ldo4";
  3128. regulator-min-microvolt = <0x325aa0>;
  3129. regulator-max-microvolt = <0x325aa0>;
  3130. };
  3131. };
  3132. };
  3133.  
  3134. rt5025@35 {
  3135. compatible = "rt,rt5025";
  3136. reg = <0x35>;
  3137. status = "disabled";
  3138.  
  3139. regulator_0 {
  3140. compatible = "rt,rt5025-dcdc1";
  3141. cell-index = <0x0>;
  3142. rt,ramp_sel = <0x0>;
  3143. rt,allow_mode_mask;
  3144. regulator-name = "vdd_arm";
  3145. regulator-min-microvolt = <0xaae60>;
  3146. regulator-max-microvolt = <0x16e360>;
  3147. qcom,comsumer-supplies = "vdd_arm", "";
  3148. regulator-always-on;
  3149. regulator-boot-on;
  3150. };
  3151.  
  3152. regulator_1 {
  3153. compatible = "rt,rt5025-dcdc2";
  3154. cell-index = <0x1>;
  3155. rt,ramp_sel = <0x0>;
  3156. rt,allow_mode_mask;
  3157. regulator-name = "vdd_logic";
  3158. regulator-min-microvolt = <0xaae60>;
  3159. regulator-max-microvolt = <0x16e360>;
  3160. qcom,comsumer-supplies = "vdd_logic", "";
  3161. regulator-always-on;
  3162. regulator-boot-on;
  3163. };
  3164.  
  3165. regulator_2 {
  3166. compatible = "rt,rt5025-dcdc3";
  3167. cell-index = <0x2>;
  3168. rt,ramp_sel = <0x0>;
  3169. rt,allow_mode_mask;
  3170. regulator-name = "rt5025-dcdc3";
  3171. regulator-min-microvolt = <0x1b7740>;
  3172. regulator-max-microvolt = <0x325aa0>;
  3173. qcom,comsumer-supplies = "rt5025-dcdc3", "";
  3174. regulator-always-on;
  3175. regulator-boot-on;
  3176. };
  3177.  
  3178. regulator_3 {
  3179. compatible = "rt,rt5025-dcdc4";
  3180. cell-index = <0x3>;
  3181. regulator-name = "rt5025-dcdc4";
  3182. regulator-min-microvolt = <0x4c4b40>;
  3183. regulator-max-microvolt = <0x4c4b40>;
  3184. qcom,comsumer-supplies = "rt5025-dcdc4", "";
  3185. regulator-always-on;
  3186. regulator-boot-on;
  3187. };
  3188.  
  3189. regulator_4 {
  3190. compatible = "rt,rt5025-ldo1";
  3191. cell-index = <0x4>;
  3192. regulator-name = "rt5025-ldo1";
  3193. regulator-min-microvolt = <0x1b7740>;
  3194. regulator-max-microvolt = <0x1b7740>;
  3195. qcom,comsumer-supplies = "rt5025-ldo1", "";
  3196. regulator-always-on;
  3197. regulator-boot-on;
  3198. };
  3199.  
  3200. regulator_5 {
  3201. compatible = "rt,rt5025-ldo2";
  3202. cell-index = <0x5>;
  3203. regulator-name = "rt5025-ldo2";
  3204. regulator-min-microvolt = <0x124f80>;
  3205. regulator-max-microvolt = <0x124f80>;
  3206. qcom,comsumer-supplies = "rt5025-ldo2", "";
  3207. regulator-always-on;
  3208. regulator-boot-on;
  3209. };
  3210.  
  3211. regulator_6 {
  3212. compatible = "rt,rt5025-ldo3";
  3213. cell-index = <0x6>;
  3214. regulator-name = "rt5025-ldo3";
  3215. regulator-min-microvolt = <0x2ab980>;
  3216. regulator-max-microvolt = <0x2ab980>;
  3217. qcom,comsumer-supplies = "rt5025-ldo3", "";
  3218. regulator-always-on;
  3219. regulator-boot-on;
  3220. };
  3221.  
  3222. regulator_7 {
  3223. compatible = "rt,rt5025-ldo4";
  3224. cell-index = <0x7>;
  3225. regulator-name = "rt5025-ldo4";
  3226. regulator-min-microvolt = <0x325aa0>;
  3227. regulator-max-microvolt = <0x325aa0>;
  3228. qcom,comsumer-supplies = "rt5025-ldo4", "";
  3229. regulator-always-on;
  3230. regulator-boot-on;
  3231. };
  3232.  
  3233. regulator_8 {
  3234. compatible = "rt,rt5025-ldo5";
  3235. cell-index = <0x8>;
  3236. regulator-name = "rt5025-ldo5";
  3237. regulator-min-microvolt = <0x1b7740>;
  3238. regulator-max-microvolt = <0x1b7740>;
  3239. qcom,comsumer-supplies = "rt5025-ldo5", "";
  3240. regulator-always-on;
  3241. regulator-boot-on;
  3242. };
  3243.  
  3244. regulator_9 {
  3245. compatible = "rt,rt5025-ldo6";
  3246. cell-index = <0x9>;
  3247. regulator-name = "rt5025-ldo6";
  3248. regulator-min-microvolt = <0x50910>;
  3249. regulator-max-microvolt = <0x325aa0>;
  3250. qcom,comsumer-supplies = "rt5025-ldo6", "";
  3251. regulator-always-on;
  3252. regulator-boot-on;
  3253. };
  3254.  
  3255. rt5025-charger {
  3256. compatible = "rt,rt5025-charger";
  3257. rt,te_en;
  3258. rt,iprec = <0x0>;
  3259. rt,ieoc = <0x0>;
  3260. rt,vprec = <0x5>;
  3261. rt,vdpm = <0x2>;
  3262. rt,chg_volt = <0x1068>;
  3263. rt,acchg_icc = <0x7d0>;
  3264. rt,usbtachg_icc = <0x7d0>;
  3265. rt,usbchg_icc = <0x1f4>;
  3266. rt,screenon_icc = <0x1f4>;
  3267. rt,temp = <0x0 0x96 0x1f4 0x258>;
  3268. rt,temp_scalar = <0x30 0x2b 0x28 0x22 0x15 0x10 0x10 0xd>;
  3269. };
  3270.  
  3271. rt5025-battery {
  3272. compatible = "rt,rt5025-battery";
  3273. };
  3274.  
  3275. rt5025-gpio {
  3276. compatible = "rt,rt5025-gpio";
  3277. gpio-controller;
  3278. #gpio-cells = <0x2>;
  3279. rt,ngpio = <0x3>;
  3280. };
  3281.  
  3282. rt5025-misc {
  3283. compatible = "rt,rt5025-misc";
  3284. rt,vsyslv = <0x2>;
  3285. rt,shdnlpress_time = <0x1>;
  3286. rt,startlpress_time = <0x0>;
  3287. rt,vsyslv_enshdn;
  3288. rt,system-power-controller;
  3289. };
  3290.  
  3291. rt5025-debug {
  3292. compatible = "rt,rt5025-debug";
  3293. };
  3294.  
  3295. rt5025-irq {
  3296. compatible = "rt,rt5025-irq";
  3297. };
  3298. };
  3299.  
  3300. rt5036@38 {
  3301. compatible = "rt,rt5036";
  3302. reg = <0x38>;
  3303. status = "disabled";
  3304.  
  3305. regulator_0 {
  3306. compatible = "rt,rt5036-dcdc1";
  3307. cell-index = <0x0>;
  3308. rt,nramp_sel = <0x0>;
  3309. rt,sramp_sel = <0x0>;
  3310. rt,allow_mode_mask;
  3311. regulator-name = "vdd_arm";
  3312. regulator-min-microvolt = <0xc3500>;
  3313. regulator-max-microvolt = <0x325aa0>;
  3314. qcom,comsumer-supplies = "vdd_arm", "";
  3315. regulator-always-on;
  3316. regulator-boot-on;
  3317. rt,standby_enabled;
  3318. rt,standby_vol = <0xe7ef0>;
  3319. };
  3320.  
  3321. regulator_1 {
  3322. compatible = "rt,rt5036-dcdc2";
  3323. cell-index = <0x1>;
  3324. rt,nramp_sel = <0x0>;
  3325. rt,sramp_sel = <0x0>;
  3326. rt,allow_mode_mask;
  3327. regulator-name = "vdd_logic";
  3328. regulator-min-microvolt = <0xc3500>;
  3329. regulator-max-microvolt = <0x325aa0>;
  3330. qcom,comsumer-supplies = "vdd_logic", "";
  3331. regulator-always-on;
  3332. regulator-boot-on;
  3333. rt,standby_enabled;
  3334. rt,standby_vol = <0xe7ef0>;
  3335. };
  3336.  
  3337. regulator_2 {
  3338. compatible = "rt,rt5036-dcdc3";
  3339. cell-index = <0x2>;
  3340. rt,nramp_sel = <0x0>;
  3341. rt,sramp_sel = <0x0>;
  3342. rt,allow_mode_mask;
  3343. regulator-name = "rt5036-dcdc3";
  3344. regulator-min-microvolt = <0xc3500>;
  3345. regulator-max-microvolt = <0x325aa0>;
  3346. qcom,comsumer-supplies = "rt5036-dcdc3", "";
  3347. regulator-always-on;
  3348. regulator-boot-on;
  3349. rt,standby_enabled;
  3350. rt,standby_vol = <0x2ab980>;
  3351. };
  3352.  
  3353. regulator_3 {
  3354. compatible = "rt,rt5036-dcdc4";
  3355. cell-index = <0x3>;
  3356. rt,nramp_sel = <0x0>;
  3357. rt,sramp_sel = <0x0>;
  3358. rt,allow_mode_mask;
  3359. regulator-name = "rt5036-dcdc4";
  3360. regulator-min-microvolt = <0xc3500>;
  3361. regulator-max-microvolt = <0x325aa0>;
  3362. qcom,comsumer-supplies = "rt5036-dcdc4", "";
  3363. regulator-always-on;
  3364. regulator-boot-on;
  3365. rt,standby_enabled;
  3366. rt,standby_vol = <0x124f80>;
  3367. };
  3368.  
  3369. regulator_4 {
  3370. supply-regulator = "rt5036-dcdc3";
  3371. compatible = "rt,rt5036-ldo1";
  3372. cell-index = <0x4>;
  3373. rt,nramp_sel = <0x0>;
  3374. rt,sramp_sel = <0x0>;
  3375. rt,allow_mode_mask;
  3376. regulator-name = "rt5036-ldo1";
  3377. regulator-min-microvolt = <0x124f80>;
  3378. regulator-max-microvolt = <0x124f80>;
  3379. qcom,comsumer-supplies = "rt5036-ldo1", "";
  3380. regulator-always-on;
  3381. regulator-boot-on;
  3382. rt,standby_enabled;
  3383. rt,standby_vol = <0x124f80>;
  3384. };
  3385.  
  3386. regulator_5 {
  3387. supply-regulator = "rt5036-dcdc3";
  3388. compatible = "rt,rt5036-ldo2";
  3389. cell-index = <0x5>;
  3390. rt,nramp_sel = <0x0>;
  3391. rt,sramp_sel = <0x0>;
  3392. rt,allow_mode_mask;
  3393. regulator-name = "rt5036-ldo2";
  3394. regulator-min-microvolt = <0x10c8e0>;
  3395. regulator-max-microvolt = <0x10c8e0>;
  3396. qcom,comsumer-supplies = "rt5036-ldo2", "";
  3397. regulator-always-on;
  3398. regulator-boot-on;
  3399. rt,standby_enabled;
  3400. rt,standby_vol = <0x10c8e0>;
  3401. };
  3402.  
  3403. regulator_6 {
  3404. supply-regulator = "rt5036-dcdc3";
  3405. compatible = "rt,rt5036-ldo3";
  3406. cell-index = <0x6>;
  3407. rt,nramp_sel = <0x0>;
  3408. rt,sramp_sel = <0x0>;
  3409. rt,allow_mode_mask;
  3410. regulator-name = "rt5036-ldo3";
  3411. regulator-min-microvolt = <0x1b7740>;
  3412. regulator-max-microvolt = <0x1b7740>;
  3413. qcom,comsumer-supplies = "rt5036-ldo3", "";
  3414. regulator-always-on;
  3415. regulator-boot-on;
  3416. rt,standby_enabled;
  3417. rt,standby_vol = <0x1b7740>;
  3418. };
  3419.  
  3420. regulator_7 {
  3421. supply-regulator = "rt5036-dcdc3";
  3422. compatible = "rt,rt5036-ldo4";
  3423. cell-index = <0x7>;
  3424. rt,nramp_sel = <0x0>;
  3425. rt,sramp_sel = <0x0>;
  3426. rt,allow_mode_mask;
  3427. regulator-name = "rt5036-ldo4";
  3428. regulator-min-microvolt = <0x1b7740>;
  3429. regulator-max-microvolt = <0x1b7740>;
  3430. qcom,comsumer-supplies = "rt5036-ldo4", "";
  3431. regulator-always-on;
  3432. regulator-boot-on;
  3433. rt,standby_enabled;
  3434. rt,standby_vol = <0x1b7740>;
  3435. };
  3436.  
  3437. regulator_8 {
  3438. supply-regulator = "rt5036-dcdc3";
  3439. compatible = "rt,rt5036-lsw1";
  3440. cell-index = <0x8>;
  3441. rt,nramp_sel = <0x0>;
  3442. rt,sramp_sel = <0x0>;
  3443. rt,allow_mode_mask;
  3444. regulator-name = "rt5036-ldo5";
  3445. qcom,comsumer-supplies = "rt5036-ldo5", "";
  3446. regulator-always-on;
  3447. regulator-boot-on;
  3448. rt,standby_enabled;
  3449. };
  3450.  
  3451. regulator_9 {
  3452. supply-regulator = "rt5036-dcdc3";
  3453. compatible = "rt,rt5036-lsw2";
  3454. cell-index = <0x9>;
  3455. rt,nramp_sel = <0x0>;
  3456. rt,sramp_sel = <0x0>;
  3457. rt,allow_mode_mask;
  3458. regulator-name = "rt5036-ldo6";
  3459. qcom,comsumer-supplies = "rt5036-ldo6", "";
  3460. regulator-always-on;
  3461. regulator-boot-on;
  3462. rt,standby_enabled;
  3463. };
  3464.  
  3465. rt5036-rtc {
  3466. compatible = "rt,rt5036-rtc";
  3467. };
  3468.  
  3469. rt5036-misc {
  3470. compatible = "rt,rt5036-misc";
  3471. rt,shdn_press = <0x1>;
  3472. rt,stb_en = <0x1>;
  3473. rt,lp_enshdn;
  3474. rt,vsysuvlo = <0x2>;
  3475. rt,syslv_enshdn;
  3476. rt,system-power-controller;
  3477. };
  3478.  
  3479. rt5036-debug {
  3480. compatible = "rt,rt5036-debug";
  3481. };
  3482.  
  3483. rt5036-irq {
  3484. compatible = "rt,rt5036-irq";
  3485. };
  3486.  
  3487. rt5036-charger {
  3488. compatible = "rt,rt5036-charger";
  3489. rt,te_en;
  3490. rt,iprec = <0x2>;
  3491. rt,ieoc = <0x3>;
  3492. rt,vprec = <0xa>;
  3493. rt,batlv = <0x4>;
  3494. rt,vrechg = <0x1>;
  3495. rt,chg_volt = <0x1068>;
  3496. rt,otg_volt = <0x13a1>;
  3497. rt,acchg_icc = <0x7d0>;
  3498. rt,usbtachg_icc = <0x7d0>;
  3499. rt,usbchg_icc = <0x384>;
  3500. };
  3501. };
  3502.  
  3503. axp_mfd@34 {
  3504. compatible = "axp_mfd";
  3505. reg = <0x34>;
  3506. irq_gpio_number = <0x77 0x5 0x8>;
  3507. status = "okay";
  3508. };
  3509. };
  3510.  
  3511. i2c@20056000 {
  3512. compatible = "rockchip,rk30-i2c";
  3513. reg = <0x20056000 0x1000>;
  3514. interrupts = <0x0 0x19 0x4>;
  3515. #address-cells = <0x1>;
  3516. #size-cells = <0x0>;
  3517. pinctrl-names = "default", "gpio";
  3518. pinctrl-0 = <0x78 0x79>;
  3519. pinctrl-1 = <0x7a>;
  3520. gpios = <0x75 0x3 0x1 0x75 0x2 0x1>;
  3521. clocks = <0x4d 0x5>;
  3522. rockchip,check-idle = <0x1>;
  3523. status = "okay";
  3524.  
  3525. sensor@4c {
  3526. compatible = "gs_mc3230";
  3527. reg = <0x4c>;
  3528. type = <0x2>;
  3529. irq_enable = <0x0>;
  3530. poll_delay_ms = <0x1e>;
  3531. layout = <0x1>;
  3532. status = "okay";
  3533. };
  3534.  
  3535. sensor@15 {
  3536. compatible = "gs_mxc6225";
  3537. reg = <0x15>;
  3538. type = <0x2>;
  3539. irq_enable = <0x0>;
  3540. poll_delay_ms = <0x1e>;
  3541. layout = <0x1>;
  3542. status = "okay";
  3543. };
  3544.  
  3545. rtc@51 {
  3546. compatible = "rtc,hym8563";
  3547. reg = <0x51>;
  3548. status = "okay";
  3549. irq_gpio = <0x76 0xa 0x2>;
  3550. };
  3551. };
  3552.  
  3553. i2c@2005a000 {
  3554. compatible = "rockchip,rk30-i2c";
  3555. reg = <0x2005a000 0x1000>;
  3556. interrupts = <0x0 0x1a 0x4>;
  3557. #address-cells = <0x1>;
  3558. #size-cells = <0x0>;
  3559. pinctrl-names = "default", "gpio";
  3560. pinctrl-0 = <0x7b 0x7c>;
  3561. pinctrl-1 = <0x7d>;
  3562. gpios = <0x76 0x14 0x1 0x76 0x15 0x1>;
  3563. clocks = <0x4d 0x6>;
  3564. rockchip,check-idle = <0x1>;
  3565. status = "okay";
  3566.  
  3567. ts@55 {
  3568. compatible = "goodix,gt8xx";
  3569. reg = <0x55>;
  3570. touch-gpio = <0x77 0x8 0x8>;
  3571. reset-gpio = <0x76 0x11 0x1>;
  3572. max-x = <0x500>;
  3573. max-y = <0x320>;
  3574. status = "disabled";
  3575. };
  3576.  
  3577. ts@76 {
  3578. compatible = "zet6221-ts";
  3579. reg = <0x76>;
  3580. pinctrl-names = "default", "gpio";
  3581. pinctrl-0 = <0x72 0x73>;
  3582. pinctrl-1 = <0x74>;
  3583. irq_gpio_number = <0x76 0x11 0x8>;
  3584. rst_gpio_number = <0x76 0x10 0x1>;
  3585. };
  3586. };
  3587.  
  3588. i2c@2005e000 {
  3589. compatible = "rockchip,rk30-i2c";
  3590. reg = <0x2005e000 0x1000>;
  3591. interrupts = <0x0 0x1b 0x4>;
  3592. #address-cells = <0x1>;
  3593. #size-cells = <0x0>;
  3594. pinctrl-names = "default", "gpio";
  3595. pinctrl-0 = <0x7e 0x7f>;
  3596. pinctrl-1 = <0x80>;
  3597. gpios = <0x75 0x7 0x1 0x75 0x6 0x1>;
  3598. clocks = <0x4d 0x7>;
  3599. rockchip,check-idle = <0x1>;
  3600. status = "disabled";
  3601. };
  3602.  
  3603. i2s0@10220000 {
  3604. compatible = "rockchip-i2s";
  3605. reg = <0x10220000 0x1000>;
  3606. i2s-id = <0x0>;
  3607. clocks = <0x1a 0x3e 0x81 0x2>;
  3608. clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
  3609. interrupts = <0x0 0x13 0x4>;
  3610. dmas = <0x51 0x0 0x51 0x1>;
  3611. dma-names = "tx", "rx";
  3612. status = "okay";
  3613. sdi_source = <0x1>;
  3614. };
  3615.  
  3616. i2s1@10200000 {
  3617. compatible = "rockchip-i2s";
  3618. reg = <0x10200000 0x1000>;
  3619. i2s-id = <0x1>;
  3620. clocks = <0x47 0x81 0x4>;
  3621. clock-names = "i2s_clk", "i2s_hclk";
  3622. interrupts = <0x0 0x44 0x4>;
  3623. dmas = <0x51 0xe 0x51 0xf>;
  3624. dma-names = "tx", "rx";
  3625. linux,phandle = <0xaf>;
  3626. phandle = <0xaf>;
  3627. };
  3628.  
  3629. spdif@10204000 {
  3630. compatible = "rockchip-spdif";
  3631. reg = <0x10204000 0x1000>;
  3632. clocks = <0x82 0x4f 0x9>;
  3633. clock-names = "spdif_mclk", "spdif_hclk";
  3634. interrupts = <0x0 0x37 0x4>;
  3635. dmas = <0x51 0xd>;
  3636. dma-names = "tx";
  3637. pinctrl-names = "default";
  3638. pinctrl-0 = <0x83>;
  3639. linux,phandle = <0xad>;
  3640. phandle = <0xad>;
  3641. };
  3642.  
  3643. mipi@10110000 {
  3644. compatible = "rockchip,rk312x-dsi";
  3645. rockchip,prop = <0x0>;
  3646. reg = <0x10110000 0x4000 0x20038000 0x4000>;
  3647. reg-names = "mipi_dsi_host", "mipi_dsi_phy";
  3648. interrupts = <0x0 0x13 0x4>;
  3649. clocks = <0x5b 0xf 0x4e 0x0 0x70 0x6 0x70 0x5 0x84>;
  3650. clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "hclk_vio_h2p", "pd_mipi_dsi";
  3651. status = "okay";
  3652. };
  3653.  
  3654. rksdmmc@1021c000 {
  3655. compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
  3656. reg = <0x1021c000 0x4000>;
  3657. interrupts = <0x0 0x10 0x4>;
  3658. #address-cells = <0x1>;
  3659. #size-cells = <0x0>;
  3660. clocks = <0x29 0x81 0x0>;
  3661. clock-names = "clk_mmc", "hclk_mmc";
  3662. dmas = <0x51 0xc>;
  3663. dma-names = "dw_mci";
  3664. num-slots = <0x1>;
  3665. fifo-depth = <0x100>;
  3666. bus-width = <0x8>;
  3667. clock-frequency = <0x2faf080>;
  3668. clock-freq-min-max = <0x61a80 0x2faf080>;
  3669. supports-highspeed;
  3670. supports-emmc;
  3671. bootpart-no-access;
  3672. supports-DDR_MODE;
  3673. ignore-pm-notify;
  3674. keep-power-in-suspend;
  3675. status = "disabled";
  3676. };
  3677.  
  3678. rksdmmc@10214000 {
  3679. compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
  3680. reg = <0x10214000 0x4000>;
  3681. interrupts = <0x0 0xe 0x4>;
  3682. #address-cells = <0x1>;
  3683. #size-cells = <0x0>;
  3684. pinctrl-names = "default", "idle", "udbg";
  3685. pinctrl-0 = <0x85 0x86 0x87 0x88>;
  3686. pinctrl-1 = <0x89>;
  3687. pinctrl-2 = <0x5a>;
  3688. clocks = <0x26 0x4e 0xa>;
  3689. clock-names = "clk_mmc", "hclk_mmc";
  3690. dmas = <0x51 0xa>;
  3691. dma-names = "dw_mci";
  3692. num-slots = <0x1>;
  3693. fifo-depth = <0x100>;
  3694. bus-width = <0x4>;
  3695. clock-frequency = <0x23c3460>;
  3696. clock-freq-min-max = <0x61a80 0x23c3460>;
  3697. supports-highspeed;
  3698. supports-sd;
  3699. broken-cd;
  3700. card-detect-delay = <0x1f4>;
  3701. ignore-pm-notify;
  3702. keep-power-in-suspend;
  3703. vmmc-supply = <0x8a>;
  3704. status = "okay";
  3705. cd-gpios = <0x76 0x7 0x0>;
  3706. };
  3707.  
  3708. rksdmmc@10218000 {
  3709. compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
  3710. reg = <0x10218000 0x4000>;
  3711. interrupts = <0x0 0xf 0x4>;
  3712. #address-cells = <0x1>;
  3713. #size-cells = <0x0>;
  3714. pinctrl-names = "default", "idle";
  3715. pinctrl-0 = <0x8b 0x8c 0x8d 0x8e>;
  3716. pinctrl-1 = <0x8f>;
  3717. clocks = <0x28 0x4e 0xb>;
  3718. clock-names = "clk_mmc", "hclk_mmc";
  3719. dmas = <0x51 0xb>;
  3720. dma-names = "dw_mci";
  3721. num-slots = <0x1>;
  3722. fifo-depth = <0x100>;
  3723. bus-width = <0x4>;
  3724. clock-frequency = <0x23c3460>;
  3725. clock-freq-min-max = <0x30d40 0x23c3460>;
  3726. supports-highspeed;
  3727. supports-sdio;
  3728. ignore-pm-notify;
  3729. keep-power-in-suspend;
  3730. cap-sdio-irq;
  3731. status = "disabled";
  3732. };
  3733.  
  3734. spi@20074000 {
  3735. compatible = "rockchip,rockchip-spi";
  3736. reg = <0x20074000 0x1000>;
  3737. interrupts = <0x0 0x17 0x4>;
  3738. #address-cells = <0x1>;
  3739. #size-cells = <0x0>;
  3740. pinctrl-names = "default";
  3741. pinctrl-0 = <0x90 0x91 0x92 0x93 0x94>;
  3742. rockchip,spi-src-clk = <0x0>;
  3743. num-cs = <0x2>;
  3744. clocks = <0x33 0x81 0xc>;
  3745. clock-names = "spi", "pclk_spi0";
  3746. dmas = <0x51 0x8 0x51 0x9>;
  3747. #dma-cells = <0x2>;
  3748. dma-names = "tx", "rx";
  3749. status = "okay";
  3750. max-freq = <0x47868c0>;
  3751. };
  3752.  
  3753. adc@2006c000 {
  3754. compatible = "rockchip,saradc";
  3755. reg = <0x2006c000 0x100>;
  3756. interrupts = <0x0 0x11 0x4>;
  3757. #io-channel-cells = <0x1>;
  3758. io-channel-ranges;
  3759. rockchip,adc-vref = <0x708>;
  3760. clock-frequency = <0xf4240>;
  3761. clocks = <0x41 0x81 0xe>;
  3762. clock-names = "saradc", "pclk_saradc";
  3763. status = "okay";
  3764. linux,phandle = <0x95>;
  3765. phandle = <0x95>;
  3766.  
  3767. key {
  3768. compatible = "rockchip,key";
  3769. io-channels = <0x95 0x2>;
  3770.  
  3771. back-key {
  3772. linux,code = <0x9e>;
  3773. label = "back";
  3774. rockchip,adc_value = <0x1>;
  3775. };
  3776.  
  3777. power-key {
  3778. gpios = <0x77 0x4 0x1>;
  3779. linux,code = <0x74>;
  3780. label = "power";
  3781. gpio-key,wakeup;
  3782. };
  3783. };
  3784.  
  3785. adc-battery {
  3786. status = "disabled";
  3787. compatible = "rk30-adc-battery";
  3788. io-channels = <0x95 0x0 0x95 0x3>;
  3789. dc_det_gpio = <0x76 0x9 0x1>;
  3790. auto_calibration = <0x0>;
  3791. ref_voltage = <0xce4>;
  3792. bat_table = <0x0 0x0 0x0 0x0 0x64 0x64 0xdac 0xe23 0xe5e 0xe96 0xe9e 0xec7 0xee5 0xf2c 0xf80 0x100e 0x107c 0xea6 0xe7e 0xeba 0xef6 0xf0a 0xf28 0xf46 0xf8c 0xfdc 0x1090 0x10cc>;
  3793. is_dc_charge = <0x1>;
  3794. is_usb_charge = <0x1>;
  3795. };
  3796. };
  3797.  
  3798. pwm@20050000 {
  3799. compatible = "rockchip,rk-pwm";
  3800. reg = <0x20050000 0x10>;
  3801. #pwm-cells = <0x2>;
  3802. pinctrl-names = "default";
  3803. pinctrl-0 = <0x96>;
  3804. clocks = <0x81 0xa>;
  3805. clock-names = "pclk_pwm";
  3806. status = "okay";
  3807. linux,phandle = <0xb4>;
  3808. phandle = <0xb4>;
  3809. };
  3810.  
  3811. pwm@20050010 {
  3812. compatible = "rockchip,rk-pwm";
  3813. reg = <0x20050010 0x10>;
  3814. #pwm-cells = <0x2>;
  3815. pinctrl-names = "default";
  3816. pinctrl-0 = <0x97>;
  3817. clocks = <0x81 0xa>;
  3818. clock-names = "pclk_pwm";
  3819. status = "okay";
  3820. linux,phandle = <0xb1>;
  3821. phandle = <0xb1>;
  3822. };
  3823.  
  3824. pwm@20050020 {
  3825. compatible = "rockchip,rk-pwm";
  3826. reg = <0x20050020 0x10>;
  3827. #pwm-cells = <0x2>;
  3828. pinctrl-names = "default";
  3829. pinctrl-0 = <0x98>;
  3830. clocks = <0x81 0xa>;
  3831. clock-names = "pclk_pwm";
  3832. status = "disabled";
  3833. linux,phandle = <0xb2>;
  3834. phandle = <0xb2>;
  3835. };
  3836.  
  3837. pwm@20050030 {
  3838. compatible = "rockchip,remotectl-pwm";
  3839. reg = <0x20050030 0x10>;
  3840. #pwm-cells = <0x2>;
  3841. pinctrl-names = "default";
  3842. pinctrl-0 = <0x99>;
  3843. clocks = <0x81 0xa>;
  3844. clock-names = "pclk_pwm";
  3845. status = "okay";
  3846. remote_pwm_id = <0x3>;
  3847. interrupts = <0x0 0x1e 0x4>;
  3848. };
  3849.  
  3850. dwc-control-usb@20008000 {
  3851. compatible = "rockchip,rk3126-dwc-control-usb";
  3852. reg = <0x20008000 0x4>;
  3853. interrupts = <0x0 0x23 0x4>;
  3854. interrupt-names = "otg_bvalid";
  3855. clocks = <0x70 0xd>;
  3856. clock-names = "hclk_usb_peri";
  3857. rockchip,remote_wakeup;
  3858. rockchip,usb_irq_wakeup;
  3859. resets = <0x9a 0x69>;
  3860. reset-names = "usbphy_por";
  3861.  
  3862. usb_bc {
  3863. compatible = "inno,phy";
  3864. regbase = "/dwc-control-usb@20008000";
  3865. rk_usb,bvalid = <0x14c 0x5 0x1>;
  3866. rk_usb,iddig = <0x14c 0x8 0x1>;
  3867. rk_usb,vdmsrcen = <0x184 0xc 0x1>;
  3868. rk_usb,vdpsrcen = <0x184 0xb 0x1>;
  3869. rk_usb,rdmpden = <0x184 0xa 0x1>;
  3870. rk_usb,idpsrcen = <0x184 0x9 0x1>;
  3871. rk_usb,idmsinken = <0x184 0x8 0x1>;
  3872. rk_usb,idpsinken = <0x184 0x7 0x1>;
  3873. rk_usb,dpattach = <0x2c0 0x7 0x1>;
  3874. rk_usb,cpdet = <0x2c0 0x6 0x1>;
  3875. rk_usb,dcpattach = <0x2c0 0x5 0x1>;
  3876. };
  3877.  
  3878. usb_uart {
  3879. status = "disabled";
  3880. };
  3881. };
  3882.  
  3883. usb@10180000 {
  3884. compatible = "rockchip,rk3126_usb20_otg";
  3885. reg = <0x10180000 0x40000>;
  3886. interrupts = <0x0 0xa 0x4>;
  3887. clocks = <0x71 0x5 0x4e 0xd>;
  3888. clock-names = "clk_usbphy0", "hclk_usb0";
  3889. resets = <0x9a 0x45 0x9a 0x67 0x9a 0x47>;
  3890. reset-names = "otg_ahb", "otg_phy", "otg_controller";
  3891. rockchip,usb-mode = <0x0>;
  3892. };
  3893.  
  3894. usb@101c0000 {
  3895. compatible = "rockchip,rk3126_ehci";
  3896. reg = <0x101c0000 0x20000>;
  3897. interrupts = <0x0 0xb 0x4>;
  3898. clocks = <0x71 0x6 0x81 0x3>;
  3899. clock-names = "clk_usbphy1", "hclk_host0";
  3900. resets = <0x9a 0x48 0x9a 0x68 0x9a 0x4a>;
  3901. reset-names = "host_ahb", "host_phy", "host_controller";
  3902. };
  3903.  
  3904. usb@101e0000 {
  3905. compatible = "rockchip,rk3126_ohci";
  3906. reg = <0x101e0000 0x20000>;
  3907. interrupts = <0x0 0x20 0x4>;
  3908. };
  3909.  
  3910. fb {
  3911. compatible = "rockchip,rk-fb";
  3912. rockchip,disp-mode = <0x0>;
  3913. rockchip,uboot-logo-on = <0x1>;
  3914. };
  3915.  
  3916. rk_screen {
  3917. compatible = "rockchip,screen";
  3918. display-timings = <0x9b>;
  3919. };
  3920.  
  3921. lvds@20038000 {
  3922. compatible = "rockchip,rk31xx-lvds";
  3923. reg = <0x20038000 0x4000 0x101100b0 0x1>;
  3924. reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
  3925. clocks = <0x4e 0x0 0x70 0x6 0x70 0x5>;
  3926. clock-names = "pclk_lvds", "pclk_lvds_ctl", "hclk_vio_h2p";
  3927. status = "okay";
  3928. pinctrl-names = "lcdc";
  3929. pinctrl-0 = <0x9c>;
  3930. };
  3931.  
  3932. lcdc@1010e000 {
  3933. compatible = "rockchip,rk312x-lcdc";
  3934. rockchip,prop = <0x1>;
  3935. reg = <0x1010e000 0x1000>;
  3936. interrupts = <0x0 0x9 0x4>;
  3937. clocks = <0x9d 0x0 0x36 0x9d 0x1 0x37 0x9e 0x14>;
  3938. clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc", "pd_lcdc", "sclk_pll";
  3939. rockchip,iommu-enabled = <0x1>;
  3940. status = "okay";
  3941. backlight = <0x9f>;
  3942. pinctrl-names = "default", "gpio";
  3943. pinctrl-0 = <0xa0>;
  3944. pinctrl-1 = <0xa1>;
  3945. rockchip,fb-win-map = <0x0>;
  3946.  
  3947. power_ctr {
  3948. rockchip,debug = <0x0>;
  3949.  
  3950. lcd_en {
  3951. rockchip,power_type = <0x0>;
  3952. gpios = <0x76 0x12 0x0>;
  3953. rockchip,delay = <0x32>;
  3954. };
  3955.  
  3956. lcd_sybyb {
  3957. rockchip,power_type = <0x0>;
  3958. gpios = <0x76 0xd 0x0>;
  3959. rockchip,delay = <0x32>;
  3960. };
  3961. };
  3962. };
  3963.  
  3964. hdmi@20034000 {
  3965. compatible = "rockchip,rk312x-hdmi";
  3966. reg = <0x20034000 0x4000>;
  3967. interrupts = <0x0 0x2d 0x4>;
  3968. rockchip,hdmi_lcdc_source = <0x0>;
  3969. pinctrl-names = "default", "gpio";
  3970. pinctrl-0 = <0xa2 0xa3 0xa4 0xa5>;
  3971. pinctrl-1 = <0xa6>;
  3972. clocks = <0x7 0x8 0xa7>;
  3973. clock-names = "pclk_hdmi", "pd_hdmi";
  3974. rockchip,hdcp_enable = <0x0>;
  3975. rockchip,cec_enable = <0x0>;
  3976. status = "disabled";
  3977. };
  3978.  
  3979. tve {
  3980. compatible = "rockchip,rk312x-tve";
  3981. reg = <0x1010e200 0x100>;
  3982. status = "disabled";
  3983. };
  3984.  
  3985. vpu_service {
  3986. compatible = "rockchip,vpu_sub";
  3987. iommu_enabled = <0x1>;
  3988. reg = <0x10106000 0x800>;
  3989. interrupts = <0x0 0x6 0x4 0x0 0x7 0x4>;
  3990. interrupt-names = "irq_enc", "irq_dec";
  3991. dev_mode = <0x0>;
  3992. linux,phandle = <0xa8>;
  3993. phandle = <0xa8>;
  3994. };
  3995.  
  3996. hevc_service {
  3997. compatible = "rockchip,hevc_sub";
  3998. iommu_enabled = <0x1>;
  3999. reg = <0x10104000 0x400>;
  4000. interrupts = <0x0 0x42 0x4>;
  4001. interrupt-names = "irq_dec";
  4002. dev_mode = <0x1>;
  4003. linux,phandle = <0xa9>;
  4004. phandle = <0xa9>;
  4005. };
  4006.  
  4007. vpu_combo@ff9a0000 {
  4008. compatible = "rockchip,vpu_combo";
  4009. subcnt = <0x2>;
  4010. rockchip,sub = <0xa8 0xa9>;
  4011. clocks = <0x6 0x45 0x3d>;
  4012. clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
  4013. mode_bit = <0xf>;
  4014. mode_ctrl = <0x144>;
  4015. status = "okay";
  4016. };
  4017.  
  4018. iep@10108000 {
  4019. compatible = "rockchip,iep";
  4020. iommu_enabled = <0x1>;
  4021. reg = <0x10108000 0x800>;
  4022. interrupts = <0x0 0x30 0x4>;
  4023. clocks = <0x70 0x8 0x70 0x7>;
  4024. clock-names = "aclk_iep", "hclk_iep";
  4025. status = "okay";
  4026. };
  4027.  
  4028. rga@1010c000 {
  4029. compatible = "rockchip,rk312x-rga";
  4030. reg = <0x1010c000 0x1000>;
  4031. interrupts = <0x0 0x2c 0x4>;
  4032. clocks = <0x9d 0xa 0x9d 0xb>;
  4033. clock-names = "hclk_rga", "aclk_rga";
  4034. status = "okay";
  4035. };
  4036.  
  4037. vop_mmu {
  4038. dbgname = "vop";
  4039. compatible = "rockchip,vop_mmu";
  4040. reg = <0x1010e300 0x100>;
  4041. interrupts = <0x0 0x9 0x4>;
  4042. interrupt-names = "vop_mmu";
  4043. };
  4044.  
  4045. hevc_mmu {
  4046. dbgname = "hevc";
  4047. compatible = "rockchip,hevc_mmu";
  4048. reg = <0x10104440 0x40 0x10104480 0x40>;
  4049. interrupts = <0x0 0x41 0x4>;
  4050. interrupt-names = "hevc_mmu";
  4051. };
  4052.  
  4053. vpu_mmu {
  4054. dbgname = "vpu";
  4055. compatible = "rockchip,vpu_mmu";
  4056. reg = <0x10106800 0x100>;
  4057. interrupts = <0x0 0x43 0x4>;
  4058. interrupt-names = "vpu_mmu";
  4059. };
  4060.  
  4061. iep_mmu {
  4062. dbgname = "iep";
  4063. compatible = "rockchip,iep_mmu";
  4064. reg = <0x10108800 0x100>;
  4065. interrupts = <0x0 0x30 0x4>;
  4066. interrupt-names = "iep_mmu";
  4067. };
  4068.  
  4069. dvfs {
  4070.  
  4071. vd_arm {
  4072. regulator_name = "vdd_arm";
  4073.  
  4074. pd_core {
  4075.  
  4076. clk_core {
  4077. operating-points = <0x34bc0 0x118c30 0x639c0 0x118c30 0x927c0 0x124f80 0xa9ec0 0x1312d0 0xc7380 0x13d620 0xf6180 0x149970>;
  4078. temp-limit-enable = <0x1>;
  4079. target-temp = <0x55>;
  4080. temp-channel = <0x1>;
  4081. normal-temp-limit = <0x3 0x17700 0x6 0x23280 0x9 0x2ee00 0xf 0x5dc00>;
  4082. performance-temp-limit = <0x6e 0xc7380>;
  4083. status = "okay";
  4084. regu-mode-table = <0xf6180 0x4 0x0 0x3>;
  4085. regu-mode-en = <0x0>;
  4086. lkg_adjust_volt_en = <0x1>;
  4087. channel = <0x0>;
  4088. def_table_lkg = <0x23>;
  4089. min_adjust_freq = <0x124f80>;
  4090. lkg_adjust_volt_table = <0x3c 0x61a8>;
  4091. virt-temp-limit-1-cpu-busy = <0x4b 0xf6180 0x55 0x124f80 0x5f 0x124f80 0x64 0x124f80>;
  4092. virt-temp-limit-2-cpu-busy = <0x4b 0xdea80 0x55 0xf6180 0x5f 0x10d880 0x64 0x124f80>;
  4093. virt-temp-limit-3-cpu-busy = <0x4b 0xc7380 0x55 0xdea80 0x5f 0x189c0 0x64 0x1af40>;
  4094. virt-temp-limit-4-cpu-busy = <0x4b 0xc7380 0x55 0xdea80 0x5f 0x189c0 0x64 0x1af40>;
  4095. };
  4096. };
  4097. };
  4098.  
  4099. vd_logic {
  4100. regulator_name = "vdd_logic";
  4101. status = "okay";
  4102.  
  4103. pd_ddr {
  4104.  
  4105. clk_ddr {
  4106. operating-points = <0x186a0 0x1312d0 0x30d40 0x1312d0 0x493e0 0x1312d0 0x57e40 0x1312d0>;
  4107. status = "okay";
  4108. freq-table = <0x1 0x57e40 0x2 0x186a0 0x2000 0x57e40>;
  4109. auto-freq-table = <0x3a980 0x4f1a0 0x57e40>;
  4110. auto-freq = <0x0>;
  4111. };
  4112. };
  4113.  
  4114. pd_gpu {
  4115.  
  4116. clk_gpu {
  4117. operating-points = <0x30d40 0x10c8e0 0x493e0 0x10c8e0 0x57e40 0x118c30>;
  4118. status = "okay";
  4119. regu-mode-table = <0x30d40 0x4 0x0 0x3>;
  4120. regu-mode-en = <0x0>;
  4121. };
  4122. };
  4123. };
  4124. };
  4125.  
  4126. ion {
  4127. compatible = "rockchip,ion";
  4128. #address-cells = <0x1>;
  4129. #size-cells = <0x0>;
  4130.  
  4131. rockchip,ion-heap@4 {
  4132. compatible = "rockchip,ion-heap";
  4133. rockchip,ion_heap = <0x4>;
  4134. reg = <0x0 0x800000>;
  4135. };
  4136.  
  4137. rockchip,ion-heap@0 {
  4138. compatible = "rockchip,ion-heap";
  4139. rockchip,ion_heap = <0x0>;
  4140. };
  4141. };
  4142.  
  4143. cif@1010a000 {
  4144. compatible = "rockchip,cif";
  4145. reg = <0x1010a000 0x2000>;
  4146. interrupts = <0x0 0x8 0x4>;
  4147. clocks = <0xaa 0x9d 0x5 0x9d 0x4 0xab 0x38>;
  4148. clock-names = "pd_cif0", "aclk_cif0", "hclk_cif0", "cif0_in", "cif0_out";
  4149. status = "okay";
  4150. };
  4151.  
  4152. codec-hdmi-spdif {
  4153. compatible = "hdmi-spdif";
  4154. linux,phandle = <0xac>;
  4155. phandle = <0xac>;
  4156. };
  4157.  
  4158. rockchip-hdmi-spdif {
  4159. compatible = "rockchip-hdmi-spdif";
  4160.  
  4161. dais {
  4162.  
  4163. dai0 {
  4164. audio-codec = <0xac>;
  4165. i2s-controller = <0xad>;
  4166. };
  4167. };
  4168. };
  4169.  
  4170. codec@20030000 {
  4171. compatible = "rk312x-codec";
  4172. reg = <0x20030000 0x4000>;
  4173. boot_depop = <0x1>;
  4174. pa_enable_time = <0x3e8>;
  4175. clocks = <0x4e 0xe>;
  4176. clock-names = "g_pclk_acodec";
  4177. spk_ctl_io = <0x76 0xb 0x0>;
  4178. spk-mute-delay = <0xc8>;
  4179. hp-mute-delay = <0x64>;
  4180. rk312x_for_mid = <0x1>;
  4181. is_rk3128 = <0x0>;
  4182. spk_volume = <0x1a>;
  4183. hp_volume = <0x19>;
  4184. capture_volume = <0x17>;
  4185. gpio_debug = <0x0>;
  4186. codec_hp_det = <0x0>;
  4187. linux,phandle = <0xae>;
  4188. phandle = <0xae>;
  4189. };
  4190.  
  4191. audio-rk312x {
  4192. compatible = "audio-rk312x";
  4193.  
  4194. dais {
  4195.  
  4196. dai0 {
  4197. audio-codec = <0xae>;
  4198. i2s-controller = <0xaf>;
  4199. format = "i2s";
  4200. };
  4201.  
  4202. dai1 {
  4203. audio-codec = <0xae>;
  4204. i2s-controller = <0xaf>;
  4205. format = "i2s";
  4206. };
  4207. };
  4208. };
  4209.  
  4210. rk3126_cif_sensor {
  4211. compatible = "rockchip,sensor";
  4212. status = "okay";
  4213. CONFIG_SENSOR_POWER_IOCTL_USR = <0x0>;
  4214. CONFIG_SENSOR_RESET_IOCTL_USR = <0x0>;
  4215. CONFIG_SENSOR_POWERDOWN_IOCTL_USR = <0x1>;
  4216. CONFIG_SENSOR_FLASH_IOCTL_USR = <0x0>;
  4217. CONFIG_SENSOR_AF_IOCTL_USR = <0x0>;
  4218.  
  4219. gc0329 {
  4220. is_front = <0x0>;
  4221. rockchip,powerdown = <0x76 0x9 0x0>;
  4222. pwdn_active = <0x1>;
  4223. #pwr_active = <0x1>;
  4224. mir = <0x0>;
  4225. flash_active = <0x0>;
  4226. resolution = <0x30000>;
  4227. powerup_sequence = <0x7654>;
  4228. orientation = <0x0>;
  4229. i2c_add = <0x62>;
  4230. i2c_rata = <0x186a0>;
  4231. i2c_chl = <0x1>;
  4232. cif_chl = <0x0>;
  4233. mclk_rate = <0x18>;
  4234. };
  4235.  
  4236. gc0308 {
  4237. is_front = <0x0>;
  4238. rockchip,powerdown = <0x76 0x9 0x0>;
  4239. pwdn_active = <0x1>;
  4240. #pwr_active = <0x1>;
  4241. mir = <0x0>;
  4242. flash_active = <0x0>;
  4243. resolution = <0x30000>;
  4244. powerup_sequence = <0x7654>;
  4245. orientation = <0x0>;
  4246. i2c_add = <0x42>;
  4247. i2c_rata = <0x186a0>;
  4248. i2c_chl = <0x1>;
  4249. cif_chl = <0x0>;
  4250. mclk_rate = <0x18>;
  4251. };
  4252.  
  4253. gc2035 {
  4254. is_front = <0x0>;
  4255. #rockchip,power = <0x75 0x0 0x0>;
  4256. rockchip,powerdown = <0x76 0x9 0x0>;
  4257. pwdn_active = <0x1>;
  4258. #pwr_active = <0x1>;
  4259. mir = <0x0>;
  4260. flash_active = <0x0>;
  4261. resolution = <0x200000>;
  4262. #pwdn_info = <0x1>;
  4263. powerup_sequence = <0x7654>;
  4264. orientation = <0x5a>;
  4265. i2c_add = <0x78>;
  4266. i2c_rata = <0x186a0>;
  4267. i2c_chl = <0x1>;
  4268. cif_chl = <0x0>;
  4269. mclk_rate = <0x18>;
  4270. };
  4271.  
  4272. gc2155 {
  4273. is_front = <0x0>;
  4274. #rockchip,power = <0x75 0x0 0x0>;
  4275. rockchip,powerdown = <0x76 0x9 0x0>;
  4276. pwdn_active = <0x1>;
  4277. #pwr_active = <0x1>;
  4278. mir = <0x0>;
  4279. flash_active = <0x0>;
  4280. resolution = <0x200000>;
  4281. #pwdn_info = <0x1>;
  4282. powerup_sequence = <0x7654>;
  4283. orientation = <0xb4>;
  4284. i2c_add = <0x78>;
  4285. i2c_rata = <0x186a0>;
  4286. i2c_chl = <0x1>;
  4287. cif_chl = <0x0>;
  4288. mclk_rate = <0x18>;
  4289. };
  4290.  
  4291. gc2145 {
  4292. is_front = <0x0>;
  4293. #rockchip,power = <0x75 0x0 0x0>;
  4294. rockchip,powerdown = <0x76 0x9 0x0>;
  4295. pwdn_active = <0x1>;
  4296. #pwr_active = <0x1>;
  4297. mir = <0x0>;
  4298. flash_active = <0x0>;
  4299. resolution = <0x200000>;
  4300. #pwdn_info = <0x1>;
  4301. powerup_sequence = <0x7654>;
  4302. orientation = <0x0>;
  4303. i2c_add = <0x78>;
  4304. i2c_rata = <0x186a0>;
  4305. i2c_chl = <0x1>;
  4306. cif_chl = <0x0>;
  4307. mclk_rate = <0x18>;
  4308. };
  4309.  
  4310. siv121du {
  4311. is_front = <0x0>;
  4312. rockchip,powerdown = <0x76 0x13 0x0>;
  4313. pwdn_active = <0x1>;
  4314. #pwr_active = <0x1>;
  4315. mir = <0x0>;
  4316. flash_active = <0x0>;
  4317. resolution = <0x30000>;
  4318. powerup_sequence = <0x7654>;
  4319. orientation = <0x0>;
  4320. i2c_add = <0x66>;
  4321. i2c_rata = <0x186a0>;
  4322. i2c_chl = <0x1>;
  4323. cif_chl = <0x0>;
  4324. mclk_rate = <0x18>;
  4325. };
  4326.  
  4327. gc0309_front {
  4328. is_front = <0x1>;
  4329. rockchip,powerdown = <0xb0 0xb 0x0>;
  4330. pwdn_active = <0x1>;
  4331. mir = <0x0>;
  4332. flash_active = <0x0>;
  4333. resolution = <0x30000>;
  4334. powerup_sequence = <0x7654>;
  4335. orientation = <0x0>;
  4336. i2c_add = <0x42>;
  4337. i2c_rata = <0x186a0>;
  4338. i2c_chl = <0x1>;
  4339. cif_chl = <0x0>;
  4340. mclk_rate = <0x18>;
  4341. };
  4342.  
  4343. gc0312_front {
  4344. is_front = <0x1>;
  4345. rockchip,powerdown = <0xb0 0xb 0x0>;
  4346. pwdn_active = <0x1>;
  4347. mir = <0x0>;
  4348. flash_active = <0x0>;
  4349. resolution = <0x30000>;
  4350. powerup_sequence = <0x7654>;
  4351. orientation = <0x0>;
  4352. i2c_add = <0x42>;
  4353. i2c_rata = <0x186a0>;
  4354. i2c_chl = <0x1>;
  4355. cif_chl = <0x0>;
  4356. mclk_rate = <0x18>;
  4357. };
  4358.  
  4359. gc0308_front {
  4360. is_front = <0x1>;
  4361. rockchip,powerdown = <0xb0 0xb 0x0>;
  4362. pwdn_active = <0x1>;
  4363. mir = <0x0>;
  4364. flash_active = <0x0>;
  4365. resolution = <0x30000>;
  4366. powerup_sequence = <0x7654>;
  4367. orientation = <0x0>;
  4368. i2c_add = <0x42>;
  4369. i2c_rata = <0x186a0>;
  4370. i2c_chl = <0x1>;
  4371. cif_chl = <0x0>;
  4372. mclk_rate = <0x18>;
  4373. };
  4374.  
  4375. gc0329_front {
  4376. is_front = <0x1>;
  4377. rockchip,powerdown = <0xb0 0xb 0x0>;
  4378. pwdn_active = <0x1>;
  4379. #pwr_active = <0x1>;
  4380. mir = <0x0>;
  4381. flash_active = <0x0>;
  4382. resolution = <0x30000>;
  4383. powerup_sequence = <0x7654>;
  4384. orientation = <0x10e>;
  4385. i2c_add = <0x62>;
  4386. i2c_rata = <0x186a0>;
  4387. i2c_chl = <0x1>;
  4388. cif_chl = <0x0>;
  4389. mclk_rate = <0x18>;
  4390. };
  4391.  
  4392. gc0328_front {
  4393. is_front = <0x1>;
  4394. rockchip,powerdown = <0xb0 0xb 0x0>;
  4395. pwdn_active = <0x1>;
  4396. #pwr_active = <0x1>;
  4397. mir = <0x0>;
  4398. flash_active = <0x0>;
  4399. resolution = <0x30000>;
  4400. powerup_sequence = <0x7654>;
  4401. orientation = <0x0>;
  4402. i2c_add = <0x42>;
  4403. i2c_rata = <0x186a0>;
  4404. i2c_chl = <0x1>;
  4405. cif_chl = <0x0>;
  4406. mclk_rate = <0x18>;
  4407. };
  4408.  
  4409. siv121du_front {
  4410. is_front = <0x1>;
  4411. rockchip,powerdown = <0xb0 0xb 0x0>;
  4412. pwdn_active = <0x1>;
  4413. #pwr_active = <0x1>;
  4414. mir = <0x0>;
  4415. flash_active = <0x0>;
  4416. resolution = <0x30000>;
  4417. powerup_sequence = <0x7654>;
  4418. orientation = <0x10e>;
  4419. i2c_add = <0x66>;
  4420. i2c_rata = <0x186a0>;
  4421. i2c_chl = <0x1>;
  4422. cif_chl = <0x0>;
  4423. mclk_rate = <0x18>;
  4424. };
  4425. };
  4426.  
  4427. pwm-regulator1 {
  4428. compatible = "rockchip_pwm_regulator";
  4429. pwms = <0xb1 0x0 0x61a8>;
  4430. rockchip,pwm_id = <0x1>;
  4431. rockchip,pwm_voltage_map = <0xe7ef0 0xee098 0xf4240 0xfa3e8 0x100590 0x106738 0x10c8e0 0x112a88 0x118c30 0x11edd8 0x124f80 0x12b128 0x1312d0 0x137478 0x13d620 0x1437c8 0x149970 0x14fb18 0x155cc0 0x15be68 0x162010>;
  4432. rockchip,pwm_voltage = <0x1312d0>;
  4433. rockchip,pwm_min_voltage = <0xe7ef0>;
  4434. rockchip,pwm_max_voltage = <0x162010>;
  4435. rockchip,pwm_suspend_voltage = <0x1312d0>;
  4436. rockchip,pwm_coefficient = <0x226>;
  4437. status = "okay";
  4438.  
  4439. regulators {
  4440. #address-cells = <0x1>;
  4441. #size-cells = <0x0>;
  4442.  
  4443. regulator@0 {
  4444. regulator-compatible = "pwm_dcdc1";
  4445. regulator-name = "vdd_logic";
  4446. regulator-min-microvolt = <0x124f80>;
  4447. regulator-max-microvolt = <0x162010>;
  4448. regulator-always-on;
  4449. regulator-boot-on;
  4450. };
  4451. };
  4452. };
  4453.  
  4454. pwm-regulator2 {
  4455. compatible = "rockchip_pwm_regulator";
  4456. pwms = <0xb2 0x0 0x61a8>;
  4457. rockchip,pwm_id = <0x2>;
  4458. rockchip,pwm_voltage_map = <0xe7ef0 0xee098 0xf4240 0xfa3e8 0x100590 0x106738 0x10c8e0 0x112a88 0x118c30 0x11edd8 0x124f80 0x12b128 0x1312d0 0x137478 0x13d620 0x1437c8 0x149970 0x14fb18 0x155cc0 0x15be68 0x162010>;
  4459. rockchip,pwm_voltage = <0x124f80>;
  4460. rockchip,pwm_min_voltage = <0xe7ef0>;
  4461. rockchip,pwm_max_voltage = <0x162010>;
  4462. rockchip,pwm_suspend_voltage = <0x1312d0>;
  4463. rockchip,pwm_coefficient = <0x226>;
  4464. status = "disabled";
  4465.  
  4466. regulators {
  4467. #address-cells = <0x1>;
  4468. #size-cells = <0x0>;
  4469.  
  4470. regulator@1 {
  4471. regulator-compatible = "pwm_dcdc2";
  4472. regulator-name = "vdd_logic";
  4473. regulator-min-microvolt = <0xe7ef0>;
  4474. regulator-max-microvolt = <0x162010>;
  4475. regulator-always-on;
  4476. regulator-boot-on;
  4477. };
  4478. };
  4479. };
  4480.  
  4481. display-timings {
  4482. native-mode = <0xb3>;
  4483. linux,phandle = <0x9b>;
  4484. phandle = <0x9b>;
  4485.  
  4486. timing0 {
  4487. screen-type = <0x2>;
  4488. lvds-format = <0x0>;
  4489. out-face = <0x0>;
  4490. color-mode = <0x0>;
  4491. clock-frequency = <0x3938700>;
  4492. hactive = <0x400>;
  4493. vactive = <0x258>;
  4494. hback-porch = <0x78>;
  4495. hfront-porch = <0x78>;
  4496. vback-porch = <0xa>;
  4497. vfront-porch = <0xf>;
  4498. hsync-len = <0x64>;
  4499. vsync-len = <0xa>;
  4500. hsync-active = <0x0>;
  4501. vsync-active = <0x0>;
  4502. de-active = <0x0>;
  4503. pixelclk-active = <0x0>;
  4504. swap-rb = <0x0>;
  4505. swap-rg = <0x0>;
  4506. swap-gb = <0x0>;
  4507. linux,phandle = <0xb3>;
  4508. phandle = <0xb3>;
  4509. };
  4510. };
  4511.  
  4512. backlight {
  4513. compatible = "pwm-backlight";
  4514. pwms = <0xb4 0x0 0x61a8>;
  4515. brightness-levels = <0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
  4516. default-brightness-level = <0x80>;
  4517. linux,phandle = <0x9f>;
  4518. phandle = <0x9f>;
  4519. };
  4520.  
  4521. usb_control {
  4522. compatible = "rockchip,rk3126-usb-control";
  4523. rockchip,remote_wakeup;
  4524. rockchip,usb_irq_wakeup;
  4525. };
  4526.  
  4527. wireless-wlan {
  4528. compatible = "wlan-platdata";
  4529. wifi_chip_type = "esp8089";
  4530. WIFI,wifi33_gpio = <0x77 0x1 0x1>;
  4531. WIFI,poweren_gpio = <0x77 0xb 0x1>;
  4532. WIFI,host_wake_irq = <0x77 0x0 0x8>;
  4533. status = "okay";
  4534. };
  4535.  
  4536. rockchip_suspend {
  4537. rockchip,ctrbits = <0x9482f>;
  4538. rockchip,pmic-suspend_gpios = <0x3c10>;
  4539. };
  4540. };
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