library ieee;
use ieee.std_logic_1164.all;

entity zadanie67 is
     port(ster : in bit;
			 clk : in bit
			 dane : in bit_vector(7 downto 0) -- deklaracja wejść
          led : out bit_vector(7 downto 0);
          hex : out bit_vector(7 downto 0)         -- deklaracja wyjść
     end zadanie67;

architecture behavioral of zadanie67 is
begin
kod: process(clk, ster)
		begin
		if(ster = 0)
		if(clk'event and clk="1")



		led <= dane;
		end process kod;
dek: process(clk, ster)
		begin
		if(ster = 1)
		if(clk'event and clk="1")


		led <= dane;
		end process dek;




end behavioral;