module Modulo (input logic [2:0]t,
			   input logic clk,
			   output logic [2:0]a);
reg [2:0]x = 3'd0;
reg s = 0;
assign a = x;
always_ff@(posedge clk) begin
	if (x<t) begin
		if (s<2)
			s = (s+1);
		else begin
			x = (x+1);
			s = 0;
			end
		end
	end
endmodule