shiftreg verilog

module shift (AsyncClear, Clk, SI, POut);
input  AsyncClear,Clk,SI;
output [7:0] POut;
reg [7:0] internal;

  always @(posedge Clk or posedge AsyncClear)
  begin
  if(AsyncClear)
    internal = 0;
  else
    begin
      internal = {internal[6:0], SI};
    end
  end
  assign POut = internal;
endmodule



//TESTBENCH STIMULUS
SI = 1;
AsyncClear = 1;
#100
AsyncClear = 0;

for(i=0;i<20;i=i+1)
begin
Clk = !Clk;
#100
end