ENTITY mux41n IS
	 GENERIC (n: INTEGER:=4);
	 PORT (a  : IN BIT_VECTOR (N-1 downto 0);
		b  : IN BIT_VECTOR (N-1 downto 0);
	 control1 : IN BIT_VECTOR (1 downto 0);
 	s: OUT BIT;
END mux41n;

ARCHITECTURE estructural OF mux41n IS
	COMPONENT mux21

		 PORT (e1, e2, c: IN BIT; sal: OUT BIT);

 END COMPONENT;

signal salmux1 : bit_vector(N-1 downto 0);

BEGIN


 G : for i in 0 to N-1 GENERATE
	MULt1 : mux21 port map  (a(n-i),b(n-i),control1,salmux1);
END GENERATE;

END estructural;