Sreg.sv

module Sreg(
        input logic c,
        input logic d,
        input logic clr,
        output logic [15:0] q
    );

reg [4:0] i;


always @(posedge c) begin
    if(clr)
        q = 16'd0;
    q[15] <= d;
    for (i = 14; i >= 0 ; i = i - 1) begin
        q[i] <= q[i+1];
    end
end


endmodule