module counter_T_4_bits(
    input [0:1] SW,
    input [0:0] KEY,
    output [0:6] HEX0);

    wire [3:0] counterOut;

    inner_counter_T_4_bits ex0(KEY[0],SW[0],SW[1],counterOut);
    decoder_hex_16 ex1(counterOut,HEX0);

endmodule

module decoder_hex_16(
    input [3:0] x,
    output reg [0:6] h);

    always@(*)
        case(x)
            4'b0000: h=7'b0000001;
            4'b0001: h=7'b1001111;
            4'b0010: h=7'b0010010;
            4'b0011: h=7'b0000110;
            4'b0100: h=7'b1001100;
            4'b0101: h=7'b0100100;
            4'b0110: h=7'b0100000;
            4'b0111: h=7'b0001111;
            4'b1000: h=7'b0000000;
            4'b1001: h=7'b0000100;
            4'b1010: h=~7'b1110111; //A
            4'b1011: h=~7'b0011111; //B
            4'b1100: h=~7'b1001110; //C
            4'b1101: h=~7'b0111101; //D
            4'b1110: h=~7'b1001111; //E
            4'b1111: h=~7'b1000111; //F

        endcase

endmodule

module inner_counter_T_4_bits(
    input clk, aclr, enable,
    output [3:0] q);

    wire [3:1] c;

    assign c[1] = q[0]&enable;
    assign c[2] = q[1]&c[1];
    assign c[3] = q[2]&c[2];

    FFT_areset ex0(enable,clk,aclr,q[0]);
    FFT_areset ex1(c[1],clk,aclr,q[1]);
    FFT_areset ex2(c[2],clk,aclr,q[2]);
    FFT_areset ex3(c[3],clk,aclr,q[3]);

endmodule

module FFT_areset(
    input T, clk, aclr,
    output reg Q);

    always@(posedge clk, negedge aclr)
        if(!aclr) Q<=1'b0;
        else if(T) Q<=~Q;
        else Q<=Q;

endmodule