module test(
  input wire CLK50MHZ,
  output wire [3:0]led,
  output wire h,v,r,g,b
);

wire wc0;

// clock 85.500 MHZ
pll pll_ (
    .inclk0(CLK50MHZ),
    .c0(wc0)
    );

reg [31:0]counter;

// http://gfiles.chinaaet.com/crazybingo/group/20170606/334-6363235373199427985140055.pdf
// Resolution: 1366 x 768 at 60 Hz (non-interlaced) NORMAL BLANKING
localparam [31:0] h_front_porch = 70;
localparam [31:0] h_sync = 143;
localparam [31:0] h_back_porch = 213;
localparam [31:0] h_resolution = 1366;

localparam [31:0] v_front_porch = 3;
localparam [31:0] v_sync = 3;
localparam [31:0] v_back_porch = 24;
localparam [31:0] v_resolution = 768;

// counters
reg [31:0]vertical;
reg [31:0]horizontal;

// tmp regs
reg [1:0]_v;
reg [1:0]_h;
reg [1:0]_r;
reg [1:0]_g;
reg [1:0]_b;

// on pll clock
always @(posedge wc0)
begin
    // leds for test
    counter <= counter + 1;

    // clock horizontal and vertical clock
    if (horizontal < (h_resolution + h_front_porch + h_sync + h_back_porch ) - 1)
    begin
        horizontal <= horizontal + 1;
    end
    else
    begin
        horizontal <= 0;

        if (vertical < (v_resolution + v_front_porch + v_sync + v_back_porch ) - 1)
        begin
            vertical <= vertical + 1;
        end
        else
        begin
            vertical <= 0;
        end
   end


    // do sync pulses
    // http://www.lucidscience.com/projects/VGA%20Video%20Generator/8.jpg
    if ((horizontal >= h_resolution + h_front_porch) && (horizontal < h_resolution + h_front_porch + h_sync))
    begin
        _h <= 1;
    end
    else
    begin
        _h <= 0;
   end

    if ((vertical >= v_resolution + v_front_porch) && (vertical < v_resolution + v_front_porch + v_sync))
    begin
        _v <= 1;
    end
    else
    begin
        _v <= 0;
   end

    // do rgb squares
    if ((vertical >= 0) && (vertical < 256))
    begin
        if((horizontal >= 0) && (horizontal < 456))
        begin
            _r <= 1;
            _g <= 0;
            _b <= 0;
        end
        else if((horizontal >= 456) && (horizontal < 912))
        begin
            _r <= 0;
            _g <= 1;
            _b <= 0;
        end
        else if((horizontal >= 912) && (horizontal < 1366))
        begin
            _r <= 0;
            _g <= 0;
            _b <= 1;
        end
        else
        begin
            _r <= 0;
            _g <= 0;
            _b <= 0;
        end
    end
    else if ((vertical >= 256) && (vertical < 512))
    begin
        if((horizontal >= 0) && (horizontal < 456))
        begin
            _r <= 1;
            _g <= 1;
            _b <= 0;
        end
        else if((horizontal >= 456) && (horizontal < 912))
        begin
            _r <= 0;
            _g <= 1;
            _b <= 1;
        end
        else if((horizontal >= 912) && (horizontal < 1366))
        begin
            _r <= 1;
            _g <= 0;
            _b <= 1;
        end
        else
        begin
            _r <= 0;
            _g <= 0;
            _b <= 0;
        end
    end
    else if ((vertical >= 512) && (vertical < v_resolution))
    begin
        if((horizontal >= 0) && (horizontal < 456))
        begin
            _r <= 1;
            _g <= 1;
            _b <= 1;
        end
        else if((horizontal >= 456) && (horizontal < 912))
        begin
            _r <= 0;
            _g <= 0;
            _b <= 0;
        end
        else if((horizontal >= 912) && (horizontal < 1366))
        begin
            _r <= 0;
            _g <= 0;
            _b <= 0;
        end
        else
        begin
            _r <= 0;
            _g <= 0;
            _b <= 0;
        end
    end
    else
    begin
        _r <= 0;
        _g <= 0;
        _b <= 0;
    end
end


// write clock
assign led = counter[23:20];

// write sync
assign h = _h;
assign v = _v;

// write color
assign r = _r;
assign g = _g;
assign b = _b;

endmodule