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  1. NIR (final form) for geometry shader:
  2. decl_var uniform int index (4294967295, 0)
  3. decl_var uniform vec4 expect (4294967295, 1)
  4. decl_var shader_in vec4[3] gl_Position (0, 0)
  5. decl_var shader_in flat vec4[16][3] m1 (24, 3)
  6. decl_var shader_in flat vec4[15][3] m2 (40, 51)
  7. decl_var shader_out vec4 gl_Position@0 (0, 0)
  8. decl_var shader_out vec4 color (24, 1)
  9. decl_overload main returning void
  10.  
  11. impl main {
  12. decl_reg vec1 r0
  13. decl_reg vec1 r1
  14. decl_reg vec1 r2
  15. decl_reg vec1 r3
  16. decl_reg vec1 r4
  17. decl_reg vec4 r5
  18. decl_reg vec2 r6
  19. decl_reg vec4 r7
  20. decl_reg vec4 r8
  21. decl_reg vec4 r9
  22. decl_reg vec4 r10
  23. decl_reg vec4 r11
  24. decl_reg vec3 r12
  25. decl_reg vec4 r13
  26. decl_reg vec4 r14
  27. decl_reg vec4 r15
  28. decl_reg vec4 r16
  29. decl_reg vec4 r17
  30. decl_reg vec1 r18
  31. decl_reg vec4 r19
  32. decl_reg vec3 r20
  33. decl_reg vec4 r21
  34. decl_reg vec4 r22
  35. decl_reg vec4 r23
  36. decl_reg vec4 r24
  37. decl_reg vec4 r25
  38. decl_reg vec4 r26
  39. decl_reg vec3 r27
  40. decl_reg vec4 r28
  41. decl_reg vec4 r29
  42. decl_reg vec4 r30
  43. decl_reg vec4 r31
  44. decl_reg vec4 r32
  45. decl_reg vec1 r33
  46. decl_reg vec1 r34
  47. decl_reg vec4 r35
  48. decl_reg vec3 r36
  49. decl_reg vec4 r37
  50. decl_reg vec4 r38
  51. decl_reg vec4 r39
  52. decl_reg vec4 r40
  53. decl_reg vec4 r41
  54. decl_reg vec4 r42
  55. decl_reg vec3 r43
  56. decl_reg vec4 r44
  57. decl_reg vec4 r45
  58. decl_reg vec4 r46
  59. decl_reg vec4 r47
  60. decl_reg vec4 r48
  61. decl_reg vec1 r49
  62. decl_reg vec4 r50
  63. decl_reg vec3 r51
  64. decl_reg vec4 r52
  65. decl_reg vec4 r53
  66. decl_reg vec4 r54
  67. decl_reg vec4 r55
  68. decl_reg vec4 r56
  69. decl_reg vec4 r57
  70. decl_reg vec3 r58
  71. decl_reg vec4 r59
  72. decl_reg vec4 r60
  73. decl_reg vec4 r61
  74. decl_reg vec4 r62
  75. decl_reg vec4 r63
  76. decl_reg vec4 r64
  77. decl_reg vec1 r65
  78. decl_reg vec4 r66
  79. decl_reg vec4 r67
  80. decl_reg vec1 r68
  81. decl_reg vec1 r69
  82. decl_reg vec1 r70
  83. decl_reg vec4 r71
  84. decl_reg vec2 r72
  85. decl_reg vec4 r73
  86. decl_reg vec4 r74
  87. decl_reg vec4 r75
  88. decl_reg vec4 r76
  89. decl_reg vec4 r77
  90. decl_reg vec3 r78
  91. decl_reg vec4 r79
  92. decl_reg vec4 r80
  93. decl_reg vec4 r81
  94. decl_reg vec4 r82
  95. decl_reg vec4 r83
  96. decl_reg vec1 r84
  97. decl_reg vec4 r85
  98. decl_reg vec3 r86
  99. decl_reg vec4 r87
  100. decl_reg vec4 r88
  101. decl_reg vec4 r89
  102. decl_reg vec4 r90
  103. decl_reg vec4 r91
  104. decl_reg vec4 r92
  105. decl_reg vec3 r93
  106. decl_reg vec4 r94
  107. decl_reg vec4 r95
  108. decl_reg vec4 r96
  109. decl_reg vec4 r97
  110. decl_reg vec4 r98
  111. decl_reg vec1 r99
  112. decl_reg vec1 r100
  113. decl_reg vec4 r101
  114. decl_reg vec3 r102
  115. decl_reg vec4 r103
  116. decl_reg vec4 r104
  117. decl_reg vec4 r105
  118. decl_reg vec4 r106
  119. decl_reg vec4 r107
  120. decl_reg vec4 r108
  121. decl_reg vec3 r109
  122. decl_reg vec4 r110
  123. decl_reg vec4 r111
  124. decl_reg vec4 r112
  125. decl_reg vec4 r113
  126. decl_reg vec4 r114
  127. decl_reg vec1 r115
  128. decl_reg vec4 r116
  129. decl_reg vec3 r117
  130. decl_reg vec4 r118
  131. decl_reg vec4 r119
  132. decl_reg vec4 r120
  133. decl_reg vec4 r121
  134. decl_reg vec4 r122
  135. decl_reg vec4 r123
  136. decl_reg vec3 r124
  137. decl_reg vec4 r125
  138. decl_reg vec4 r126
  139. decl_reg vec4 r127
  140. decl_reg vec4 r128
  141. decl_reg vec4 r129
  142. decl_reg vec1 r130
  143. decl_reg vec4 r131
  144. decl_reg vec4 r132
  145. decl_reg vec1 r133
  146. decl_reg vec1 r134
  147. decl_reg vec1 r135
  148. decl_reg vec4 r136
  149. decl_reg vec2 r137
  150. decl_reg vec4 r138
  151. decl_reg vec4 r139
  152. decl_reg vec4 r140
  153. decl_reg vec4 r141
  154. decl_reg vec4 r142
  155. decl_reg vec3 r143
  156. decl_reg vec4 r144
  157. decl_reg vec4 r145
  158. decl_reg vec4 r146
  159. decl_reg vec4 r147
  160. decl_reg vec4 r148
  161. decl_reg vec1 r149
  162. decl_reg vec4 r150
  163. decl_reg vec3 r151
  164. decl_reg vec4 r152
  165. decl_reg vec4 r153
  166. decl_reg vec4 r154
  167. decl_reg vec4 r155
  168. decl_reg vec4 r156
  169. decl_reg vec4 r157
  170. decl_reg vec3 r158
  171. decl_reg vec4 r159
  172. decl_reg vec4 r160
  173. decl_reg vec4 r161
  174. decl_reg vec4 r162
  175. decl_reg vec4 r163
  176. decl_reg vec1 r164
  177. decl_reg vec1 r165
  178. decl_reg vec4 r166
  179. decl_reg vec3 r167
  180. decl_reg vec4 r168
  181. decl_reg vec4 r169
  182. decl_reg vec4 r170
  183. decl_reg vec4 r171
  184. decl_reg vec4 r172
  185. decl_reg vec4 r173
  186. decl_reg vec3 r174
  187. decl_reg vec4 r175
  188. decl_reg vec4 r176
  189. decl_reg vec4 r177
  190. decl_reg vec4 r178
  191. decl_reg vec4 r179
  192. decl_reg vec1 r180
  193. decl_reg vec4 r181
  194. decl_reg vec3 r182
  195. decl_reg vec4 r183
  196. decl_reg vec4 r184
  197. decl_reg vec4 r185
  198. decl_reg vec4 r186
  199. decl_reg vec4 r187
  200. decl_reg vec4 r188
  201. decl_reg vec3 r189
  202. decl_reg vec4 r190
  203. decl_reg vec4 r191
  204. decl_reg vec4 r192
  205. decl_reg vec4 r193
  206. decl_reg vec4 r194
  207. decl_reg vec1 r195
  208. decl_reg vec4 r196
  209. decl_reg vec4 r197
  210. block block_0:
  211. /* preds: */
  212. vec4 ssa_0 = load_const (0x3f800000 /* 1.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */)
  213. vec4 ssa_1 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */)
  214. vec3 ssa_2 = load_const (0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */)
  215. vec3 ssa_3 = load_const (0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */)
  216. vec1 ssa_4 = load_const (0x0000000c /* 0.000000 */)
  217. vec3 ssa_5 = load_const (0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */)
  218. vec3 ssa_6 = load_const (0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */)
  219. vec1 ssa_7 = load_const (0x00000004 /* 0.000000 */)
  220. vec1 ssa_8 = load_const (0x00000008 /* 0.000000 */)
  221. vec3 ssa_9 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */)
  222. vec3 ssa_10 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */)
  223. vec1 ssa_11 = load_const (0x0000000b /* 0.000000 */)
  224. vec3 ssa_12 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */)
  225. vec2 ssa_13 = load_const (0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */)
  226. vec1 ssa_14 = load_const (0x00000003 /* 0.000000 */)
  227. vec1 ssa_15 = load_const (0x00000007 /* 0.000000 */)
  228. vec1 ssa_16 = load_const (0xfffffff0 /* -nan */)
  229. vec1 ssa_17 = load_const (0x00000010 /* 0.000000 */)
  230. r0 = intrinsic load_uniform () () (0)
  231. r1 = ige r0, ssa_17
  232. /* succs: block_1 block_11 */
  233. if r1 {
  234. block block_1:
  235. /* preds: block_0 */
  236. r2 = iadd r0, ssa_16
  237. r3 = ilt r2, ssa_15
  238. /* succs: block_2 block_6 */
  239. if r3 {
  240. block block_2:
  241. /* preds: block_1 */
  242. r4 = ilt r2, ssa_14
  243. /* succs: block_3 block_4 */
  244. if r4 {
  245. block block_3:
  246. /* preds: block_2 */
  247. r5 = intrinsic load_input () () (51)
  248. r6 = ieq r2.xx, ssa_13
  249. r7 = intrinsic load_input () () (52)
  250. r8 = bcsel r6.xxxx, r7, r5
  251. r9 = intrinsic load_input () () (53)
  252. r10 = bcsel r6.yyyy, r9, r8
  253. /* succs: block_5 */
  254. } else {
  255. block block_4:
  256. /* preds: block_2 */
  257. r11 = intrinsic load_input () () (54)
  258. r12 = ieq r2.xxx, ssa_12
  259. r13 = intrinsic load_input () () (55)
  260. r14 = bcsel r12.xxxx, r13, r11
  261. r15 = intrinsic load_input () () (56)
  262. r16 = bcsel r12.yyyy, r15, r14
  263. r17 = intrinsic load_input () () (57)
  264. r10 = bcsel r12.zzzz, r17, r16
  265. /* succs: block_5 */
  266. }
  267. block block_5:
  268. /* preds: block_3 block_4 */
  269. /* succs: block_10 */
  270. } else {
  271. block block_6:
  272. /* preds: block_1 */
  273. r18 = ilt r2, ssa_11
  274. /* succs: block_7 block_8 */
  275. if r18 {
  276. block block_7:
  277. /* preds: block_6 */
  278. r19 = intrinsic load_input () () (58)
  279. r20 = ieq r2.xxx, ssa_10
  280. r21 = intrinsic load_input () () (59)
  281. r22 = bcsel r20.xxxx, r21, r19
  282. r23 = intrinsic load_input () () (60)
  283. r24 = bcsel r20.yyyy, r23, r22
  284. r25 = intrinsic load_input () () (61)
  285. r10 = bcsel r20.zzzz, r25, r24
  286. /* succs: block_9 */
  287. } else {
  288. block block_8:
  289. /* preds: block_6 */
  290. r26 = intrinsic load_input () () (62)
  291. r27 = ieq r2.xxx, ssa_9
  292. r28 = intrinsic load_input () () (63)
  293. r29 = bcsel r27.xxxx, r28, r26
  294. r30 = intrinsic load_input () () (64)
  295. r31 = bcsel r27.yyyy, r30, r29
  296. r32 = intrinsic load_input () () (65)
  297. r10 = bcsel r27.zzzz, r32, r31
  298. /* succs: block_9 */
  299. }
  300. block block_9:
  301. /* preds: block_7 block_8 */
  302. /* succs: block_10 */
  303. }
  304. block block_10:
  305. /* preds: block_5 block_9 */
  306. /* succs: block_21 */
  307. } else {
  308. block block_11:
  309. /* preds: block_0 */
  310. r33 = ilt r0, ssa_8
  311. /* succs: block_12 block_16 */
  312. if r33 {
  313. block block_12:
  314. /* preds: block_11 */
  315. r34 = ilt r0, ssa_7
  316. /* succs: block_13 block_14 */
  317. if r34 {
  318. block block_13:
  319. /* preds: block_12 */
  320. r35 = intrinsic load_input () () (3)
  321. r36 = ieq r0.xxx, ssa_6
  322. r37 = intrinsic load_input () () (4)
  323. r38 = bcsel r36.xxxx, r37, r35
  324. r39 = intrinsic load_input () () (5)
  325. r40 = bcsel r36.yyyy, r39, r38
  326. r41 = intrinsic load_input () () (6)
  327. r10 = bcsel r36.zzzz, r41, r40
  328. /* succs: block_15 */
  329. } else {
  330. block block_14:
  331. /* preds: block_12 */
  332. r42 = intrinsic load_input () () (7)
  333. r43 = ieq r0.xxx, ssa_5
  334. r44 = intrinsic load_input () () (8)
  335. r45 = bcsel r43.xxxx, r44, r42
  336. r46 = intrinsic load_input () () (9)
  337. r47 = bcsel r43.yyyy, r46, r45
  338. r48 = intrinsic load_input () () (10)
  339. r10 = bcsel r43.zzzz, r48, r47
  340. /* succs: block_15 */
  341. }
  342. block block_15:
  343. /* preds: block_13 block_14 */
  344. /* succs: block_20 */
  345. } else {
  346. block block_16:
  347. /* preds: block_11 */
  348. r49 = ilt r0, ssa_4
  349. /* succs: block_17 block_18 */
  350. if r49 {
  351. block block_17:
  352. /* preds: block_16 */
  353. r50 = intrinsic load_input () () (11)
  354. r51 = ieq r0.xxx, ssa_3
  355. r52 = intrinsic load_input () () (12)
  356. r53 = bcsel r51.xxxx, r52, r50
  357. r54 = intrinsic load_input () () (13)
  358. r55 = bcsel r51.yyyy, r54, r53
  359. r56 = intrinsic load_input () () (14)
  360. r10 = bcsel r51.zzzz, r56, r55
  361. /* succs: block_19 */
  362. } else {
  363. block block_18:
  364. /* preds: block_16 */
  365. r57 = intrinsic load_input () () (15)
  366. r58 = ieq r0.xxx, ssa_2
  367. r59 = intrinsic load_input () () (16)
  368. r60 = bcsel r58.xxxx, r59, r57
  369. r61 = intrinsic load_input () () (17)
  370. r62 = bcsel r58.yyyy, r61, r60
  371. r63 = intrinsic load_input () () (18)
  372. r10 = bcsel r58.zzzz, r63, r62
  373. /* succs: block_19 */
  374. }
  375. block block_19:
  376. /* preds: block_17 block_18 */
  377. /* succs: block_20 */
  378. }
  379. block block_20:
  380. /* preds: block_15 block_19 */
  381. /* succs: block_21 */
  382. }
  383. block block_21:
  384. /* preds: block_10 block_20 */
  385. r64 = intrinsic load_uniform () () (1)
  386. r65 = ball_fequal4 r10, r64
  387. r66 = bcsel r65.xxxx, ssa_1, ssa_0
  388. r67 = intrinsic load_input () () (0)
  389. intrinsic store_output (r66) () (1)
  390. intrinsic store_output (r67) () (0)
  391. intrinsic emit_vertex () () (0)
  392. /* succs: block_22 block_32 */
  393. if r1 {
  394. block block_22:
  395. /* preds: block_21 */
  396. r68 = iadd r0, ssa_16
  397. r69 = ilt r68, ssa_15
  398. /* succs: block_23 block_27 */
  399. if r69 {
  400. block block_23:
  401. /* preds: block_22 */
  402. r70 = ilt r68, ssa_14
  403. /* succs: block_24 block_25 */
  404. if r70 {
  405. block block_24:
  406. /* preds: block_23 */
  407. r71 = intrinsic load_input () () (66)
  408. r72 = ieq r68.xx, ssa_13
  409. r73 = intrinsic load_input () () (67)
  410. r74 = bcsel r72.xxxx, r73, r71
  411. r75 = intrinsic load_input () () (68)
  412. r76 = bcsel r72.yyyy, r75, r74
  413. /* succs: block_26 */
  414. } else {
  415. block block_25:
  416. /* preds: block_23 */
  417. r77 = intrinsic load_input () () (69)
  418. r78 = ieq r68.xxx, ssa_12
  419. r79 = intrinsic load_input () () (70)
  420. r80 = bcsel r78.xxxx, r79, r77
  421. r81 = intrinsic load_input () () (71)
  422. r82 = bcsel r78.yyyy, r81, r80
  423. r83 = intrinsic load_input () () (72)
  424. r76 = bcsel r78.zzzz, r83, r82
  425. /* succs: block_26 */
  426. }
  427. block block_26:
  428. /* preds: block_24 block_25 */
  429. /* succs: block_31 */
  430. } else {
  431. block block_27:
  432. /* preds: block_22 */
  433. r84 = ilt r68, ssa_11
  434. /* succs: block_28 block_29 */
  435. if r84 {
  436. block block_28:
  437. /* preds: block_27 */
  438. r85 = intrinsic load_input () () (73)
  439. r86 = ieq r68.xxx, ssa_10
  440. r87 = intrinsic load_input () () (74)
  441. r88 = bcsel r86.xxxx, r87, r85
  442. r89 = intrinsic load_input () () (75)
  443. r90 = bcsel r86.yyyy, r89, r88
  444. r91 = intrinsic load_input () () (76)
  445. r76 = bcsel r86.zzzz, r91, r90
  446. /* succs: block_30 */
  447. } else {
  448. block block_29:
  449. /* preds: block_27 */
  450. r92 = intrinsic load_input () () (77)
  451. r93 = ieq r68.xxx, ssa_9
  452. r94 = intrinsic load_input () () (78)
  453. r95 = bcsel r93.xxxx, r94, r92
  454. r96 = intrinsic load_input () () (79)
  455. r97 = bcsel r93.yyyy, r96, r95
  456. r98 = intrinsic load_input () () (80)
  457. r76 = bcsel r93.zzzz, r98, r97
  458. /* succs: block_30 */
  459. }
  460. block block_30:
  461. /* preds: block_28 block_29 */
  462. /* succs: block_31 */
  463. }
  464. block block_31:
  465. /* preds: block_26 block_30 */
  466. /* succs: block_42 */
  467. } else {
  468. block block_32:
  469. /* preds: block_21 */
  470. r99 = ilt r0, ssa_8
  471. /* succs: block_33 block_37 */
  472. if r99 {
  473. block block_33:
  474. /* preds: block_32 */
  475. r100 = ilt r0, ssa_7
  476. /* succs: block_34 block_35 */
  477. if r100 {
  478. block block_34:
  479. /* preds: block_33 */
  480. r101 = intrinsic load_input () () (19)
  481. r102 = ieq r0.xxx, ssa_6
  482. r103 = intrinsic load_input () () (20)
  483. r104 = bcsel r102.xxxx, r103, r101
  484. r105 = intrinsic load_input () () (21)
  485. r106 = bcsel r102.yyyy, r105, r104
  486. r107 = intrinsic load_input () () (22)
  487. r76 = bcsel r102.zzzz, r107, r106
  488. /* succs: block_36 */
  489. } else {
  490. block block_35:
  491. /* preds: block_33 */
  492. r108 = intrinsic load_input () () (23)
  493. r109 = ieq r0.xxx, ssa_5
  494. r110 = intrinsic load_input () () (24)
  495. r111 = bcsel r109.xxxx, r110, r108
  496. r112 = intrinsic load_input () () (25)
  497. r113 = bcsel r109.yyyy, r112, r111
  498. r114 = intrinsic load_input () () (26)
  499. r76 = bcsel r109.zzzz, r114, r113
  500. /* succs: block_36 */
  501. }
  502. block block_36:
  503. /* preds: block_34 block_35 */
  504. /* succs: block_41 */
  505. } else {
  506. block block_37:
  507. /* preds: block_32 */
  508. r115 = ilt r0, ssa_4
  509. /* succs: block_38 block_39 */
  510. if r115 {
  511. block block_38:
  512. /* preds: block_37 */
  513. r116 = intrinsic load_input () () (27)
  514. r117 = ieq r0.xxx, ssa_3
  515. r118 = intrinsic load_input () () (28)
  516. r119 = bcsel r117.xxxx, r118, r116
  517. r120 = intrinsic load_input () () (29)
  518. r121 = bcsel r117.yyyy, r120, r119
  519. r122 = intrinsic load_input () () (30)
  520. r76 = bcsel r117.zzzz, r122, r121
  521. /* succs: block_40 */
  522. } else {
  523. block block_39:
  524. /* preds: block_37 */
  525. r123 = intrinsic load_input () () (31)
  526. r124 = ieq r0.xxx, ssa_2
  527. r125 = intrinsic load_input () () (32)
  528. r126 = bcsel r124.xxxx, r125, r123
  529. r127 = intrinsic load_input () () (33)
  530. r128 = bcsel r124.yyyy, r127, r126
  531. r129 = intrinsic load_input () () (34)
  532. r76 = bcsel r124.zzzz, r129, r128
  533. /* succs: block_40 */
  534. }
  535. block block_40:
  536. /* preds: block_38 block_39 */
  537. /* succs: block_41 */
  538. }
  539. block block_41:
  540. /* preds: block_36 block_40 */
  541. /* succs: block_42 */
  542. }
  543. block block_42:
  544. /* preds: block_31 block_41 */
  545. r130 = ball_fequal4 r76, r64
  546. r131 = bcsel r130.xxxx, ssa_1, ssa_0
  547. r132 = intrinsic load_input () () (1)
  548. intrinsic store_output (r131) () (1)
  549. intrinsic store_output (r132) () (0)
  550. intrinsic emit_vertex () () (0)
  551. /* succs: block_43 block_53 */
  552. if r1 {
  553. block block_43:
  554. /* preds: block_42 */
  555. r133 = iadd r0, ssa_16
  556. r134 = ilt r133, ssa_15
  557. /* succs: block_44 block_48 */
  558. if r134 {
  559. block block_44:
  560. /* preds: block_43 */
  561. r135 = ilt r133, ssa_14
  562. /* succs: block_45 block_46 */
  563. if r135 {
  564. block block_45:
  565. /* preds: block_44 */
  566. r136 = intrinsic load_input () () (81)
  567. r137 = ieq r133.xx, ssa_13
  568. r138 = intrinsic load_input () () (82)
  569. r139 = bcsel r137.xxxx, r138, r136
  570. r140 = intrinsic load_input () () (83)
  571. r141 = bcsel r137.yyyy, r140, r139
  572. /* succs: block_47 */
  573. } else {
  574. block block_46:
  575. /* preds: block_44 */
  576. r142 = intrinsic load_input () () (84)
  577. r143 = ieq r133.xxx, ssa_12
  578. r144 = intrinsic load_input () () (85)
  579. r145 = bcsel r143.xxxx, r144, r142
  580. r146 = intrinsic load_input () () (86)
  581. r147 = bcsel r143.yyyy, r146, r145
  582. r148 = intrinsic load_input () () (87)
  583. r141 = bcsel r143.zzzz, r148, r147
  584. /* succs: block_47 */
  585. }
  586. block block_47:
  587. /* preds: block_45 block_46 */
  588. /* succs: block_52 */
  589. } else {
  590. block block_48:
  591. /* preds: block_43 */
  592. r149 = ilt r133, ssa_11
  593. /* succs: block_49 block_50 */
  594. if r149 {
  595. block block_49:
  596. /* preds: block_48 */
  597. r150 = intrinsic load_input () () (88)
  598. r151 = ieq r133.xxx, ssa_10
  599. r152 = intrinsic load_input () () (89)
  600. r153 = bcsel r151.xxxx, r152, r150
  601. r154 = intrinsic load_input () () (90)
  602. r155 = bcsel r151.yyyy, r154, r153
  603. r156 = intrinsic load_input () () (91)
  604. r141 = bcsel r151.zzzz, r156, r155
  605. /* succs: block_51 */
  606. } else {
  607. block block_50:
  608. /* preds: block_48 */
  609. r157 = intrinsic load_input () () (92)
  610. r158 = ieq r133.xxx, ssa_9
  611. r159 = intrinsic load_input () () (93)
  612. r160 = bcsel r158.xxxx, r159, r157
  613. r161 = intrinsic load_input () () (94)
  614. r162 = bcsel r158.yyyy, r161, r160
  615. r163 = intrinsic load_input () () (95)
  616. r141 = bcsel r158.zzzz, r163, r162
  617. /* succs: block_51 */
  618. }
  619. block block_51:
  620. /* preds: block_49 block_50 */
  621. /* succs: block_52 */
  622. }
  623. block block_52:
  624. /* preds: block_47 block_51 */
  625. /* succs: block_63 */
  626. } else {
  627. block block_53:
  628. /* preds: block_42 */
  629. r164 = ilt r0, ssa_8
  630. /* succs: block_54 block_58 */
  631. if r164 {
  632. block block_54:
  633. /* preds: block_53 */
  634. r165 = ilt r0, ssa_7
  635. /* succs: block_55 block_56 */
  636. if r165 {
  637. block block_55:
  638. /* preds: block_54 */
  639. r166 = intrinsic load_input () () (35)
  640. r167 = ieq r0.xxx, ssa_6
  641. r168 = intrinsic load_input () () (36)
  642. r169 = bcsel r167.xxxx, r168, r166
  643. r170 = intrinsic load_input () () (37)
  644. r171 = bcsel r167.yyyy, r170, r169
  645. r172 = intrinsic load_input () () (38)
  646. r141 = bcsel r167.zzzz, r172, r171
  647. /* succs: block_57 */
  648. } else {
  649. block block_56:
  650. /* preds: block_54 */
  651. r173 = intrinsic load_input () () (39)
  652. r174 = ieq r0.xxx, ssa_5
  653. r175 = intrinsic load_input () () (40)
  654. r176 = bcsel r174.xxxx, r175, r173
  655. r177 = intrinsic load_input () () (41)
  656. r178 = bcsel r174.yyyy, r177, r176
  657. r179 = intrinsic load_input () () (42)
  658. r141 = bcsel r174.zzzz, r179, r178
  659. /* succs: block_57 */
  660. }
  661. block block_57:
  662. /* preds: block_55 block_56 */
  663. /* succs: block_62 */
  664. } else {
  665. block block_58:
  666. /* preds: block_53 */
  667. r180 = ilt r0, ssa_4
  668. /* succs: block_59 block_60 */
  669. if r180 {
  670. block block_59:
  671. /* preds: block_58 */
  672. r181 = intrinsic load_input () () (43)
  673. r182 = ieq r0.xxx, ssa_3
  674. r183 = intrinsic load_input () () (44)
  675. r184 = bcsel r182.xxxx, r183, r181
  676. r185 = intrinsic load_input () () (45)
  677. r186 = bcsel r182.yyyy, r185, r184
  678. r187 = intrinsic load_input () () (46)
  679. r141 = bcsel r182.zzzz, r187, r186
  680. /* succs: block_61 */
  681. } else {
  682. block block_60:
  683. /* preds: block_58 */
  684. r188 = intrinsic load_input () () (47)
  685. r189 = ieq r0.xxx, ssa_2
  686. r190 = intrinsic load_input () () (48)
  687. r191 = bcsel r189.xxxx, r190, r188
  688. r192 = intrinsic load_input () () (49)
  689. r193 = bcsel r189.yyyy, r192, r191
  690. r194 = intrinsic load_input () () (50)
  691. r141 = bcsel r189.zzzz, r194, r193
  692. /* succs: block_61 */
  693. }
  694. block block_61:
  695. /* preds: block_59 block_60 */
  696. /* succs: block_62 */
  697. }
  698. block block_62:
  699. /* preds: block_57 block_61 */
  700. /* succs: block_63 */
  701. }
  702. block block_63:
  703. /* preds: block_52 block_62 */
  704. r195 = ball_fequal4 r141, r64
  705. r196 = bcsel r195.xxxx, ssa_1, ssa_0
  706. r197 = intrinsic load_input () () (2)
  707. intrinsic store_output (r196) () (1)
  708. intrinsic store_output (r197) () (0)
  709. intrinsic emit_vertex () () (0)
  710. /* succs: block_64 */
  711. block block_64:
  712. }
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