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  1. diff --git a/libgloss/arm/Makefile.in b/libgloss/arm/Makefile.in
  2. index e1bad17..c70d760 100644
  3. --- a/libgloss/arm/Makefile.in
  4. +++ b/libgloss/arm/Makefile.in
  5. @@ -109,7 +109,7 @@ INCLUDES += `if [ -d ${objroot}/newlib ]; then echo -I$(srcroot)/newlib/libc/mac
  6. # build a test program for each target board. Just trying to get
  7. # it to link is a good test, so we ignore all the errors for now.
  8. #
  9. -all: ${CRT0} ${LINUX_CRT0} ${LINUX_BSP} ${REDBOOT_CRT0} ${REDBOOT_OBJS} ${RDPMON_CRT0} ${RDPMON_BSP} ${RDIMON_CRT0} ${RDIMON_BSP}
  10. +all: ${CRT0} # ${LINUX_CRT0} ${LINUX_BSP} ${REDBOOT_CRT0} ${REDBOOT_OBJS} ${RDPMON_CRT0} ${RDPMON_BSP} ${RDIMON_CRT0} ${RDIMON_BSP}
  11. @rootpre=`pwd`/; export rootpre; \
  12. srcrootpre=`cd $(srcdir); pwd`/; export srcrootpre; \
  13. for dir in .. ${SUBDIRS}; do \
  14. @@ -206,7 +206,7 @@ distclean maintainer-clean realclean: clean
  15. rm -f Makefile config.status *~
  16.  
  17. .PHONY: install info install-info clean-info
  18. -install: ${CRT0_INSTALL} ${LINUX_INSTALL} ${REDBOOT_INSTALL} ${RDPMON_INSTALL} ${RDIMON_INSTALL} ${IQ80310_INSTALL} ${PID_INSTALL} ${NANO_INSTALL}
  19. +install: ${CRT0_INSTALL} ${NANO_INSTALL} # ${LINUX_INSTALL} ${REDBOOT_INSTALL} ${RDPMON_INSTALL} ${RDIMON_INSTALL} ${IQ80310_INSTALL} ${PID_INSTALL} ${NANO_INSTALL}
  20. @rootpre=`pwd`/; export rootpre; \
  21. srcrootpre=`cd $(srcdir); pwd`/; export srcrootpre; \
  22. for dir in .. ${SUBDIRS}; do \
  23. diff --git a/libgloss/arm/cpu-init/Makefile.in b/libgloss/arm/cpu-init/Makefile.in
  24. deleted file mode 100644
  25. index 547c58d..0000000
  26. --- a/libgloss/arm/cpu-init/Makefile.in
  27. +++ /dev/null
  28. @@ -1,87 +0,0 @@
  29. -#
  30. -#
  31. -DESTDIR =
  32. -VPATH = @srcdir@ @srcdir@/.. @srcdir@/../..
  33. -srcdir = @srcdir@
  34. -objdir = .
  35. -srcroot = $(srcdir)/../../..
  36. -objroot = $(objdir)/../../..
  37. -
  38. -prefix = @prefix@
  39. -exec_prefix = @exec_prefix@
  40. -
  41. -host_alias = @host_alias@
  42. -target_alias = @target_alias@
  43. -
  44. -bindir = @bindir@
  45. -libdir = @libdir@
  46. -tooldir = $(exec_prefix)/$(target_alias)
  47. -
  48. -objtype = @objtype@
  49. -
  50. -INSTALL = @INSTALL@
  51. -INSTALL_PROGRAM = @INSTALL_PROGRAM@
  52. -INSTALL_DATA = @INSTALL_DATA@
  53. -
  54. -# Multilib support variables.
  55. -# TOP is used instead of MULTI{BUILD,SRC}TOP.
  56. -MULTISRCTOP =
  57. -MULTIBUILDTOP =
  58. -MULTIDIRS =
  59. -MULTISUBDIR =
  60. -MULTIDO = true
  61. -MULTICLEAN = true
  62. -
  63. -SHELL = /bin/sh
  64. -
  65. -CC = @CC@
  66. -
  67. -AS = @AS@
  68. -AR = @AR@
  69. -LD = @LD@
  70. -RANLIB = @RANLIB@
  71. -
  72. -CPU_INIT_OBJS = rdimon-aem.o
  73. -CPU_INIT_INSTALL = install-cpu-init
  74. -
  75. -CFLAGS = -g
  76. -
  77. -# Host specific makefile fragment comes in here.
  78. -@host_makefile_frag@
  79. -
  80. -.PHONY: all
  81. -all: ${CPU_INIT_OBJS}
  82. -
  83. -#
  84. -# here's where we build the test programs for each target
  85. -#
  86. -.PHONY: test
  87. -test:
  88. -
  89. -# Static pattern rule for assembling cpu init files to object files.
  90. -${CPU_INIT_OBJS}: %.o: %.S
  91. - $(CC) $(CFLAGS_FOR_TARGET) $(CFLAGS) $(INCLUDES) -DARM_RDI_MONITOR -o $@ -c $<
  92. -
  93. -clean mostlyclean:
  94. - rm -f a.out core *.i *.o *-test *.srec *.dis *.x
  95. -
  96. -distclean maintainer-clean realclean: clean
  97. - rm -f Makefile *~
  98. -
  99. -.PHONY: install info install-info clean-info
  100. -install: ${CPU_INIT_INSTALL}
  101. -
  102. -install-cpu-init:
  103. - test -d $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/cpu-init || mkdir $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/cpu-init
  104. - set -e; for x in ${CPU_INIT_OBJS}; do ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/cpu-init/$$x; done
  105. -
  106. -doc:
  107. -info:
  108. -install-info:
  109. -clean-info:
  110. -
  111. -Makefile: Makefile.in ../config.status @host_makefile_frag_path@
  112. - $(SHELL) ../config.status --file cpu-init/Makefile
  113. -
  114. -../config.status: ../configure
  115. - $(SHELL) ../config.status --recheck
  116. diff --git a/libgloss/arm/cpu-init/rdimon-aem.S b/libgloss/arm/cpu-init/rdimon-aem.S
  117. deleted file mode 100644
  118. index 95b86e4..0000000
  119. --- a/libgloss/arm/cpu-init/rdimon-aem.S
  120. +++ /dev/null
  121. @@ -1,539 +0,0 @@
  122. -/* Copyright (c) 2005-2013 ARM Ltd. All rights reserved.
  123. -
  124. - Redistribution and use in source and binary forms, with or without
  125. - modification, are permitted provided that the following conditions
  126. - are met:
  127. - 1. Redistributions of source code must retain the above copyright
  128. - notice, this list of conditions and the following disclaimer.
  129. - 2. Redistributions in binary form must reproduce the above copyright
  130. - notice, this list of conditions and the following disclaimer in the
  131. - documentation and/or other materials provided with the distribution.
  132. - 3. The name of the company may not be used to endorse or promote
  133. - products derived from this software without specific prior written
  134. - permission.
  135. -
  136. - THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
  137. - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  138. - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  139. - IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  140. - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  141. - TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  142. - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  143. - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  144. - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  145. - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
  146. -
  147. -/* This file gives a basic initialisation of a Cortex-A series core. It is
  148. - the bare minimum required to get Cortex-A core running with a semihosting
  149. - interface.
  150. -
  151. - It sets up a basic 1:1 phsyical address to virtual address mapping;
  152. - turns the MMU on; enables branch prediction; activates any integrated
  153. - caches; enables the Advanced SIMD and VFP co-processors; and installs
  154. - basic exception handlers.
  155. -
  156. - It does not handle peripherals, and assumes all memory is Normal.
  157. -
  158. - It does not change processor state from the startup privilege and security
  159. - level.
  160. -
  161. - This has only been tested to work in ARM state.
  162. -
  163. - By default it assumes exception vectors are located from address 0.
  164. - However, if this is not true they can be moved by defining the
  165. - _rdimon_vector_base symbol. For example if you have HIVECS enabled you
  166. - may pass --defsym _rdimon_vector_base=0xffff0000 on the linker command
  167. - line. */
  168. -
  169. - /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A
  170. - has been defined since 4.2 onwards, which is when v7-a support was added
  171. - and hence 'A' profile support was added in the compiler. Allow for this
  172. - file to be built with older compilers. */
  173. -#if defined(__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A')
  174. - .syntax unified
  175. - .arch armv7-a
  176. - .arm
  177. -
  178. - @ CPU Initialisation
  179. - .globl _rdimon_hw_init_hook
  180. - .type _rdimon_hw_init_hook, %function
  181. -
  182. -_rdimon_hw_init_hook:
  183. - @ Only run the code on CPU 0 - otherwise spin
  184. - mrc 15, 0, r4, cr0, cr0, 5 @ Read MPIDR
  185. - ands r4, r4, #15
  186. -spin:
  187. - bne spin
  188. -
  189. - mov r10, lr @ Save LR for final return
  190. -
  191. -#ifdef __ARMEB__
  192. - @ Setup for Big Endian
  193. - setend be
  194. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  195. - orr r4, r4, #(1<<25) @ Switch to Big Endian (Set SCTLR.EE)
  196. - mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
  197. -#else
  198. - @ Setup for Little Endian
  199. - setend le
  200. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  201. - bic r4, r4, #(1<<25) @ Switch to LE (unset SCTLR.EE)
  202. - mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
  203. -#endif
  204. -
  205. - bl is_a15_a7
  206. -
  207. - @ For Cortex-A15 and Cortex-A7 only:
  208. - @ Write zero into the ACTLR to turn everything on.
  209. - itt eq
  210. - moveq r4, #0
  211. - mcreq 15, 0, r4, c1, c0, 1
  212. - isb
  213. -
  214. - @ For Cortex-A15 and Cortex-A7 only:
  215. - @ Set ACTLR:SMP bit before enabling the caches and MMU,
  216. - @ or performing any cache and TLB maintenance operations.
  217. - ittt eq
  218. - mrceq 15, 0, r4, c1, c0, 1 @ Read ACTLR
  219. - orreq r4, r4, #(1<<6) @ Enable ACTLR:SMP
  220. - mcreq 15, 0, r4, c1, c0, 1 @ Write ACTLR
  221. - isb
  222. -
  223. - @ Setup for exceptions being taken to Thumb/ARM state
  224. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  225. -#if defined(__thumb__)
  226. - orr r4, r4, #(1 << 30) @ Enable SCTLR.TE
  227. -#else
  228. - bic r4, r4, #(1 << 30) @ Disable SCTLR.TE
  229. -#endif
  230. - mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
  231. -
  232. - bl __reset_caches
  233. -
  234. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  235. - orr r4, r4, #(1<<22) @ Enable unaligned mode
  236. - bic r4, r4, #2 @ Disable alignment faults
  237. - bic r4, r4, #1 @ Disable MMU
  238. - mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
  239. -
  240. - mov r4, #0
  241. - mcr 15, 0, r4, cr8, cr7, 0 @ Write TLBIALL - Invaliidate unified
  242. - @ TLB
  243. - @ Setup MMU Primary table P=V mapping.
  244. - mvn r4, #0
  245. - mcr 15, 0, r4, cr3, cr0, 0 @ Write DACR
  246. -
  247. - mov r4, #0 @ Always use TTBR0, no LPAE
  248. - mcr 15, 0, r4, cr2, cr0, 2 @ Write TTBCR
  249. - adr r4, page_table_addr @ Load the base for vectors
  250. - ldr r4, [r4]
  251. - mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
  252. - tst r0, #0x80000000 @ bis[31]
  253. - @ Set page table flags - there are two page table flag formats for the
  254. - @ architecture. For systems without multiprocessor extensions we use 0x1
  255. - @ which is Inner cacheable/Outer non-cacheable. For systems with
  256. - @ multiprocessor extensions we use 0x59 which is Inner/Outer write-back,
  257. - @ no write-allocate, and cacheable. See the ARMARM-v7AR for more details.
  258. - it ne
  259. - addne r4, r4, #0x58
  260. - add r4, r4, #1
  261. -
  262. - mcr 15, 0, r4, cr2, cr0, 0 @ Write TTBR0
  263. -
  264. - mov r0, #34 @ 0x22 @ TR0 and TR1 - normal memory
  265. - orr r0, r0, #(1 << 19) @ Shareable
  266. - mcr 15, 0, r0, cr10, cr2, 0 @ Write PRRR
  267. - movw r0, #0x33
  268. - movt r0, #0x33
  269. - mcr 15, 0, r0, cr10, cr2, 1 @ Write NMRR
  270. - mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR
  271. - bic r0, r0, #(1 << 28) @ Clear TRE bit
  272. - mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR
  273. -
  274. - @ Now install the vector code - we move the Vector code from where it is
  275. - @ in the image to be based at _rdimon_vector_base. We have to do this copy
  276. - @ as the code is all PC-relative. We actually cheat and do a BX <reg> so
  277. - @ that we are at a known address relatively quickly and have to move as
  278. - @ little code as possible.
  279. - mov r7, #(VectorCode_Limit - VectorCode)
  280. - adr r5, VectorCode
  281. - adr r6, vector_base_addr @ Load the base for vectors
  282. - ldr r6, [r6]
  283. -
  284. -copy_loop: @ Do the copy
  285. - ldr r4, [r5], #4
  286. - str r4, [r6], #4
  287. - subs r7, r7, #4
  288. - bne copy_loop
  289. -
  290. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  291. - bic r4, r4, #0x1000 @ Disable I Cache
  292. - bic r4, r4, #4 @ Disable D Cache
  293. - orr r4, r4, #1 @ Enable MMU
  294. - bic r4, r4, #(1 << 28) @ Clear TRE bit
  295. - mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
  296. - mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR
  297. - orr r4, r4, #0x00f00000 @ Turn on VFP Co-procs
  298. - bic r4, r4, #0x80000000 @ Clear ASEDIS bit
  299. - mcr 15, 0, r4, cr1, cr0, 2 @ Write CPACR
  300. - isb
  301. - mov r4, #0
  302. - mcr 15, 0, r4, cr7, cr5, 4 @ Flush prefetch buffer
  303. - mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR
  304. - ubfx r4, r4, #20, #4 @ Extract bits [20, 23)
  305. - cmp r4, #0xf @ If not all set then the CPU does not
  306. - itt eq @ have FP or Advanced SIMD.
  307. - moveq r4, #0x40000000 @ Enable FP and Advanced SIMD
  308. - mcreq 10, 7, r4, cr8, cr0, 0 @ vmsr fpexc, r4
  309. -skip_vfp_enable:
  310. - bl __enable_caches @ Turn caches on
  311. - bx r10 @ Return to CRT startup routine
  312. -
  313. - @ This enable us to be more precise about which caches we want
  314. -init_cpu_client_enable_dcache:
  315. -init_cpu_client_enable_icache:
  316. - mov r0, #1
  317. - bx lr
  318. -
  319. -vector_base_addr:
  320. - .word _rdimon_vector_base
  321. - .weak _rdimon_vector_base
  322. -page_table_addr:
  323. - .word page_tables
  324. -
  325. - @ Vector code - must be PIC and in ARM state.
  326. -VectorCode:
  327. - b vector_reset
  328. - b vector_undef
  329. - b vector_swi
  330. - b vector_prefetch
  331. - b vector_dataabt
  332. - b vector_reserved
  333. - b vector_irq
  334. - b vector_fiq
  335. -
  336. -vector_reset:
  337. - adr sp, vector_sp_base
  338. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  339. - mov r4, #0
  340. - b vector_common
  341. -vector_undef:
  342. - adr sp, vector_sp_base
  343. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  344. - mov r4, #1
  345. - b vector_common
  346. -vector_swi:
  347. - adr sp, vector_sp_base
  348. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  349. - mov r4, #2
  350. - b vector_common
  351. -vector_prefetch:
  352. - adr sp, vector_sp_base
  353. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  354. - mov r4, #3
  355. - b vector_common
  356. -vector_dataabt:
  357. - adr sp, vector_sp_base
  358. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  359. - mov r4, #4
  360. - b vector_common
  361. -vector_reserved:
  362. - adr sp, vector_sp_base
  363. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  364. - mov r4, #5
  365. - b vector_common
  366. -vector_irq:
  367. - adr sp, vector_sp_base
  368. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  369. - mov r4, #6
  370. - b vector_common
  371. -vector_fiq:
  372. - adr sp, vector_sp_base
  373. - push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
  374. - mov r4, #7
  375. - b vector_common
  376. -vector_common:
  377. - adr r1, vector_common_adr @ Find where we're going to
  378. - ldr r1, [r1]
  379. - bx r1 @ And branch there
  380. -vector_common_adr:
  381. - .word vector_common_2 @ Common handling code
  382. -
  383. - @ Vector stack
  384. - .p2align 3 @ Align to 8 byte boundary boundary to
  385. - @ keep ABI compatibility
  386. - .fill 32, 4, 0 @ 32-entry stack is enough for vector
  387. - @ handlers.
  388. -vector_sp_base:
  389. -VectorCode_Limit:
  390. - @ End of PIC code for vectors
  391. -
  392. - @ Common Handling of vectors
  393. - .type vector_common_2, %function
  394. -vector_common_2:
  395. - mrs r1, APSR
  396. - mrs r2, SPSR
  397. - push {r1, r2} @ Save PSRs
  398. -
  399. - @ Output the vector we have caught
  400. - bl out_nl
  401. - adr r0, which_vector
  402. - bl out_string
  403. - adr r0, vector_names
  404. - mov r1, #11
  405. - mla r0, r4, r1, r0
  406. - bl out_string
  407. - bl out_nl
  408. -
  409. - @ Dump the registers
  410. - adrl r6, register_names
  411. - mov r7, #0
  412. -dump_r_loop:
  413. - mov r0, r6
  414. - bl out_string
  415. - add r6, r6, #6
  416. - ldr r0, [sp, r7, lsl #2]
  417. - bl out_word
  418. - bl out_nl
  419. - add r7, r7, #1
  420. - cmp r7, #16
  421. - blt dump_r_loop
  422. - adr r0, end
  423. - bl out_string
  424. -
  425. - @ And exit
  426. - mov r0, #24
  427. - orr r1, r4, #0x20000
  428. - svc 0x00123456
  429. -
  430. - @ Output the string in r0
  431. -out_string:
  432. - push {lr}
  433. - mov r1, r0
  434. - mov r0, #4
  435. - svc 0x00123456
  436. - pop {pc}
  437. -
  438. - @ Output a New-line
  439. -out_nl:
  440. - mov r0, #10
  441. - @ Fallthrough
  442. -
  443. - @ Output the character in r0
  444. -out_char:
  445. - push {lr}
  446. - strb r0, [sp, #-4]!
  447. - mov r0, #3
  448. - mov r1, sp
  449. - svc 0x00123456
  450. - add sp, sp, #4
  451. - pop {pc}
  452. -
  453. - @ Output the value of r0 as a hex-word
  454. -out_word:
  455. - push {r4, r5, r6, lr}
  456. - mov r4, r0
  457. - mov r5, #28
  458. - adr r6, hexchars
  459. -word_loop:
  460. - lsr r0, r4, r5
  461. - and r0, r0, #15
  462. - ldrb r0, [r6, r0]
  463. - bl out_char
  464. - subs r5, r5, #4
  465. - bpl word_loop
  466. - pop {r4, r5, r6, pc}
  467. -
  468. -hexchars:
  469. - .ascii "0123456789abcdef"
  470. -
  471. -which_vector:
  472. - .asciz "Hit vector:"
  473. -end:
  474. - .asciz "End.\n"
  475. -
  476. -vector_names:
  477. - .asciz "reset "
  478. - .asciz "undef "
  479. - .asciz "swi "
  480. - .asciz "prefetch "
  481. - .asciz "data abort"
  482. - .asciz "reserved "
  483. - .asciz "irq "
  484. - .asciz "fiq "
  485. -
  486. -register_names:
  487. - .asciz "apsr "
  488. - .asciz "spsr "
  489. - .asciz "r0 "
  490. - .asciz "r1 "
  491. - .asciz "r2 "
  492. - .asciz "r3 "
  493. - .asciz "r4 "
  494. - .asciz "r5 "
  495. - .asciz "r6 "
  496. - .asciz "r7 "
  497. - .asciz "r8 "
  498. - .asciz "r9 "
  499. - .asciz "r10 "
  500. - .asciz "r11 "
  501. - .asciz "r12 "
  502. - .asciz "r14 "
  503. -
  504. - .p2align 3
  505. -
  506. -
  507. - @ Enable the caches
  508. -__enable_caches:
  509. - mov r0, #0
  510. - mcr 15, 0, r0, cr8, cr7, 0 @ Invalidate all unified-TLB
  511. - mov r0, #0
  512. - mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
  513. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  514. - orr r4, r4, #0x800 @ Enable branch predictor
  515. - mcr 15, 0, r4, cr1, cr0, 0 @ Set SCTLR
  516. - mov r5, lr @ Save LR as we're going to BL
  517. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  518. - bl init_cpu_client_enable_icache
  519. - cmp r0, #0
  520. - it ne
  521. - orrne r4, r4, #0x1000 @ Enable I-Cache
  522. - bl init_cpu_client_enable_dcache
  523. - cmp r0, #0
  524. - it ne
  525. - orrne r4, r4, #4
  526. - mcr 15, 0, r4, cr1, cr0, 0 @ Enable D-Cache
  527. - bx r5 @ Return
  528. -
  529. -__reset_caches:
  530. - mov ip, lr @ Save LR
  531. - mov r0, #0
  532. - mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
  533. - mrc 15, 0, r6, cr1, cr0, 0 @ Read SCTLR
  534. - mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR!
  535. - bic r0, r0, #0x1000 @ Disable I cache
  536. - mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR
  537. - mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
  538. - tst r0, #3 @ Harvard Cache?
  539. - mov r0, #0
  540. - it ne
  541. - mcrne 15, 0, r0, cr7, cr5, 0 @ Invalidate Instruction Cache?
  542. -
  543. - mrc 15, 0, r1, cr1, cr0, 0 @ Read SCTLR (again!)
  544. - orr r1, r1, #0x800 @ Enable branch predictor
  545. -
  546. - @ If we're not enabling caches we have
  547. - @ no more work to do.
  548. - bl init_cpu_client_enable_icache
  549. - cmp r0, #0
  550. - it ne
  551. - orrne r1, r1, #0x1000 @ Enable I-Cache now -
  552. - @ We actually only do this if we have a
  553. - @ Harvard style cache.
  554. - it eq
  555. - bleq init_cpu_client_enable_dcache
  556. - itt eq
  557. - cmpeq r0, #0
  558. - beq Finished1
  559. -
  560. - mcr 15, 0, r1, cr1, cr0, 0 @ Write SCTLR (turn on Branch predictor & I-cache)
  561. -
  562. - mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
  563. - ands r3, r0, #0x7000000
  564. - lsr r3, r3, #23 @ Total cache levels << 1
  565. - beq Finished1
  566. -
  567. - mov lr, #0 @ lr = cache level << 1
  568. -Loop11:
  569. - mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
  570. - add r2, lr, lr, lsr #1 @ r2 holds cache 'set' position
  571. - lsr r1, r0, r2 @ Bottom 3-bits are Ctype for this level
  572. - and r1, r1, #7 @ Get those 3-bits alone
  573. - cmp r1, #2
  574. - blt Skip1 @ No cache or only I-Cache at this level
  575. - mcr 15, 2, lr, cr0, cr0, 0 @ Write CSSELR
  576. - mov r1, #0
  577. - isb sy
  578. - mrc 15, 1, r1, cr0, cr0, 0 @ Read CCSIDR
  579. - and r2, r1, #7 @ Extract line length field
  580. - add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes)
  581. - movw r0, #0x3ff
  582. - ands r0, r0, r1, lsr #3 @ r0 is the max number on the way size
  583. - clz r4, r0 @ r4 is the bit position of the way size increment
  584. - movw r5, #0x7fff
  585. - ands r5, r5, r1, lsr #13 @ r5 is the max number of the index size (right aligned)
  586. -Loop21:
  587. - mov r7, r0 @ r7 working copy of max way size
  588. -Loop31:
  589. - orr r1, lr, r7, lsl r4 @ factor in way number and cache number
  590. - orr r1, r1, r5, lsl r2 @ factor in set number
  591. - tst r6, #4 @ D-Cache on?
  592. - ite eq
  593. - mcreq 15, 0, r1, cr7, cr6, 2 @ No - invalidate by set/way
  594. - mcrne 15, 0, r1, cr7, cr14, 2 @ yes - clean + invalidate by set/way
  595. - subs r7, r7, #1 @ Decrement way number
  596. - bge Loop31
  597. - subs r5, r5, #1 @ Decrement set number
  598. - bge Loop21
  599. -Skip1:
  600. - add lr, lr, #2 @ increment cache number
  601. - cmp r3, lr
  602. - bgt Loop11
  603. -Finished1:
  604. - @ Now we know the caches are clean we can:
  605. - mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
  606. - bic r4, r4, #4 @ Disable D-Cache
  607. - mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
  608. - mov r4, #0
  609. - mcr 15, 0, r4, cr7, cr5, 6 @ Write BPIALL
  610. -
  611. - bx ip @ Return
  612. -
  613. - @ Set Z if this is a Cortex-A15 or Cortex_A7
  614. - @ Other flags corrupted
  615. -is_a15_a7:
  616. - mrc 15, 0, r8, c0, c0, 0
  617. - movw r9, #0xfff0
  618. - movt r9, #0xff0f
  619. - and r8, r8, r9
  620. - movw r9, #0xc0f0
  621. - movt r9, #0x410f
  622. - cmp r8, r9
  623. - movw r9, #0xc070
  624. - movt r9, #0x410f
  625. - it ne
  626. - cmpne r8, r9
  627. - bx lr
  628. -
  629. - @ Descriptor type: Section
  630. - @ Bufferable: True
  631. - @ Cacheable: True
  632. - @ Execute Never: False
  633. - @ Domain: 0
  634. - @ Impl. Defined: 0
  635. - @ Access: 0/11 Full access
  636. - @ TEX: 001
  637. - @ Shareable: False
  638. - @ Not Global: False
  639. - @ Supersection: False
  640. -#define PT(X) \
  641. - .word X;
  642. -#define PT2(X) \
  643. - PT(X) PT(X + 0x100000) PT(X + 0x200000) PT(X + 0x300000)
  644. -#define PT3(X) \
  645. - PT2(X) PT2(X + 0x400000) PT2(X + 0x800000) PT2(X + 0xc00000)
  646. -#define PT4(X) \
  647. - PT3(X) PT3(X + 0x1000000) PT3(X + 0x2000000) PT3(X + 0x3000000)
  648. -#define PT5(X) \
  649. - PT4(X) PT4(X + 0x4000000) PT4(X + 0x8000000) PT4(X + 0xc000000)
  650. -#define PT6(X) \
  651. - PT5(X) PT5(X + 0x10000000) PT5(X + 0x20000000) PT5(X + 0x30000000)
  652. -#define PT7(X) \
  653. - PT6(X) PT6(X + 0x40000000) PT6(X + 0x80000000) PT6(X + 0xc0000000)
  654. -
  655. - .section page_tables_section, "aw", %progbits
  656. - .p2align 14
  657. -page_tables:
  658. - PT7(0x1c0e)
  659. -
  660. -#endif //#if defined(__ARM_ARCH_7A__) || __ARM_ARCH_PROFILE == 'A'
  661. diff --git a/libgloss/libnosys/configure b/libgloss/libnosys/configure
  662. index 7c23c7a..88f3142 100755
  663. --- a/libgloss/libnosys/configure
  664. +++ b/libgloss/libnosys/configure
  665. @@ -2058,7 +2058,7 @@ case "${target}" in
  666. esac
  667.  
  668. case "${target}" in
  669. - *-*-elf)
  670. + *-*-elf | *-*-eabi*)
  671. $as_echo "#define HAVE_ELF 1" >>confdefs.h
  672.  
  673.  
  674. diff --git a/libgloss/libnosys/configure.in b/libgloss/libnosys/configure.in
  675. index 8908217..5ced9b0 100644
  676. --- a/libgloss/libnosys/configure.in
  677. +++ b/libgloss/libnosys/configure.in
  678. @@ -92,7 +92,7 @@ esac
  679.  
  680. dnl Make sure we know if elf format used
  681. case "${target}" in
  682. - *-*-elf)
  683. + *-*-elf | *-*-eabi*)
  684. AC_DEFINE(HAVE_ELF)
  685.  
  686. AC_CACHE_CHECK([for .previous assembler directive],
  687. diff --git a/newlib/libc/include/stdio.h b/newlib/libc/include/stdio.h
  688. index 164d95b..0f41a86 100644
  689. --- a/newlib/libc/include/stdio.h
  690. +++ b/newlib/libc/include/stdio.h
  691. @@ -690,7 +690,7 @@ _ELIDABLE_INLINE int __sputc_r(struct _reent *_ptr, int _c, FILE *_p) {
  692. __sputc_r (_ptr, '\r', _p);
  693. #endif
  694. if (--_p->_w >= 0 || (_p->_w >= _p->_lbfsize && (char)_c != '\n'))
  695. - return (*_p->_p++ = _c);
  696. + return (*_p->_p++ = (unsigned char)_c);
  697. else
  698. return (__swbuf_r(_ptr, _c, _p));
  699. }
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