module count_4bit(
    input clk,
    input up_down,  // 1-up,0-down
    output [3:0] count
    );

    reg count_tmp;

    always @ (posedge clk)
    begin
        if (up_down == 1)
            count_tmp <= count_tmp + 1;
        else
            count_tmp <= count_tmp - 1;
    end

    assign count = count_tmp;
endmodule