`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.04.2018 18:58:29
// Design Name:
// Module Name: FSM
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module FSM(input L, R, clk, rst, output reg [5:0] LIGHTS);

localparam S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6;
reg [2:0] state_p, // Current state
state_n; // Next state
parameter IDLE = 6'b000000, // Output-coded state assignment
          L3 = 6'b111000, // and tail-light patterns
          L2 = 6'b011000,
          L1 = 6'b001000,
          R1 = 6'b000100,
          R2 = 6'b000110,
          R3 = 6'b000111;

clk_div clk_div(clk, rst, clk_en);

always @(clk_en) begin
 if (rst) begin
 state_p <= S0; // Initial state
 end else begin
 state_p <= state_n;
 end
end

always@(*) begin
 // state_n <= state_p;
 case (state_p)

 S0: begin
    TL <= 3'b000;
    TR <= 3'b000;

    if (L == 1) begin
    state_n <= S1;
    end

    else if (R == 1) begin
    state_n <= S4;
    end

    end

 S1: begin
    TL <= 3'b001;
    state_n <= S2;
    end

 S2: begin
    TL <= 3'b011;
    state_n <= S3;
    end

 S3: begin
    TL <= 3'b111;
    state_n <= S0;
    end

 S4: begin
    TR <= 3'b100;
    state_n <= S5;
    end

 S5: begin
    TR <= 3'b110;
    state_n <= S6;
    end

 S6: begin
    TR <= 3'b111;
    state_n <= S0;
    end

 default: begin
    TL <= 3'b000;
    TR <= 3'b000;
    end

 endcase
end

endmodule