----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.03.2019 12:16:15
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port( clk : in STD_LOGIC;
          btn : in STD_LOGIC_VECTOR (4 downto 0);
          sw  : in STD_LOGIC_VECTOR (15 downto 0);
          led : out STD_LOGIC_VECTOR (15 downto 0);
          an  : out STD_LOGIC_VECTOR (3 downto 0);
          cat : out STD_LOGIC_VECTOR (6 downto 0)
        );
end main;

architecture Behavioral of main is

--component ssd is
--    Port( data : in  std_logic_vector (15 downto 0);
--          clk  : in  std_logic;
--          cat  : out std_logic_vector (6 downto 0);
--          an   : out std_logic_vector (3 downto 0));
--end component;

begin

    ssd1 : entity Work.ssd port map (sw,clk,cat,an);

end Behavioral;