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  1.  
  2. /----------------------------------------------------------------------------\
  3. | |
  4. | yosys -- Yosys Open SYnthesis Suite |
  5. | |
  6. | Copyright (C) 2012 - 2020 Claire Wolf <[email protected]> |
  7. | |
  8. | Permission to use, copy, modify, and/or distribute this software for any |
  9. | purpose with or without fee is hereby granted, provided that the above |
  10. | copyright notice and this permission notice appear in all copies. |
  11. | |
  12. | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
  13. | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
  14. | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
  15. | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
  16. | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
  17. | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
  18. | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
  19. | |
  20. \----------------------------------------------------------------------------/
  21.  
  22. Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
  23.  
  24. [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
  25. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
  26. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
  27. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
  28. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
  29.  
  30. 1. Executing Verilog-2005 frontend: /project/openlane/user_proj_conv/../../caravel/verilog/rtl/defines.v
  31. Parsing SystemVerilog input from `/project/openlane/user_proj_conv/../../caravel/verilog/rtl/defines.v' to AST representation.
  32. Successfully finished Verilog frontend.
  33.  
  34. 2. Executing Verilog-2005 frontend: /project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v
  35. Parsing SystemVerilog input from `/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v' to AST representation.
  36. Generating RTLIL representation for module `\user_proj_conv'.
  37. Generating RTLIL representation for module `\convolve'.
  38. Generating RTLIL representation for module `\shift_register'.
  39. Warning: Replacing memory \arr with list of registers. See /project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:232
  40. Generating RTLIL representation for module `\kernel_mem'.
  41. Generating RTLIL representation for module `\multiplier'.
  42. Successfully finished Verilog frontend.
  43.  
  44. 3. Generating Graphviz representation of design.
  45. Writing dot description to `/project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/hierarchy.dot'.
  46. Dumping module user_proj_conv to page 1.
  47.  
  48. 4. Executing HIERARCHY pass (managing design hierarchy).
  49.  
  50. 4.1. Analyzing design hierarchy..
  51. Top module: \user_proj_conv
  52. Used module: \convolve
  53. Used module: \multiplier
  54. Used module: \kernel_mem
  55. Used module: \shift_register
  56. Parameter \BITS = 9
  57.  
  58. 4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\convolve'.
  59. Parameter \BITS = 9
  60. Generating RTLIL representation for module `$paramod\convolve\BITS=9'.
  61. Parameter \BITS = 9
  62. Parameter \KERNEL_SIZE = 1
  63.  
  64. 4.3. Executing AST frontend in derive mode using pre-parsed AST for module `\multiplier'.
  65. Parameter \BITS = 9
  66. Parameter \KERNEL_SIZE = 1
  67. Generating RTLIL representation for module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  68. Parameter \BITS = 9
  69. Parameter \KERNEL_SIZE = 1
  70.  
  71. 4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\kernel_mem'.
  72. Parameter \BITS = 9
  73. Parameter \KERNEL_SIZE = 1
  74. Generating RTLIL representation for module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  75. Parameter \BITS = 9
  76. Parameter \KERNEL_SIZE = 1
  77.  
  78. 4.5. Executing AST frontend in derive mode using pre-parsed AST for module `\shift_register'.
  79. Parameter \BITS = 9
  80. Parameter \KERNEL_SIZE = 1
  81. Generating RTLIL representation for module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  82. Warning: Replacing memory \arr with list of registers. See /project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:232
  83.  
  84. 4.6. Analyzing design hierarchy..
  85. Top module: \user_proj_conv
  86. Used module: $paramod\convolve\BITS=9
  87. Used module: \multiplier
  88. Used module: \kernel_mem
  89. Used module: \shift_register
  90. Parameter \BITS = 9
  91. Parameter \KERNEL_SIZE = 1
  92. Found cached RTLIL representation for module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  93. Parameter \BITS = 9
  94. Parameter \KERNEL_SIZE = 1
  95. Found cached RTLIL representation for module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  96. Parameter \BITS = 9
  97. Parameter \KERNEL_SIZE = 1
  98. Found cached RTLIL representation for module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  99.  
  100. 4.7. Analyzing design hierarchy..
  101. Top module: \user_proj_conv
  102. Used module: $paramod\convolve\BITS=9
  103. Used module: $paramod\multiplier\BITS=9\KERNEL_SIZE=1
  104. Used module: $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  105. Used module: $paramod\shift_register\BITS=9\KERNEL_SIZE=1
  106.  
  107. 4.8. Analyzing design hierarchy..
  108. Top module: \user_proj_conv
  109. Used module: $paramod\convolve\BITS=9
  110. Used module: $paramod\multiplier\BITS=9\KERNEL_SIZE=1
  111. Used module: $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  112. Used module: $paramod\shift_register\BITS=9\KERNEL_SIZE=1
  113. Removing unused module `\multiplier'.
  114. Removing unused module `\kernel_mem'.
  115. Removing unused module `\shift_register'.
  116. Removing unused module `\convolve'.
  117. Removed 4 unused modules.
  118.  
  119. 5. Executing TRIBUF pass.
  120.  
  121. 6. Executing SYNTH pass.
  122.  
  123. 6.1. Executing HIERARCHY pass (managing design hierarchy).
  124.  
  125. 6.1.1. Analyzing design hierarchy..
  126. Top module: \user_proj_conv
  127. Used module: $paramod\convolve\BITS=9
  128. Used module: $paramod\multiplier\BITS=9\KERNEL_SIZE=1
  129. Used module: $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  130. Used module: $paramod\shift_register\BITS=9\KERNEL_SIZE=1
  131.  
  132. 6.1.2. Analyzing design hierarchy..
  133. Top module: \user_proj_conv
  134. Used module: $paramod\convolve\BITS=9
  135. Used module: $paramod\multiplier\BITS=9\KERNEL_SIZE=1
  136. Used module: $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  137. Used module: $paramod\shift_register\BITS=9\KERNEL_SIZE=1
  138. Removed 0 unused modules.
  139.  
  140. 6.2. Executing PROC pass (convert processes to netlists).
  141.  
  142. 6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
  143. Cleaned up 0 empty switches.
  144.  
  145. 6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
  146. Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159 in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  147. Marked 2 switch rules as full_case in process $proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143 in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  148. Marked 3 switch rules as full_case in process $proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:346$127 in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  149. Removed a total of 0 dead cases.
  150.  
  151. 6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
  152. Removed 2 redundant assignments.
  153. Promoted 12 assignments to connections.
  154.  
  155. 6.2.4. Executing PROC_INIT pass (extract init attributes).
  156.  
  157. 6.2.5. Executing PROC_ARST pass (detect async resets in processes).
  158.  
  159. 6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
  160. Creating decoders for process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:245$162'.
  161. Creating decoders for process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159'.
  162. 1/6: $3\counter[31:0]
  163. 2/6: $2\counter[31:0]
  164. 3/6: $1\counter[31:0]
  165. 4/6: $1\m[31:0]
  166. 5/6: $1\i[31:0]
  167. 6/6: $0\arr[1][8:0]
  168. Creating decoders for process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:319$152'.
  169. Creating decoders for process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  170. 1/6: $0\counter[3:0]
  171. 2/6: $1\i[31:0]
  172. 3/6: $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144
  173. 4/6: $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147
  174. 5/6: $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_DATA[8:0]$146
  175. 6/6: $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_ADDR[3:0]$145
  176. Creating decoders for process `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:362$136'.
  177. Creating decoders for process `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:346$127'.
  178. 1/1: $0\pixel_out[8:0]
  179.  
  180. 6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
  181. No latch inferred for signal `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out' from process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:245$162'.
  182. No latch inferred for signal `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.\j' from process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:245$162'.
  183. No latch inferred for signal `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.\k' from process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:245$162'.
  184. No latch inferred for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out' from process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:319$152'.
  185. No latch inferred for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\j' from process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:319$152'.
  186. No latch inferred for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\k' from process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:319$152'.
  187. No latch inferred for signal `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.\i' from process `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:362$136'.
  188. No latch inferred for signal `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.\accum_out' from process `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:362$136'.
  189.  
  190. 6.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
  191. Creating register for signal `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.\counter' using process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159'.
  192. created $dff cell `$procdff$233' with positive edge clock.
  193. Creating register for signal `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.\i' using process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159'.
  194. created $dff cell `$procdff$234' with positive edge clock.
  195. Creating register for signal `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.\m' using process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159'.
  196. created $dff cell `$procdff$235' with positive edge clock.
  197. Creating register for signal `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.\arr[1]' using process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159'.
  198. created $dff cell `$procdff$236' with positive edge clock.
  199. Creating register for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\counter' using process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  200. created $dff cell `$procdff$237' with positive edge clock.
  201. Creating register for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\i' using process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  202. created $dff cell `$procdff$238' with positive edge clock.
  203. Creating register for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN' using process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  204. created $dff cell `$procdff$239' with positive edge clock.
  205. Creating register for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_ADDR' using process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  206. created $dff cell `$procdff$240' with positive edge clock.
  207. Creating register for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_DATA' using process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  208. created $dff cell `$procdff$241' with positive edge clock.
  209. Creating register for signal `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN' using process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  210. created $dff cell `$procdff$242' with positive edge clock.
  211. Creating register for signal `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out' using process `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:346$127'.
  212. created $dff cell `$procdff$243' with positive edge clock.
  213.  
  214. 6.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
  215. Removing empty process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:245$162'.
  216. Found and cleaned up 3 empty switches in `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159'.
  217. Removing empty process `$paramod\shift_register\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:215$159'.
  218. Removing empty process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:319$152'.
  219. Found and cleaned up 2 empty switches in `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  220. Removing empty process `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:292$143'.
  221. Removing empty process `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:362$136'.
  222. Found and cleaned up 3 empty switches in `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:346$127'.
  223. Removing empty process `$paramod\multiplier\BITS=9\KERNEL_SIZE=1.$proc$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:346$127'.
  224. Cleaned up 8 empty switches.
  225.  
  226. 6.3. Executing OPT_EXPR pass (perform const folding).
  227. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  228. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  229. <suppressed ~1 debug messages>
  230. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  231. <suppressed ~4 debug messages>
  232. Optimizing module $paramod\convolve\BITS=9.
  233. Optimizing module user_proj_conv.
  234. <suppressed ~2 debug messages>
  235.  
  236. 6.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  237. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  238. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  239. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  240. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  241. Finding unused cells or wires in module \user_proj_conv..
  242. Removed 13 unused cells and 71 unused wires.
  243. <suppressed ~23 debug messages>
  244.  
  245. 6.5. Executing CHECK pass (checking for obvious problems).
  246. checking module $paramod\convolve\BITS=9..
  247. checking module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  248. checking module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  249. checking module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  250. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [8] is used but has no driver.
  251. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [7] is used but has no driver.
  252. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [6] is used but has no driver.
  253. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [5] is used but has no driver.
  254. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [4] is used but has no driver.
  255. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [3] is used but has no driver.
  256. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [2] is used but has no driver.
  257. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [1] is used but has no driver.
  258. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [0] is used but has no driver.
  259. checking module user_proj_conv..
  260. found and reported 9 problems.
  261.  
  262. 6.6. Executing OPT pass (performing simple optimizations).
  263.  
  264. 6.6.1. Executing OPT_EXPR pass (perform const folding).
  265. Optimizing module $paramod\convolve\BITS=9.
  266. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  267. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  268. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  269. Optimizing module user_proj_conv.
  270.  
  271. 6.6.2. Executing OPT_MERGE pass (detect identical cells).
  272. Finding identical cells in module `$paramod\convolve\BITS=9'.
  273. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  274. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  275. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  276. <suppressed ~3 debug messages>
  277. Finding identical cells in module `\user_proj_conv'.
  278. Removed a total of 1 cells.
  279.  
  280. 6.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  281. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  282. Creating internal representation of mux trees.
  283. No muxes found in this module.
  284. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  285. Creating internal representation of mux trees.
  286. Evaluating internal representation of mux trees.
  287. Analyzing evaluation results.
  288. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  289. Creating internal representation of mux trees.
  290. Evaluating internal representation of mux trees.
  291. Analyzing evaluation results.
  292. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  293. Creating internal representation of mux trees.
  294. Evaluating internal representation of mux trees.
  295. Analyzing evaluation results.
  296. dead port 2/2 on $mux $procmux$168.
  297. dead port 1/2 on $mux $procmux$171.
  298. dead port 1/2 on $mux $procmux$177.
  299. Running muxtree optimizer on module \user_proj_conv..
  300. Creating internal representation of mux trees.
  301. Evaluating internal representation of mux trees.
  302. Analyzing evaluation results.
  303. Removed 3 multiplexer ports.
  304. <suppressed ~9 debug messages>
  305.  
  306. 6.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  307. Optimizing cells in module $paramod\convolve\BITS=9.
  308. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  309. Consolidated identical input bits for $mux cell $procmux$204:
  310. Old ports: A=9'000000000, B=9'111111111, Y=$0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144
  311. New ports: A=1'0, B=1'1, Y=$0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0]
  312. New connections: $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [8:1] = { $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN[8:0]$144 [0] }
  313. Consolidated identical input bits for $mux cell $procmux$207:
  314. Old ports: A=9'000000000, B=9'111111111, Y=$procmux$207_Y
  315. New ports: A=1'0, B=1'1, Y=$procmux$207_Y [0]
  316. New connections: $procmux$207_Y [8:1] = { $procmux$207_Y [0] $procmux$207_Y [0] $procmux$207_Y [0] $procmux$207_Y [0] $procmux$207_Y [0] $procmux$207_Y [0] $procmux$207_Y [0] $procmux$207_Y [0] }
  317. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  318. Consolidated identical input bits for $mux cell $procmux$210:
  319. Old ports: A=$procmux$207_Y, B=9'000000000, Y=$0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147
  320. New ports: A=$procmux$207_Y [0], B=1'0, Y=$0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0]
  321. New connections: $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [8:1] = { $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] $0$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN[8:0]$147 [0] }
  322. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  323. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  324. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  325. Optimizing cells in module \user_proj_conv.
  326. Performed a total of 3 changes.
  327.  
  328. 6.6.5. Executing OPT_MERGE pass (detect identical cells).
  329. Finding identical cells in module `$paramod\convolve\BITS=9'.
  330. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  331. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  332. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  333. Finding identical cells in module `\user_proj_conv'.
  334. Removed a total of 0 cells.
  335.  
  336. 6.6.6. Executing OPT_DFF pass (perform DFF optimizations).
  337.  
  338. 6.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  339. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  340. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  341. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  342. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  343. Finding unused cells or wires in module \user_proj_conv..
  344. Removed 0 unused cells and 4 unused wires.
  345. <suppressed ~1 debug messages>
  346.  
  347. 6.6.8. Executing OPT_EXPR pass (perform const folding).
  348. Optimizing module $paramod\convolve\BITS=9.
  349. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  350. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  351. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  352. Optimizing module user_proj_conv.
  353.  
  354. 6.6.9. Rerunning OPT passes. (Maybe there is more to do..)
  355.  
  356. 6.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  357. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  358. Creating internal representation of mux trees.
  359. No muxes found in this module.
  360. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  361. Creating internal representation of mux trees.
  362. Evaluating internal representation of mux trees.
  363. Analyzing evaluation results.
  364. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  365. Creating internal representation of mux trees.
  366. Evaluating internal representation of mux trees.
  367. Analyzing evaluation results.
  368. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  369. Creating internal representation of mux trees.
  370. Evaluating internal representation of mux trees.
  371. Analyzing evaluation results.
  372. Running muxtree optimizer on module \user_proj_conv..
  373. Creating internal representation of mux trees.
  374. Evaluating internal representation of mux trees.
  375. Analyzing evaluation results.
  376. Removed 0 multiplexer ports.
  377. <suppressed ~9 debug messages>
  378.  
  379. 6.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  380. Optimizing cells in module $paramod\convolve\BITS=9.
  381. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  382. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  383. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  384. Optimizing cells in module \user_proj_conv.
  385. Performed a total of 0 changes.
  386.  
  387. 6.6.12. Executing OPT_MERGE pass (detect identical cells).
  388. Finding identical cells in module `$paramod\convolve\BITS=9'.
  389. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  390. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  391. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  392. Finding identical cells in module `\user_proj_conv'.
  393. Removed a total of 0 cells.
  394.  
  395. 6.6.13. Executing OPT_DFF pass (perform DFF optimizations).
  396.  
  397. 6.6.14. Executing OPT_CLEAN pass (remove unused cells and wires).
  398. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  399. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  400. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  401. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  402. Finding unused cells or wires in module \user_proj_conv..
  403.  
  404. 6.6.15. Executing OPT_EXPR pass (perform const folding).
  405. Optimizing module $paramod\convolve\BITS=9.
  406. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  407. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  408. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  409. Optimizing module user_proj_conv.
  410.  
  411. 6.6.16. Finished OPT passes. (There is nothing left to do.)
  412.  
  413. 6.7. Executing FSM pass (extract and optimize FSM).
  414.  
  415. 6.7.1. Executing FSM_DETECT pass (finding FSMs in design).
  416. Not marking $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:299$141_EN as FSM state register:
  417. Users of register don't seem to benefit from recoding.
  418. Not marking $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN as FSM state register:
  419. Users of register don't seem to benefit from recoding.
  420.  
  421. 6.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).
  422.  
  423. 6.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).
  424.  
  425. 6.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  426. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  427. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  428. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  429. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  430. Finding unused cells or wires in module \user_proj_conv..
  431.  
  432. 6.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).
  433.  
  434. 6.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
  435.  
  436. 6.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
  437.  
  438. 6.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
  439.  
  440. 6.8. Executing OPT pass (performing simple optimizations).
  441.  
  442. 6.8.1. Executing OPT_EXPR pass (perform const folding).
  443. Optimizing module $paramod\convolve\BITS=9.
  444. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  445. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  446. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  447. Optimizing module user_proj_conv.
  448.  
  449. 6.8.2. Executing OPT_MERGE pass (detect identical cells).
  450. Finding identical cells in module `$paramod\convolve\BITS=9'.
  451. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  452. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  453. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  454. Finding identical cells in module `\user_proj_conv'.
  455. Removed a total of 0 cells.
  456.  
  457. 6.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  458. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  459. Creating internal representation of mux trees.
  460. No muxes found in this module.
  461. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  462. Creating internal representation of mux trees.
  463. Evaluating internal representation of mux trees.
  464. Analyzing evaluation results.
  465. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  466. Creating internal representation of mux trees.
  467. Evaluating internal representation of mux trees.
  468. Analyzing evaluation results.
  469. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  470. Creating internal representation of mux trees.
  471. Evaluating internal representation of mux trees.
  472. Analyzing evaluation results.
  473. Running muxtree optimizer on module \user_proj_conv..
  474. Creating internal representation of mux trees.
  475. Evaluating internal representation of mux trees.
  476. Analyzing evaluation results.
  477. Removed 0 multiplexer ports.
  478. <suppressed ~9 debug messages>
  479.  
  480. 6.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  481. Optimizing cells in module $paramod\convolve\BITS=9.
  482. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  483. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  484. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  485. Optimizing cells in module \user_proj_conv.
  486. Performed a total of 0 changes.
  487.  
  488. 6.8.5. Executing OPT_MERGE pass (detect identical cells).
  489. Finding identical cells in module `$paramod\convolve\BITS=9'.
  490. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  491. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  492. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  493. Finding identical cells in module `\user_proj_conv'.
  494. Removed a total of 0 cells.
  495.  
  496. 6.8.6. Executing OPT_DFF pass (perform DFF optimizations).
  497. Adding SRST signal on $procdff$237 ($dff) from module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 (D = $procmux$195_Y, Q = \counter, rval = 4'0000).
  498. Adding EN signal on $auto$opt_dff.cc:702:run$244 ($sdff) from module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 (D = $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:309$150_Y, Q = \counter).
  499. Adding SRST signal on $procdff$243 ($dff) from module $paramod\multiplier\BITS=9\KERNEL_SIZE=1 (D = $procmux$228_Y [7:0], Q = \pixel_out [7:0], rval = 8'00000000).
  500. Adding SRST signal on $procdff$243 ($dff) from module $paramod\multiplier\BITS=9\KERNEL_SIZE=1 (D = \accum_out [8], Q = \pixel_out [8], rval = 1'0).
  501. Adding SRST signal on $procdff$233 ($dff) from module $paramod\shift_register\BITS=9\KERNEL_SIZE=1 (D = $2\counter[31:0], Q = \counter, rval = 0).
  502. Adding EN signal on $auto$opt_dff.cc:702:run$252 ($sdff) from module $paramod\shift_register\BITS=9\KERNEL_SIZE=1 (D = $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:238$161_Y, Q = \counter).
  503.  
  504. 6.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  505. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  506. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  507. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  508. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  509. Finding unused cells or wires in module \user_proj_conv..
  510. Removed 6 unused cells and 6 unused wires.
  511. <suppressed ~9 debug messages>
  512.  
  513. 6.8.8. Executing OPT_EXPR pass (perform const folding).
  514. Optimizing module $paramod\convolve\BITS=9.
  515. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  516. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  517. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  518. Optimizing module user_proj_conv.
  519.  
  520. 6.8.9. Rerunning OPT passes. (Maybe there is more to do..)
  521.  
  522. 6.8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  523. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  524. Creating internal representation of mux trees.
  525. No muxes found in this module.
  526. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  527. Creating internal representation of mux trees.
  528. Evaluating internal representation of mux trees.
  529. Analyzing evaluation results.
  530. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  531. Creating internal representation of mux trees.
  532. Evaluating internal representation of mux trees.
  533. Analyzing evaluation results.
  534. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  535. Creating internal representation of mux trees.
  536. No muxes found in this module.
  537. Running muxtree optimizer on module \user_proj_conv..
  538. Creating internal representation of mux trees.
  539. Evaluating internal representation of mux trees.
  540. Analyzing evaluation results.
  541. Removed 0 multiplexer ports.
  542. <suppressed ~7 debug messages>
  543.  
  544. 6.8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  545. Optimizing cells in module $paramod\convolve\BITS=9.
  546. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  547. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  548. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  549. Optimizing cells in module \user_proj_conv.
  550. Performed a total of 0 changes.
  551.  
  552. 6.8.12. Executing OPT_MERGE pass (detect identical cells).
  553. Finding identical cells in module `$paramod\convolve\BITS=9'.
  554. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  555. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  556. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  557. Finding identical cells in module `\user_proj_conv'.
  558. Removed a total of 0 cells.
  559.  
  560. 6.8.13. Executing OPT_DFF pass (perform DFF optimizations).
  561.  
  562. 6.8.14. Executing OPT_CLEAN pass (remove unused cells and wires).
  563. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  564. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  565. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  566. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  567. Finding unused cells or wires in module \user_proj_conv..
  568.  
  569. 6.8.15. Executing OPT_EXPR pass (perform const folding).
  570. Optimizing module $paramod\convolve\BITS=9.
  571. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  572. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  573. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  574. Optimizing module user_proj_conv.
  575.  
  576. 6.8.16. Finished OPT passes. (There is nothing left to do.)
  577.  
  578. 6.9. Executing WREDUCE pass (reducing word size of cells).
  579. Removed top 32 address bits (of 32) from memory read port $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memrd$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:323$153 (arr).
  580. Removed top 32 address bits (of 32) from memory write port $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:0$155 (arr).
  581. Removed top 4 address bits (of 4) from memory write port $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:0$156 (arr).
  582. Removed cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$procmux$219 ($mux).
  583. Removed cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$procmux$216 ($mux).
  584. Removed cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$procmux$213 ($mux).
  585. Removed top 8 bits (of 9) from FF cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$procdff$242 ($dff).
  586. Removed cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$procdff$240 ($dff).
  587. Removed top 8 bits (of 9) from FF cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$procdff$239 ($dff).
  588. Removed cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$procmux$222 ($mux).
  589. Removed top 31 bits (of 32) from port B of cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$lt$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:307$148 ($lt).
  590. Removed top 3 bits (of 4) from port B of cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:309$150 ($add).
  591. Removed top 3 bits (of 4) from port B of cell $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.$eq$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:317$151 ($eq).
  592. Removed top 1 bits (of 9) from mux cell $paramod\multiplier\BITS=9\KERNEL_SIZE=1.$procmux$228 ($mux).
  593. Removed top 1 bits (of 9) from mux cell $paramod\multiplier\BITS=9\KERNEL_SIZE=1.$procmux$225 ($mux).
  594. Removed top 10 bits (of 28) from port Y of cell $paramod\multiplier\BITS=9\KERNEL_SIZE=1.$mul$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:365$137 ($mul).
  595. Removed top 1 bits (of 9) from wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.$procmux$225_Y.
  596. Removed top 1 bits (of 9) from wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.$procmux$228_Y.
  597. Removed top 10 bits (of 28) from wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.accum_out.
  598. Removed top 30 bits (of 32) from port B of cell $paramod\shift_register\BITS=9\KERNEL_SIZE=1.$eq$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:235$160 ($eq).
  599. Removed top 31 bits (of 32) from port B of cell $paramod\shift_register\BITS=9\KERNEL_SIZE=1.$add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:238$161 ($add).
  600.  
  601. 6.10. Executing PEEPOPT pass (run peephole optimizers).
  602.  
  603. 6.11. Executing OPT_CLEAN pass (remove unused cells and wires).
  604. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  605. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  606. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  607. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  608. Finding unused cells or wires in module \user_proj_conv..
  609. Removed 0 unused cells and 8 unused wires.
  610. <suppressed ~2 debug messages>
  611.  
  612. 6.12. Executing ALUMACC pass (create $alu and $macc cells).
  613. Extracting $alu and $macc cells in module $paramod\convolve\BITS=9:
  614. created 0 $alu and 0 $macc cells.
  615. Extracting $alu and $macc cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1:
  616. creating $macc model for $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:309$150 ($add).
  617. creating $alu model for $macc $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:309$150.
  618. creating $alu model for $lt$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:307$148 ($lt): new $alu
  619. creating $alu model for $eq$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:317$151 ($eq): merged with $lt$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:307$148.
  620. creating $alu cell for $lt$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:307$148, $eq$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:317$151: $auto$alumacc.cc:485:replace_alu$262
  621. creating $alu cell for $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:309$150: $auto$alumacc.cc:485:replace_alu$273
  622. created 2 $alu and 0 $macc cells.
  623. Extracting $alu and $macc cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1:
  624. creating $macc model for $mul$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:365$137 ($mul).
  625. creating $macc cell for $mul$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:365$137: $auto$alumacc.cc:365:replace_macc$276
  626. created 0 $alu and 1 $macc cells.
  627. Extracting $alu and $macc cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1:
  628. creating $macc model for $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:238$161 ($add).
  629. creating $alu model for $macc $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:238$161.
  630. creating $alu cell for $add$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:238$161: $auto$alumacc.cc:485:replace_alu$277
  631. created 1 $alu and 0 $macc cells.
  632. Extracting $alu and $macc cells in module user_proj_conv:
  633. created 0 $alu and 0 $macc cells.
  634.  
  635. 6.13. Executing SHARE pass (SAT-based resource sharing).
  636.  
  637. 6.14. Executing OPT pass (performing simple optimizations).
  638.  
  639. 6.14.1. Executing OPT_EXPR pass (perform const folding).
  640. Optimizing module $paramod\convolve\BITS=9.
  641. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  642. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  643. <suppressed ~6 debug messages>
  644. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  645. Optimizing module user_proj_conv.
  646.  
  647. 6.14.2. Executing OPT_MERGE pass (detect identical cells).
  648. Finding identical cells in module `$paramod\convolve\BITS=9'.
  649. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  650. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  651. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  652. Finding identical cells in module `\user_proj_conv'.
  653. Removed a total of 0 cells.
  654.  
  655. 6.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  656. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  657. Creating internal representation of mux trees.
  658. No muxes found in this module.
  659. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  660. Creating internal representation of mux trees.
  661. Evaluating internal representation of mux trees.
  662. Analyzing evaluation results.
  663. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  664. Creating internal representation of mux trees.
  665. Evaluating internal representation of mux trees.
  666. Analyzing evaluation results.
  667. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  668. Creating internal representation of mux trees.
  669. No muxes found in this module.
  670. Running muxtree optimizer on module \user_proj_conv..
  671. Creating internal representation of mux trees.
  672. Evaluating internal representation of mux trees.
  673. Analyzing evaluation results.
  674. Removed 0 multiplexer ports.
  675. <suppressed ~5 debug messages>
  676.  
  677. 6.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  678. Optimizing cells in module $paramod\convolve\BITS=9.
  679. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  680. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  681. New input vector for $reduce_or cell $reduce_or$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:349$129: \accum_out [17:9]
  682. New input vector for $reduce_or cell $auto$opt_dff.cc:277:combine_resets$250: { \accum_out [17:9] $auto$rtlil.cc:2121:Not$248 }
  683. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  684. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  685. Optimizing cells in module \user_proj_conv.
  686. Performed a total of 2 changes.
  687.  
  688. 6.14.5. Executing OPT_MERGE pass (detect identical cells).
  689. Finding identical cells in module `$paramod\convolve\BITS=9'.
  690. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  691. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  692. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  693. Finding identical cells in module `\user_proj_conv'.
  694. Removed a total of 0 cells.
  695.  
  696. 6.14.6. Executing OPT_DFF pass (perform DFF optimizations).
  697. Adding SRST signal on $procdff$242 ($dff) from module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 (D = $procmux$207_Y [8], Q = $memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:308$142_EN [8], rval = 1'0).
  698.  
  699. 6.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  700. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  701. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  702. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  703. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  704. Finding unused cells or wires in module \user_proj_conv..
  705. Removed 1 unused cells and 9 unused wires.
  706. <suppressed ~3 debug messages>
  707.  
  708. 6.14.8. Executing OPT_EXPR pass (perform const folding).
  709. Optimizing module $paramod\convolve\BITS=9.
  710. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  711. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  712. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  713. Optimizing module user_proj_conv.
  714.  
  715. 6.14.9. Rerunning OPT passes. (Maybe there is more to do..)
  716.  
  717. 6.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  718. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  719. Creating internal representation of mux trees.
  720. No muxes found in this module.
  721. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  722. Creating internal representation of mux trees.
  723. Evaluating internal representation of mux trees.
  724. Analyzing evaluation results.
  725. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  726. Creating internal representation of mux trees.
  727. Evaluating internal representation of mux trees.
  728. Analyzing evaluation results.
  729. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  730. Creating internal representation of mux trees.
  731. No muxes found in this module.
  732. Running muxtree optimizer on module \user_proj_conv..
  733. Creating internal representation of mux trees.
  734. Evaluating internal representation of mux trees.
  735. Analyzing evaluation results.
  736. Removed 0 multiplexer ports.
  737. <suppressed ~5 debug messages>
  738.  
  739. 6.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  740. Optimizing cells in module $paramod\convolve\BITS=9.
  741. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  742. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  743. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  744. Optimizing cells in module \user_proj_conv.
  745. Performed a total of 0 changes.
  746.  
  747. 6.14.12. Executing OPT_MERGE pass (detect identical cells).
  748. Finding identical cells in module `$paramod\convolve\BITS=9'.
  749. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  750. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  751. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  752. Finding identical cells in module `\user_proj_conv'.
  753. Removed a total of 0 cells.
  754.  
  755. 6.14.13. Executing OPT_DFF pass (perform DFF optimizations).
  756.  
  757. 6.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
  758. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  759. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  760. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  761. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  762. Finding unused cells or wires in module \user_proj_conv..
  763.  
  764. 6.14.15. Executing OPT_EXPR pass (perform const folding).
  765. Optimizing module $paramod\convolve\BITS=9.
  766. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  767. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  768. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  769. Optimizing module user_proj_conv.
  770.  
  771. 6.14.16. Finished OPT passes. (There is nothing left to do.)
  772.  
  773. 6.15. Executing MEMORY pass.
  774.  
  775. 6.15.1. Executing OPT_MEM pass (optimize memories).
  776. Performed a total of 0 transformations.
  777.  
  778. 6.15.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
  779. Checking cell `$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:0$155' in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1': merged $dff to cell.
  780. Checking cell `$memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:0$156' in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1': merged $dff to cell.
  781. Checking cell `$memrd$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:323$153' in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1': no (compatible) $dff found.
  782.  
  783. 6.15.3. Executing OPT_CLEAN pass (remove unused cells and wires).
  784. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  785. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  786. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  787. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  788. Finding unused cells or wires in module \user_proj_conv..
  789. Removed 3 unused cells and 3 unused wires.
  790. <suppressed ~4 debug messages>
  791.  
  792. 6.15.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
  793. Consolidating write ports of memory $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.arr by address:
  794. New clock domain: posedge \clk
  795. Port 0 ($memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:0$155) has addr { }.
  796. Active bits: 111111111
  797. Port 1 ($memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:0$156) has addr { }.
  798. Active bits: 111111111
  799. Merging port 0 into this one.
  800. Creating logic for merging DATA and EN ports.
  801. Active bits: 111111111
  802.  
  803. 6.15.5. Executing OPT_CLEAN pass (remove unused cells and wires).
  804. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  805. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  806. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  807. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  808. Finding unused cells or wires in module \user_proj_conv..
  809.  
  810. 6.15.6. Executing MEMORY_COLLECT pass (generating $mem cells).
  811. Collecting $memrd, $memwr and $meminit for memory `\arr' in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1':
  812. $memwr$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:0$156 ($memwr)
  813. $memrd$\arr$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:323$153 ($memrd)
  814.  
  815. 6.16. Executing OPT_CLEAN pass (remove unused cells and wires).
  816. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  817. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  818. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  819. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  820. Finding unused cells or wires in module \user_proj_conv..
  821.  
  822. 6.17. Executing OPT pass (performing simple optimizations).
  823.  
  824. 6.17.1. Executing OPT_EXPR pass (perform const folding).
  825. Optimizing module $paramod\convolve\BITS=9.
  826. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  827. <suppressed ~25 debug messages>
  828. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  829. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  830. <suppressed ~5 debug messages>
  831. Optimizing module user_proj_conv.
  832.  
  833. 6.17.2. Executing OPT_MERGE pass (detect identical cells).
  834. Finding identical cells in module `$paramod\convolve\BITS=9'.
  835. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  836. <suppressed ~24 debug messages>
  837. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  838. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  839. Finding identical cells in module `\user_proj_conv'.
  840. Removed a total of 8 cells.
  841.  
  842. 6.17.3. Executing OPT_DFF pass (perform DFF optimizations).
  843.  
  844. 6.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  845. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  846. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  847. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  848. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  849. Finding unused cells or wires in module \user_proj_conv..
  850. Removed 2 unused cells and 24 unused wires.
  851. <suppressed ~4 debug messages>
  852.  
  853. 6.17.5. Finished fast OPT passes.
  854.  
  855. 6.18. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
  856. Mapping memory cell \arr in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1:
  857. created 1 $dff cells and 0 static cells of width 9.
  858. read interface: 0 $dff and 1 $mux cells.
  859. write interface: 9 write mux blocks.
  860.  
  861. 6.19. Executing OPT pass (performing simple optimizations).
  862.  
  863. 6.19.1. Executing OPT_EXPR pass (perform const folding).
  864. Optimizing module $paramod\convolve\BITS=9.
  865. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  866. <suppressed ~16 debug messages>
  867. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  868. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  869. Optimizing module user_proj_conv.
  870.  
  871. 6.19.2. Executing OPT_MERGE pass (detect identical cells).
  872. Finding identical cells in module `$paramod\convolve\BITS=9'.
  873. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  874. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  875. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  876. Finding identical cells in module `\user_proj_conv'.
  877. Removed a total of 0 cells.
  878.  
  879. 6.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  880. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  881. Creating internal representation of mux trees.
  882. No muxes found in this module.
  883. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  884. Creating internal representation of mux trees.
  885. Evaluating internal representation of mux trees.
  886. Analyzing evaluation results.
  887. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  888. Creating internal representation of mux trees.
  889. Evaluating internal representation of mux trees.
  890. Analyzing evaluation results.
  891. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  892. Creating internal representation of mux trees.
  893. No muxes found in this module.
  894. Running muxtree optimizer on module \user_proj_conv..
  895. Creating internal representation of mux trees.
  896. Evaluating internal representation of mux trees.
  897. Analyzing evaluation results.
  898. Removed 0 multiplexer ports.
  899. <suppressed ~13 debug messages>
  900.  
  901. 6.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  902. Optimizing cells in module $paramod\convolve\BITS=9.
  903. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  904. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  905. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  906. Optimizing cells in module \user_proj_conv.
  907. Performed a total of 0 changes.
  908.  
  909. 6.19.5. Executing OPT_MERGE pass (detect identical cells).
  910. Finding identical cells in module `$paramod\convolve\BITS=9'.
  911. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  912. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  913. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  914. Finding identical cells in module `\user_proj_conv'.
  915. Removed a total of 0 cells.
  916.  
  917. 6.19.6. Executing OPT_SHARE pass.
  918.  
  919. 6.19.7. Executing OPT_DFF pass (perform DFF optimizations).
  920.  
  921. 6.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).
  922. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  923. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  924. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  925. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  926. Finding unused cells or wires in module \user_proj_conv..
  927. Removed 0 unused cells and 14 unused wires.
  928. <suppressed ~1 debug messages>
  929.  
  930. 6.19.9. Executing OPT_EXPR pass (perform const folding).
  931. Optimizing module $paramod\convolve\BITS=9.
  932. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  933. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  934. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  935. Optimizing module user_proj_conv.
  936.  
  937. 6.19.10. Rerunning OPT passes. (Maybe there is more to do..)
  938.  
  939. 6.19.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  940. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  941. Creating internal representation of mux trees.
  942. No muxes found in this module.
  943. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  944. Creating internal representation of mux trees.
  945. Evaluating internal representation of mux trees.
  946. Analyzing evaluation results.
  947. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  948. Creating internal representation of mux trees.
  949. Evaluating internal representation of mux trees.
  950. Analyzing evaluation results.
  951. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  952. Creating internal representation of mux trees.
  953. No muxes found in this module.
  954. Running muxtree optimizer on module \user_proj_conv..
  955. Creating internal representation of mux trees.
  956. Evaluating internal representation of mux trees.
  957. Analyzing evaluation results.
  958. Removed 0 multiplexer ports.
  959. <suppressed ~13 debug messages>
  960.  
  961. 6.19.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  962. Optimizing cells in module $paramod\convolve\BITS=9.
  963. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  964. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  965. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  966. Optimizing cells in module \user_proj_conv.
  967. Performed a total of 0 changes.
  968.  
  969. 6.19.13. Executing OPT_MERGE pass (detect identical cells).
  970. Finding identical cells in module `$paramod\convolve\BITS=9'.
  971. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  972. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  973. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  974. Finding identical cells in module `\user_proj_conv'.
  975. Removed a total of 0 cells.
  976.  
  977. 6.19.14. Executing OPT_SHARE pass.
  978.  
  979. 6.19.15. Executing OPT_DFF pass (perform DFF optimizations).
  980. Adding EN signal on $memory\arr[0]$338 ($dff) from module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 (D = $auto$rtlil.cc:2151:And$324, Q = \arr[0]).
  981.  
  982. 6.19.16. Executing OPT_CLEAN pass (remove unused cells and wires).
  983. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  984. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  985. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  986. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  987. Finding unused cells or wires in module \user_proj_conv..
  988. Removed 9 unused cells and 9 unused wires.
  989. <suppressed ~10 debug messages>
  990.  
  991. 6.19.17. Executing OPT_EXPR pass (perform const folding).
  992. Optimizing module $paramod\convolve\BITS=9.
  993. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  994. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  995. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  996. Optimizing module user_proj_conv.
  997.  
  998. 6.19.18. Rerunning OPT passes. (Maybe there is more to do..)
  999.  
  1000. 6.19.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  1001. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  1002. Creating internal representation of mux trees.
  1003. No muxes found in this module.
  1004. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1005. Creating internal representation of mux trees.
  1006. Evaluating internal representation of mux trees.
  1007. Analyzing evaluation results.
  1008. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1009. Creating internal representation of mux trees.
  1010. Evaluating internal representation of mux trees.
  1011. Analyzing evaluation results.
  1012. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1013. Creating internal representation of mux trees.
  1014. No muxes found in this module.
  1015. Running muxtree optimizer on module \user_proj_conv..
  1016. Creating internal representation of mux trees.
  1017. Evaluating internal representation of mux trees.
  1018. Analyzing evaluation results.
  1019. Removed 0 multiplexer ports.
  1020. <suppressed ~4 debug messages>
  1021.  
  1022. 6.19.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  1023. Optimizing cells in module $paramod\convolve\BITS=9.
  1024. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  1025. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  1026. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  1027. Optimizing cells in module \user_proj_conv.
  1028. Performed a total of 0 changes.
  1029.  
  1030. 6.19.21. Executing OPT_MERGE pass (detect identical cells).
  1031. Finding identical cells in module `$paramod\convolve\BITS=9'.
  1032. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  1033. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  1034. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  1035. Finding identical cells in module `\user_proj_conv'.
  1036. Removed a total of 0 cells.
  1037.  
  1038. 6.19.22. Executing OPT_SHARE pass.
  1039.  
  1040. 6.19.23. Executing OPT_DFF pass (perform DFF optimizations).
  1041.  
  1042. 6.19.24. Executing OPT_CLEAN pass (remove unused cells and wires).
  1043. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  1044. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1045. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1046. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1047. Finding unused cells or wires in module \user_proj_conv..
  1048.  
  1049. 6.19.25. Executing OPT_EXPR pass (perform const folding).
  1050. Optimizing module $paramod\convolve\BITS=9.
  1051. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  1052. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  1053. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  1054. Optimizing module user_proj_conv.
  1055.  
  1056. 6.19.26. Finished OPT passes. (There is nothing left to do.)
  1057.  
  1058. 6.20. Executing TECHMAP pass (map to technology primitives).
  1059.  
  1060. 6.20.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
  1061. Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
  1062. Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
  1063. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
  1064. Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
  1065. Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
  1066. Generating RTLIL representation for module `\_90_simplemap_various'.
  1067. Generating RTLIL representation for module `\_90_simplemap_registers'.
  1068. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
  1069. Generating RTLIL representation for module `\_90_shift_shiftx'.
  1070. Generating RTLIL representation for module `\_90_fa'.
  1071. Generating RTLIL representation for module `\_90_lcu'.
  1072. Generating RTLIL representation for module `\_90_alu'.
  1073. Generating RTLIL representation for module `\_90_macc'.
  1074. Generating RTLIL representation for module `\_90_alumacc'.
  1075. Generating RTLIL representation for module `\$__div_mod_u'.
  1076. Generating RTLIL representation for module `\$__div_mod_trunc'.
  1077. Generating RTLIL representation for module `\_90_div'.
  1078. Generating RTLIL representation for module `\_90_mod'.
  1079. Generating RTLIL representation for module `\$__div_mod_floor'.
  1080. Generating RTLIL representation for module `\_90_divfloor'.
  1081. Generating RTLIL representation for module `\_90_modfloor'.
  1082. Generating RTLIL representation for module `\_90_pow'.
  1083. Generating RTLIL representation for module `\_90_pmux'.
  1084. Generating RTLIL representation for module `\_90_lut'.
  1085. Successfully finished Verilog frontend.
  1086.  
  1087. 6.20.2. Continuing TECHMAP pass.
  1088. Using extmapper simplemap for cells of type $mux.
  1089. Using extmapper simplemap for cells of type $sdffe.
  1090. Using extmapper simplemap for cells of type $reduce_and.
  1091. Using extmapper simplemap for cells of type $not.
  1092. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
  1093. Using extmapper simplemap for cells of type $eq.
  1094. Using extmapper simplemap for cells of type $xor.
  1095. Using extmapper simplemap for cells of type $and.
  1096. Using template $paramod\_90_lcu\WIDTH=32 for cells of type $lcu.
  1097. Using extmapper simplemap for cells of type $pos.
  1098. Using extmapper simplemap for cells of type $or.
  1099. Using extmapper simplemap for cells of type $sdff.
  1100. Using extmapper simplemap for cells of type $reduce_or.
  1101. Using extmapper maccmap for cells of type $macc.
  1102. add \shift_in * \kernel_in (9x9 bits, unsigned)
  1103. Using template $paramod\_90_fa\WIDTH=18 for cells of type $fa.
  1104. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=18\Y_WIDTH=18 for cells of type $alu.
  1105. Using template $paramod\_90_lcu\WIDTH=18 for cells of type $lcu.
  1106. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
  1107. Using extmapper simplemap for cells of type $dffe.
  1108. Using extmapper simplemap for cells of type $logic_and.
  1109. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
  1110. Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
  1111. Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
  1112. No more expansions possible.
  1113. <suppressed ~921 debug messages>
  1114.  
  1115. 6.21. Executing OPT pass (performing simple optimizations).
  1116.  
  1117. 6.21.1. Executing OPT_EXPR pass (perform const folding).
  1118. Optimizing module $paramod\convolve\BITS=9.
  1119. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  1120. <suppressed ~37 debug messages>
  1121. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  1122. <suppressed ~477 debug messages>
  1123. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  1124. <suppressed ~216 debug messages>
  1125. Optimizing module user_proj_conv.
  1126.  
  1127. 6.21.2. Executing OPT_MERGE pass (detect identical cells).
  1128. Finding identical cells in module `$paramod\convolve\BITS=9'.
  1129. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  1130. <suppressed ~12 debug messages>
  1131. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  1132. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  1133. <suppressed ~6 debug messages>
  1134. Finding identical cells in module `\user_proj_conv'.
  1135. Removed a total of 6 cells.
  1136.  
  1137. 6.21.3. Executing OPT_DFF pass (perform DFF optimizations).
  1138.  
  1139. 6.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  1140. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  1141. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1142. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1143. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1144. Finding unused cells or wires in module \user_proj_conv..
  1145. Removed 61 unused cells and 298 unused wires.
  1146. <suppressed ~64 debug messages>
  1147.  
  1148. 6.21.5. Finished fast OPT passes.
  1149.  
  1150. 6.22. Executing ABC pass (technology mapping using ABC).
  1151.  
  1152. 6.22.1. Extracting gate netlist of module `$paramod\convolve\BITS=9' to `<abc-temp-dir>/input.blif'..
  1153. Extracted 1 gates and 3 wires to a netlist network with 2 inputs and 1 outputs.
  1154.  
  1155. 6.22.1.1. Executing ABC.
  1156. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
  1157. ABC: ABC command line: "source <abc-temp-dir>/abc.script".
  1158. ABC:
  1159. ABC: + read_blif <abc-temp-dir>/input.blif
  1160. ABC: + read_library <abc-temp-dir>/stdcells.genlib
  1161. ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
  1162. ABC: + strash
  1163. ABC: + dretime
  1164. ABC: + map
  1165. ABC: + write_blif <abc-temp-dir>/output.blif
  1166.  
  1167. 6.22.1.2. Re-integrating ABC results.
  1168. ABC RESULTS: AND cells: 1
  1169. ABC RESULTS: internal signals: 0
  1170. ABC RESULTS: input signals: 2
  1171. ABC RESULTS: output signals: 1
  1172. Removing temp directory.
  1173.  
  1174. 6.22.2. Extracting gate netlist of module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1' to `<abc-temp-dir>/input.blif'..
  1175. Extracted 65 gates and 81 wires to a netlist network with 15 inputs and 16 outputs.
  1176.  
  1177. 6.22.2.1. Executing ABC.
  1178. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
  1179. ABC: ABC command line: "source <abc-temp-dir>/abc.script".
  1180. ABC:
  1181. ABC: + read_blif <abc-temp-dir>/input.blif
  1182. ABC: + read_library <abc-temp-dir>/stdcells.genlib
  1183. ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
  1184. ABC: + strash
  1185. ABC: + dretime
  1186. ABC: + map
  1187. ABC: + write_blif <abc-temp-dir>/output.blif
  1188.  
  1189. 6.22.2.2. Re-integrating ABC results.
  1190. ABC RESULTS: ANDNOT cells: 13
  1191. ABC RESULTS: NAND cells: 1
  1192. ABC RESULTS: NOT cells: 1
  1193. ABC RESULTS: OR cells: 5
  1194. ABC RESULTS: ORNOT cells: 1
  1195. ABC RESULTS: XNOR cells: 1
  1196. ABC RESULTS: XOR cells: 2
  1197. ABC RESULTS: internal signals: 50
  1198. ABC RESULTS: input signals: 15
  1199. ABC RESULTS: output signals: 16
  1200. Removing temp directory.
  1201.  
  1202. 6.22.3. Extracting gate netlist of module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1' to `<abc-temp-dir>/input.blif'..
  1203. Extracted 482 gates and 502 wires to a netlist network with 19 inputs and 10 outputs.
  1204.  
  1205. 6.22.3.1. Executing ABC.
  1206. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
  1207. ABC: ABC command line: "source <abc-temp-dir>/abc.script".
  1208. ABC:
  1209. ABC: + read_blif <abc-temp-dir>/input.blif
  1210. ABC: + read_library <abc-temp-dir>/stdcells.genlib
  1211. ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
  1212. ABC: + strash
  1213. ABC: + dretime
  1214. ABC: + map
  1215. ABC: + write_blif <abc-temp-dir>/output.blif
  1216.  
  1217. 6.22.3.2. Re-integrating ABC results.
  1218. ABC RESULTS: AND cells: 78
  1219. ABC RESULTS: ANDNOT cells: 124
  1220. ABC RESULTS: NAND cells: 26
  1221. ABC RESULTS: NOR cells: 16
  1222. ABC RESULTS: NOT cells: 7
  1223. ABC RESULTS: OR cells: 63
  1224. ABC RESULTS: ORNOT cells: 28
  1225. ABC RESULTS: XNOR cells: 48
  1226. ABC RESULTS: XOR cells: 98
  1227. ABC RESULTS: internal signals: 473
  1228. ABC RESULTS: input signals: 19
  1229. ABC RESULTS: output signals: 10
  1230. Removing temp directory.
  1231.  
  1232. 6.22.4. Extracting gate netlist of module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1' to `<abc-temp-dir>/input.blif'..
  1233. Extracted 118 gates and 151 wires to a netlist network with 33 inputs and 34 outputs.
  1234.  
  1235. 6.22.4.1. Executing ABC.
  1236. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
  1237. ABC: ABC command line: "source <abc-temp-dir>/abc.script".
  1238. ABC:
  1239. ABC: + read_blif <abc-temp-dir>/input.blif
  1240. ABC: + read_library <abc-temp-dir>/stdcells.genlib
  1241. ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
  1242. ABC: + strash
  1243. ABC: + dretime
  1244. ABC: + map
  1245. ABC: + write_blif <abc-temp-dir>/output.blif
  1246.  
  1247. 6.22.4.2. Re-integrating ABC results.
  1248. ABC RESULTS: AND cells: 1
  1249. ABC RESULTS: ANDNOT cells: 20
  1250. ABC RESULTS: NAND cells: 15
  1251. ABC RESULTS: NOR cells: 1
  1252. ABC RESULTS: NOT cells: 1
  1253. ABC RESULTS: OR cells: 46
  1254. ABC RESULTS: ORNOT cells: 1
  1255. ABC RESULTS: XNOR cells: 14
  1256. ABC RESULTS: XOR cells: 17
  1257. ABC RESULTS: internal signals: 84
  1258. ABC RESULTS: input signals: 33
  1259. ABC RESULTS: output signals: 34
  1260. Removing temp directory.
  1261.  
  1262. 6.22.5. Extracting gate netlist of module `\user_proj_conv' to `<abc-temp-dir>/input.blif'..
  1263. Extracted 2 gates and 8 wires to a netlist network with 6 inputs and 2 outputs.
  1264.  
  1265. 6.22.5.1. Executing ABC.
  1266. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
  1267. ABC: ABC command line: "source <abc-temp-dir>/abc.script".
  1268. ABC:
  1269. ABC: + read_blif <abc-temp-dir>/input.blif
  1270. ABC: + read_library <abc-temp-dir>/stdcells.genlib
  1271. ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
  1272. ABC: + strash
  1273. ABC: + dretime
  1274. ABC: + map
  1275. ABC: + write_blif <abc-temp-dir>/output.blif
  1276.  
  1277. 6.22.5.2. Re-integrating ABC results.
  1278. ABC RESULTS: MUX cells: 2
  1279. ABC RESULTS: internal signals: 0
  1280. ABC RESULTS: input signals: 6
  1281. ABC RESULTS: output signals: 2
  1282. Removing temp directory.
  1283.  
  1284. 6.23. Executing OPT pass (performing simple optimizations).
  1285.  
  1286. 6.23.1. Executing OPT_EXPR pass (perform const folding).
  1287. Optimizing module $paramod\convolve\BITS=9.
  1288. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  1289. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  1290. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  1291. Optimizing module user_proj_conv.
  1292.  
  1293. 6.23.2. Executing OPT_MERGE pass (detect identical cells).
  1294. Finding identical cells in module `$paramod\convolve\BITS=9'.
  1295. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  1296. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  1297. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  1298. Finding identical cells in module `\user_proj_conv'.
  1299. Removed a total of 0 cells.
  1300.  
  1301. 6.23.3. Executing OPT_DFF pass (perform DFF optimizations).
  1302.  
  1303. 6.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  1304. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  1305. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1306. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1307. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1308. Finding unused cells or wires in module \user_proj_conv..
  1309. Removed 0 unused cells and 254 unused wires.
  1310. <suppressed ~5 debug messages>
  1311.  
  1312. 6.23.5. Finished fast OPT passes.
  1313.  
  1314. 6.24. Executing HIERARCHY pass (managing design hierarchy).
  1315.  
  1316. 6.24.1. Analyzing design hierarchy..
  1317. Top module: \user_proj_conv
  1318. Used module: $paramod\convolve\BITS=9
  1319. Used module: $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  1320. Used module: $paramod\multiplier\BITS=9\KERNEL_SIZE=1
  1321. Used module: $paramod\shift_register\BITS=9\KERNEL_SIZE=1
  1322.  
  1323. 6.24.2. Analyzing design hierarchy..
  1324. Top module: \user_proj_conv
  1325. Used module: $paramod\convolve\BITS=9
  1326. Used module: $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  1327. Used module: $paramod\multiplier\BITS=9\KERNEL_SIZE=1
  1328. Used module: $paramod\shift_register\BITS=9\KERNEL_SIZE=1
  1329. Removed 0 unused modules.
  1330.  
  1331. 6.25. Printing statistics.
  1332.  
  1333. === $paramod\convolve\BITS=9 ===
  1334.  
  1335. Number of wires: 12
  1336. Number of wire bits: 52
  1337. Number of public wires: 11
  1338. Number of public wire bits: 51
  1339. Number of memories: 0
  1340. Number of memory bits: 0
  1341. Number of processes: 0
  1342. Number of cells: 4
  1343. $_AND_ 1
  1344. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  1345. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  1346. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  1347.  
  1348. === $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 ===
  1349.  
  1350. Number of wires: 31
  1351. Number of wire bits: 126
  1352. Number of public wires: 10
  1353. Number of public wire bits: 99
  1354. Number of memories: 0
  1355. Number of memory bits: 0
  1356. Number of processes: 0
  1357. Number of cells: 37
  1358. $_ANDNOT_ 13
  1359. $_DFFE_PP_ 9
  1360. $_NAND_ 1
  1361. $_NOT_ 1
  1362. $_ORNOT_ 1
  1363. $_OR_ 5
  1364. $_SDFFE_PP0P_ 4
  1365. $_XNOR_ 1
  1366. $_XOR_ 2
  1367.  
  1368. === $paramod\multiplier\BITS=9\KERNEL_SIZE=1 ===
  1369.  
  1370. Number of wires: 494
  1371. Number of wire bits: 566
  1372. Number of public wires: 7
  1373. Number of public wire bits: 79
  1374. Number of memories: 0
  1375. Number of memory bits: 0
  1376. Number of processes: 0
  1377. Number of cells: 497
  1378. $_ANDNOT_ 124
  1379. $_AND_ 78
  1380. $_NAND_ 26
  1381. $_NOR_ 16
  1382. $_NOT_ 7
  1383. $_ORNOT_ 28
  1384. $_OR_ 63
  1385. $_SDFF_PN0_ 8
  1386. $_SDFF_PP0_ 1
  1387. $_XNOR_ 48
  1388. $_XOR_ 98
  1389.  
  1390. === $paramod\shift_register\BITS=9\KERNEL_SIZE=1 ===
  1391.  
  1392. Number of wires: 95
  1393. Number of wire bits: 274
  1394. Number of public wires: 10
  1395. Number of public wire bits: 127
  1396. Number of memories: 0
  1397. Number of memory bits: 0
  1398. Number of processes: 0
  1399. Number of cells: 148
  1400. $_ANDNOT_ 20
  1401. $_AND_ 1
  1402. $_NAND_ 15
  1403. $_NOR_ 1
  1404. $_NOT_ 1
  1405. $_ORNOT_ 1
  1406. $_OR_ 46
  1407. $_SDFFE_PP0P_ 32
  1408. $_XNOR_ 14
  1409. $_XOR_ 17
  1410.  
  1411. === user_proj_conv ===
  1412.  
  1413. Number of wires: 24
  1414. Number of wire bits: 638
  1415. Number of public wires: 24
  1416. Number of public wire bits: 638
  1417. Number of memories: 0
  1418. Number of memory bits: 0
  1419. Number of processes: 0
  1420. Number of cells: 3
  1421. $_MUX_ 2
  1422. $paramod\convolve\BITS=9 1
  1423.  
  1424. === design hierarchy ===
  1425.  
  1426. user_proj_conv 1
  1427. $paramod\convolve\BITS=9 1
  1428. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  1429. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  1430. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  1431.  
  1432. Number of wires: 656
  1433. Number of wire bits: 1656
  1434. Number of public wires: 62
  1435. Number of public wire bits: 994
  1436. Number of memories: 0
  1437. Number of memory bits: 0
  1438. Number of processes: 0
  1439. Number of cells: 685
  1440. $_ANDNOT_ 157
  1441. $_AND_ 80
  1442. $_DFFE_PP_ 9
  1443. $_MUX_ 2
  1444. $_NAND_ 42
  1445. $_NOR_ 17
  1446. $_NOT_ 9
  1447. $_ORNOT_ 30
  1448. $_OR_ 114
  1449. $_SDFFE_PP0P_ 36
  1450. $_SDFF_PN0_ 8
  1451. $_SDFF_PP0_ 1
  1452. $_XNOR_ 63
  1453. $_XOR_ 117
  1454.  
  1455. 6.26. Executing CHECK pass (checking for obvious problems).
  1456. checking module $paramod\convolve\BITS=9..
  1457. checking module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1458. checking module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1459. checking module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1460. checking module user_proj_conv..
  1461. found and reported 0 problems.
  1462.  
  1463. 7. Executing SHARE pass (SAT-based resource sharing).
  1464.  
  1465. 8. Executing OPT pass (performing simple optimizations).
  1466.  
  1467. 8.1. Executing OPT_EXPR pass (perform const folding).
  1468. Optimizing module $paramod\convolve\BITS=9.
  1469. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  1470. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  1471. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  1472. Optimizing module user_proj_conv.
  1473.  
  1474. 8.2. Executing OPT_MERGE pass (detect identical cells).
  1475. Finding identical cells in module `$paramod\convolve\BITS=9'.
  1476. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  1477. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  1478. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  1479. Finding identical cells in module `\user_proj_conv'.
  1480. Removed a total of 0 cells.
  1481.  
  1482. 8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  1483. Running muxtree optimizer on module $paramod\convolve\BITS=9..
  1484. Creating internal representation of mux trees.
  1485. No muxes found in this module.
  1486. Running muxtree optimizer on module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1487. Creating internal representation of mux trees.
  1488. No muxes found in this module.
  1489. Running muxtree optimizer on module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1490. Creating internal representation of mux trees.
  1491. No muxes found in this module.
  1492. Running muxtree optimizer on module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1493. Creating internal representation of mux trees.
  1494. No muxes found in this module.
  1495. Running muxtree optimizer on module \user_proj_conv..
  1496. Creating internal representation of mux trees.
  1497. No muxes found in this module.
  1498. Removed 0 multiplexer ports.
  1499.  
  1500. 8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  1501. Optimizing cells in module $paramod\convolve\BITS=9.
  1502. Optimizing cells in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  1503. Optimizing cells in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  1504. Optimizing cells in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  1505. Optimizing cells in module \user_proj_conv.
  1506. Performed a total of 0 changes.
  1507.  
  1508. 8.5. Executing OPT_MERGE pass (detect identical cells).
  1509. Finding identical cells in module `$paramod\convolve\BITS=9'.
  1510. Finding identical cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  1511. Finding identical cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  1512. Finding identical cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  1513. Finding identical cells in module `\user_proj_conv'.
  1514. Removed a total of 0 cells.
  1515.  
  1516. 8.6. Executing OPT_DFF pass (perform DFF optimizations).
  1517.  
  1518. 8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  1519. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  1520. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1521. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1522. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1523. Finding unused cells or wires in module \user_proj_conv..
  1524.  
  1525. 8.8. Executing OPT_EXPR pass (perform const folding).
  1526. Optimizing module $paramod\convolve\BITS=9.
  1527. Optimizing module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  1528. Optimizing module $paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  1529. Optimizing module $paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  1530. Optimizing module user_proj_conv.
  1531.  
  1532. 8.9. Finished OPT passes. (There is nothing left to do.)
  1533.  
  1534. 9. Executing OPT_CLEAN pass (remove unused cells and wires).
  1535. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  1536. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1537. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1538. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1539. Finding unused cells or wires in module \user_proj_conv..
  1540. Removed 0 unused cells and 11 unused wires.
  1541. <suppressed ~11 debug messages>
  1542.  
  1543. 10. Printing statistics.
  1544.  
  1545. === $paramod\convolve\BITS=9 ===
  1546.  
  1547. Number of wires: 12
  1548. Number of wire bits: 52
  1549. Number of public wires: 11
  1550. Number of public wire bits: 51
  1551. Number of memories: 0
  1552. Number of memory bits: 0
  1553. Number of processes: 0
  1554. Number of cells: 4
  1555. $_AND_ 1
  1556. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  1557. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  1558. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  1559.  
  1560. === $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 ===
  1561.  
  1562. Number of wires: 28
  1563. Number of wire bits: 53
  1564. Number of public wires: 7
  1565. Number of public wire bits: 26
  1566. Number of memories: 0
  1567. Number of memory bits: 0
  1568. Number of processes: 0
  1569. Number of cells: 37
  1570. $_ANDNOT_ 13
  1571. $_DFFE_PP_ 9
  1572. $_NAND_ 1
  1573. $_NOT_ 1
  1574. $_ORNOT_ 1
  1575. $_OR_ 5
  1576. $_SDFFE_PP0P_ 4
  1577. $_XNOR_ 1
  1578. $_XOR_ 2
  1579.  
  1580. === $paramod\multiplier\BITS=9\KERNEL_SIZE=1 ===
  1581.  
  1582. Number of wires: 493
  1583. Number of wire bits: 534
  1584. Number of public wires: 6
  1585. Number of public wire bits: 47
  1586. Number of memories: 0
  1587. Number of memory bits: 0
  1588. Number of processes: 0
  1589. Number of cells: 497
  1590. $_ANDNOT_ 124
  1591. $_AND_ 78
  1592. $_NAND_ 26
  1593. $_NOR_ 16
  1594. $_NOT_ 7
  1595. $_ORNOT_ 28
  1596. $_OR_ 63
  1597. $_SDFF_PN0_ 8
  1598. $_SDFF_PP0_ 1
  1599. $_XNOR_ 48
  1600. $_XOR_ 98
  1601.  
  1602. === $paramod\shift_register\BITS=9\KERNEL_SIZE=1 ===
  1603.  
  1604. Number of wires: 92
  1605. Number of wire bits: 201
  1606. Number of public wires: 7
  1607. Number of public wire bits: 54
  1608. Number of memories: 0
  1609. Number of memory bits: 0
  1610. Number of processes: 0
  1611. Number of cells: 148
  1612. $_ANDNOT_ 20
  1613. $_AND_ 1
  1614. $_NAND_ 15
  1615. $_NOR_ 1
  1616. $_NOT_ 1
  1617. $_ORNOT_ 1
  1618. $_OR_ 46
  1619. $_SDFFE_PP0P_ 32
  1620. $_XNOR_ 14
  1621. $_XOR_ 17
  1622.  
  1623. === user_proj_conv ===
  1624.  
  1625. Number of wires: 20
  1626. Number of wire bits: 618
  1627. Number of public wires: 20
  1628. Number of public wire bits: 618
  1629. Number of memories: 0
  1630. Number of memory bits: 0
  1631. Number of processes: 0
  1632. Number of cells: 3
  1633. $_MUX_ 2
  1634. $paramod\convolve\BITS=9 1
  1635.  
  1636. === design hierarchy ===
  1637.  
  1638. user_proj_conv 1
  1639. $paramod\convolve\BITS=9 1
  1640. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  1641. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  1642. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  1643.  
  1644. Number of wires: 645
  1645. Number of wire bits: 1458
  1646. Number of public wires: 51
  1647. Number of public wire bits: 796
  1648. Number of memories: 0
  1649. Number of memory bits: 0
  1650. Number of processes: 0
  1651. Number of cells: 685
  1652. $_ANDNOT_ 157
  1653. $_AND_ 80
  1654. $_DFFE_PP_ 9
  1655. $_MUX_ 2
  1656. $_NAND_ 42
  1657. $_NOR_ 17
  1658. $_NOT_ 9
  1659. $_ORNOT_ 30
  1660. $_OR_ 114
  1661. $_SDFFE_PP0P_ 36
  1662. $_SDFF_PN0_ 8
  1663. $_SDFF_PP0_ 1
  1664. $_XNOR_ 63
  1665. $_XOR_ 117
  1666.  
  1667. mapping tbuf
  1668.  
  1669. 11. Executing TECHMAP pass (map to technology primitives).
  1670.  
  1671. 11.1. Executing Verilog-2005 frontend: /home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
  1672. Parsing Verilog input from `/home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
  1673. Generating RTLIL representation for module `\$_TBUF_'.
  1674. Successfully finished Verilog frontend.
  1675.  
  1676. 11.2. Continuing TECHMAP pass.
  1677. No more expansions possible.
  1678. <suppressed ~3 debug messages>
  1679.  
  1680. 12. Executing SIMPLEMAP pass (map simple cells to gate primitives).
  1681.  
  1682. 13. Executing MUXCOVER pass (mapping to wider MUXes).
  1683. Covering MUX trees in module $paramod\convolve\BITS=9..
  1684. Treeifying 0 MUXes:
  1685. Finished treeification: Found 0 trees.
  1686. Covering trees:
  1687. Added a total of 0 decoder MUXes.
  1688. Covering MUX trees in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  1689. Treeifying 0 MUXes:
  1690. Finished treeification: Found 0 trees.
  1691. Covering trees:
  1692. Added a total of 0 decoder MUXes.
  1693. Covering MUX trees in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  1694. Treeifying 0 MUXes:
  1695. Finished treeification: Found 0 trees.
  1696. Covering trees:
  1697. Added a total of 0 decoder MUXes.
  1698. Covering MUX trees in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  1699. Treeifying 0 MUXes:
  1700. Finished treeification: Found 0 trees.
  1701. Covering trees:
  1702. Added a total of 0 decoder MUXes.
  1703. Covering MUX trees in module user_proj_conv..
  1704. Treeifying 2 MUXes:
  1705. Found tree with 1 MUXes at root \clk.
  1706. Found tree with 1 MUXes at root \rst.
  1707. Finished treeification: Found 2 trees.
  1708. Covering trees:
  1709. Replaced tree at \clk: 1 MUX2, 0 MUX4, 0 MUX8, 0 MUX16
  1710. Replaced tree at \rst: 1 MUX2, 0 MUX4, 0 MUX8, 0 MUX16
  1711. Added a total of 0 decoder MUXes.
  1712. <suppressed ~39 debug messages>
  1713.  
  1714. 14. Executing TECHMAP pass (map to technology primitives).
  1715.  
  1716. 14.1. Executing Verilog-2005 frontend: /home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v
  1717. Parsing Verilog input from `/home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v' to AST representation.
  1718. Generating RTLIL representation for module `\$_MUX4_'.
  1719. Successfully finished Verilog frontend.
  1720.  
  1721. 14.2. Continuing TECHMAP pass.
  1722. No more expansions possible.
  1723. <suppressed ~3 debug messages>
  1724.  
  1725. 15. Executing SIMPLEMAP pass (map simple cells to gate primitives).
  1726.  
  1727. 16. Executing TECHMAP pass (map to technology primitives).
  1728.  
  1729. 16.1. Executing Verilog-2005 frontend: /home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v
  1730. Parsing Verilog input from `/home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v' to AST representation.
  1731. Generating RTLIL representation for module `\$_MUX_'.
  1732. Successfully finished Verilog frontend.
  1733.  
  1734. 16.2. Continuing TECHMAP pass.
  1735. Using template \$_MUX_ for cells of type $_MUX_.
  1736. No more expansions possible.
  1737. <suppressed ~5 debug messages>
  1738.  
  1739. 17. Executing SIMPLEMAP pass (map simple cells to gate primitives).
  1740.  
  1741. 18. Executing TECHMAP pass (map to technology primitives).
  1742.  
  1743. 18.1. Executing Verilog-2005 frontend: /home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v
  1744. Parsing Verilog input from `/home/korlamarch/brown/chips/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation.
  1745. Generating RTLIL representation for module `\$_DLATCH_P_'.
  1746. Generating RTLIL representation for module `\$_DLATCH_N_'.
  1747. Successfully finished Verilog frontend.
  1748.  
  1749. 18.2. Continuing TECHMAP pass.
  1750. No more expansions possible.
  1751. <suppressed ~4 debug messages>
  1752.  
  1753. 19. Executing SIMPLEMAP pass (map simple cells to gate primitives).
  1754.  
  1755. 20. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  1756. cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_.
  1757. cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_.
  1758. cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  1759. cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  1760. final dff cell mappings:
  1761. unmapped dff cell: $_DFF_N_
  1762. \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
  1763. unmapped dff cell: $_DFF_NN0_
  1764. unmapped dff cell: $_DFF_NN1_
  1765. unmapped dff cell: $_DFF_NP0_
  1766. unmapped dff cell: $_DFF_NP1_
  1767. \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
  1768. \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
  1769. unmapped dff cell: $_DFF_PP0_
  1770. unmapped dff cell: $_DFF_PP1_
  1771. \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
  1772. unmapped dff cell: $_DFFSR_NNP_
  1773. unmapped dff cell: $_DFFSR_NPN_
  1774. unmapped dff cell: $_DFFSR_NPP_
  1775. unmapped dff cell: $_DFFSR_PNN_
  1776. unmapped dff cell: $_DFFSR_PNP_
  1777. unmapped dff cell: $_DFFSR_PPN_
  1778. unmapped dff cell: $_DFFSR_PPP_
  1779.  
  1780. 20.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
  1781. Mapping DFF cells in module `$paramod\convolve\BITS=9':
  1782. Mapping DFF cells in module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1':
  1783. mapped 13 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells.
  1784. Mapping DFF cells in module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1':
  1785. mapped 9 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells.
  1786. Mapping DFF cells in module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1':
  1787. mapped 32 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells.
  1788. Mapping DFF cells in module `\user_proj_conv':
  1789.  
  1790. 21. Printing statistics.
  1791.  
  1792. === $paramod\convolve\BITS=9 ===
  1793.  
  1794. Number of wires: 12
  1795. Number of wire bits: 52
  1796. Number of public wires: 11
  1797. Number of public wire bits: 51
  1798. Number of memories: 0
  1799. Number of memory bits: 0
  1800. Number of processes: 0
  1801. Number of cells: 4
  1802. $_AND_ 1
  1803. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  1804. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  1805. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  1806.  
  1807. === $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 ===
  1808.  
  1809. Number of wires: 45
  1810. Number of wire bits: 70
  1811. Number of public wires: 7
  1812. Number of public wire bits: 26
  1813. Number of memories: 0
  1814. Number of memory bits: 0
  1815. Number of processes: 0
  1816. Number of cells: 54
  1817. $_ANDNOT_ 13
  1818. $_MUX_ 17
  1819. $_NAND_ 1
  1820. $_NOT_ 1
  1821. $_ORNOT_ 1
  1822. $_OR_ 5
  1823. $_XNOR_ 1
  1824. $_XOR_ 2
  1825. sky130_fd_sc_hd__dfxtp_2 13
  1826.  
  1827. === $paramod\multiplier\BITS=9\KERNEL_SIZE=1 ===
  1828.  
  1829. Number of wires: 502
  1830. Number of wire bits: 543
  1831. Number of public wires: 6
  1832. Number of public wire bits: 47
  1833. Number of memories: 0
  1834. Number of memory bits: 0
  1835. Number of processes: 0
  1836. Number of cells: 506
  1837. $_ANDNOT_ 124
  1838. $_AND_ 78
  1839. $_MUX_ 9
  1840. $_NAND_ 26
  1841. $_NOR_ 16
  1842. $_NOT_ 7
  1843. $_ORNOT_ 28
  1844. $_OR_ 63
  1845. $_XNOR_ 48
  1846. $_XOR_ 98
  1847. sky130_fd_sc_hd__dfxtp_2 9
  1848.  
  1849. === $paramod\shift_register\BITS=9\KERNEL_SIZE=1 ===
  1850.  
  1851. Number of wires: 156
  1852. Number of wire bits: 265
  1853. Number of public wires: 7
  1854. Number of public wire bits: 54
  1855. Number of memories: 0
  1856. Number of memory bits: 0
  1857. Number of processes: 0
  1858. Number of cells: 212
  1859. $_ANDNOT_ 20
  1860. $_AND_ 1
  1861. $_MUX_ 64
  1862. $_NAND_ 15
  1863. $_NOR_ 1
  1864. $_NOT_ 1
  1865. $_ORNOT_ 1
  1866. $_OR_ 46
  1867. $_XNOR_ 14
  1868. $_XOR_ 17
  1869. sky130_fd_sc_hd__dfxtp_2 32
  1870.  
  1871. === user_proj_conv ===
  1872.  
  1873. Number of wires: 28
  1874. Number of wire bits: 626
  1875. Number of public wires: 20
  1876. Number of public wire bits: 618
  1877. Number of memories: 0
  1878. Number of memory bits: 0
  1879. Number of processes: 0
  1880. Number of cells: 3
  1881. $paramod\convolve\BITS=9 1
  1882. sky130_fd_sc_hd__mux2_1 2
  1883.  
  1884. === design hierarchy ===
  1885.  
  1886. user_proj_conv 1
  1887. $paramod\convolve\BITS=9 1
  1888. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  1889. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  1890. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  1891.  
  1892. Number of wires: 743
  1893. Number of wire bits: 1556
  1894. Number of public wires: 51
  1895. Number of public wire bits: 796
  1896. Number of memories: 0
  1897. Number of memory bits: 0
  1898. Number of processes: 0
  1899. Number of cells: 775
  1900. $_ANDNOT_ 157
  1901. $_AND_ 80
  1902. $_MUX_ 90
  1903. $_NAND_ 42
  1904. $_NOR_ 17
  1905. $_NOT_ 9
  1906. $_ORNOT_ 30
  1907. $_OR_ 114
  1908. $_XNOR_ 63
  1909. $_XOR_ 117
  1910. sky130_fd_sc_hd__dfxtp_2 54
  1911. sky130_fd_sc_hd__mux2_1 2
  1912.  
  1913. [INFO]: ABC: WireLoad : S_4
  1914.  
  1915. 22. Executing ABC pass (technology mapping using ABC).
  1916.  
  1917. 22.1. Extracting gate netlist of module `$paramod\convolve\BITS=9' to `/tmp/yosys-abc-QZyiir/input.blif'..
  1918. Extracted 1 gates and 3 wires to a netlist network with 2 inputs and 1 outputs.
  1919.  
  1920. 22.1.1. Executing ABC.
  1921. Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-QZyiir/abc.script 2>&1
  1922. ABC: ABC command line: "source /tmp/yosys-abc-QZyiir/abc.script".
  1923. ABC:
  1924. ABC: + read_blif /tmp/yosys-abc-QZyiir/input.blif
  1925. ABC: + read_lib -w /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib
  1926. ABC: Parsing finished successfully. Parsing time = 0.09 sec
  1927. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
  1928. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
  1929. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
  1930. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
  1931. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
  1932. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
  1933. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
  1934. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
  1935. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
  1936. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
  1937. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
  1938. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
  1939. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
  1940. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
  1941. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
  1942. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
  1943. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
  1944. ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.13 sec
  1945. ABC: Memory = 7.77 MB. Time = 0.13 sec
  1946. ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
  1947. ABC: + read_constr -v /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  1948. ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
  1949. ABC: Setting output load to be 17.650000.
  1950. ABC: + read_constr /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  1951. ABC: + fx
  1952. ABC: The network is unchanged by fast extract.
  1953. ABC: + mfs
  1954. ABC: + strash
  1955. ABC: + refactor
  1956. ABC: + balance
  1957. ABC: + rewrite
  1958. ABC: + refactor
  1959. ABC: + balance
  1960. ABC: + rewrite
  1961. ABC: + rewrite -z
  1962. ABC: + balance
  1963. ABC: + refactor -z
  1964. ABC: + rewrite -z
  1965. ABC: + balance
  1966. ABC: + retime -D -D 10000 -M 5
  1967. ABC: + scleanup
  1968. ABC: Error: The network is combinational.
  1969. ABC: + fraig_store
  1970. ABC: + balance
  1971. ABC: + fraig_store
  1972. ABC: + balance
  1973. ABC: + rewrite
  1974. ABC: + refactor
  1975. ABC: + balance
  1976. ABC: + rewrite
  1977. ABC: + rewrite -z
  1978. ABC: + balance
  1979. ABC: + refactor -z
  1980. ABC: + rewrite -z
  1981. ABC: + balance
  1982. ABC: + fraig_store
  1983. ABC: + balance
  1984. ABC: + rewrite
  1985. ABC: + refactor
  1986. ABC: + balance
  1987. ABC: + rewrite
  1988. ABC: + rewrite -z
  1989. ABC: + balance
  1990. ABC: + refactor -z
  1991. ABC: + rewrite -z
  1992. ABC: + balance
  1993. ABC: + fraig_store
  1994. ABC: + balance
  1995. ABC: + rewrite
  1996. ABC: + refactor
  1997. ABC: + balance
  1998. ABC: + rewrite
  1999. ABC: + rewrite -z
  2000. ABC: + balance
  2001. ABC: + refactor -z
  2002. ABC: + rewrite -z
  2003. ABC: + balance
  2004. ABC: + fraig_store
  2005. ABC: + fraig_restore
  2006. ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
  2007. ABC: + retime -D -D 10000
  2008. ABC: + buffer -N 5 -S 1000.0
  2009. ABC: + upsize -D 10000
  2010. ABC: Current delay (158.50 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
  2011. ABC: + dnsize -D 10000
  2012. ABC: + stime -p
  2013. ABC: WireLoad = "none" Gates = 1 ( 0.0 %) Cap = 6.9 ff ( 0.0 %) Area = 7.51 (100.0 %) Delay = 209.60 ps (100.0 %)
  2014. ABC: Path 0 -- 2 : 0 1 pi A = 0.00 Df = 2.1 -1.5 ps S = 13.4 ps Cin = 0.0 ff Cout = 1.5 ff Cmax = 0.0 ff G = 0
  2015. ABC: Path 1 -- 4 : 2 1 sky130_fd_sc_hd__and2_2 A = 7.51 Df = 209.6 -30.7 ps S = 106.4 ps Cin = 1.5 ff Cout = 17.6 ff Cmax = 303.0 ff G = 1207
  2016. ABC: Start-point = pi1 (\shift_ready). End-point = po0 ($abc$2475$and$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:180$125_Y).
  2017. ABC: + print_stats -m
  2018. ABC: netlist : i/o = 2/ 1 lat = 0 nd = 1 edge = 2 area = 7.51 delay = 1.00 lev = 1
  2019. ABC: + write_blif /tmp/yosys-abc-QZyiir/output.blif
  2020.  
  2021. 22.1.2. Re-integrating ABC results.
  2022. ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 1
  2023. ABC RESULTS: internal signals: 0
  2024. ABC RESULTS: input signals: 2
  2025. ABC RESULTS: output signals: 1
  2026. Removing temp directory.
  2027.  
  2028. 22.2. Extracting gate netlist of module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1' to `/tmp/yosys-abc-WG4vP1/input.blif'..
  2029. Extracted 41 gates and 66 wires to a netlist network with 24 inputs and 14 outputs.
  2030.  
  2031. 22.2.1. Executing ABC.
  2032. Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-WG4vP1/abc.script 2>&1
  2033. ABC: ABC command line: "source /tmp/yosys-abc-WG4vP1/abc.script".
  2034. ABC:
  2035. ABC: + read_blif /tmp/yosys-abc-WG4vP1/input.blif
  2036. ABC: + read_lib -w /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib
  2037. ABC: Parsing finished successfully. Parsing time = 0.09 sec
  2038. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
  2039. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
  2040. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
  2041. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
  2042. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
  2043. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
  2044. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
  2045. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
  2046. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
  2047. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
  2048. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
  2049. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
  2050. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
  2051. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
  2052. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
  2053. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
  2054. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
  2055. ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.13 sec
  2056. ABC: Memory = 7.77 MB. Time = 0.13 sec
  2057. ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
  2058. ABC: + read_constr -v /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  2059. ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
  2060. ABC: Setting output load to be 17.650000.
  2061. ABC: + read_constr /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  2062. ABC: + fx
  2063. ABC: + mfs
  2064. ABC: + strash
  2065. ABC: + refactor
  2066. ABC: + balance
  2067. ABC: + rewrite
  2068. ABC: + refactor
  2069. ABC: + balance
  2070. ABC: + rewrite
  2071. ABC: + rewrite -z
  2072. ABC: + balance
  2073. ABC: + refactor -z
  2074. ABC: + rewrite -z
  2075. ABC: + balance
  2076. ABC: + retime -D -D 10000 -M 5
  2077. ABC: + scleanup
  2078. ABC: Error: The network is combinational.
  2079. ABC: + fraig_store
  2080. ABC: + balance
  2081. ABC: + fraig_store
  2082. ABC: + balance
  2083. ABC: + rewrite
  2084. ABC: + refactor
  2085. ABC: + balance
  2086. ABC: + rewrite
  2087. ABC: + rewrite -z
  2088. ABC: + balance
  2089. ABC: + refactor -z
  2090. ABC: + rewrite -z
  2091. ABC: + balance
  2092. ABC: + fraig_store
  2093. ABC: + balance
  2094. ABC: + rewrite
  2095. ABC: + refactor
  2096. ABC: + balance
  2097. ABC: + rewrite
  2098. ABC: + rewrite -z
  2099. ABC: + balance
  2100. ABC: + refactor -z
  2101. ABC: + rewrite -z
  2102. ABC: + balance
  2103. ABC: + fraig_store
  2104. ABC: + balance
  2105. ABC: + rewrite
  2106. ABC: + refactor
  2107. ABC: + balance
  2108. ABC: + rewrite
  2109. ABC: + rewrite -z
  2110. ABC: + balance
  2111. ABC: + refactor -z
  2112. ABC: + rewrite -z
  2113. ABC: + balance
  2114. ABC: + fraig_store
  2115. ABC: + fraig_restore
  2116. ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
  2117. ABC: + retime -D -D 10000
  2118. ABC: + buffer -N 5 -S 1000.0
  2119. ABC: + upsize -D 10000
  2120. ABC: Current delay (1401.89 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
  2121. ABC: + dnsize -D 10000
  2122. ABC: + stime -p
  2123. ABC: WireLoad = "none" Gates = 21 ( 19.0 %) Cap = 9.1 ff ( 3.6 %) Area = 177.67 ( 81.0 %) Delay = 1404.11 ps ( 38.1 %)
  2124. ABC: Path 0 -- 1 : 0 3 pi A = 0.00 Df = 9.7 -6.7 ps S = 22.1 ps Cin = 0.0 ff Cout = 7.6 ff Cmax = 0.0 ff G = 0
  2125. ABC: Path 1 -- 43 : 4 3 sky130_fd_sc_hd__or4b_2 A = 10.01 Df = 712.7 -496.9 ps S = 137.9 ps Cin = 1.5 ff Cout = 12.3 ff Cmax = 265.5 ff G = 790
  2126. ABC: Path 2 -- 45 : 3 5 sky130_fd_sc_hd__o21a_2 A = 8.76 Df = 965.2 -595.9 ps S = 77.6 ps Cin = 2.4 ff Cout = 12.3 ff Cmax = 294.8 ff G = 486
  2127. ABC: Path 3 -- 46 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =1094.6 -557.3 ps S = 157.5 ps Cin = 2.1 ff Cout = 12.6 ff Cmax = 130.0 ff G = 564
  2128. ABC: Path 4 -- 49 : 4 1 sky130_fd_sc_hd__a22o_2 A = 10.01 Df =1404.1 -4.4 ps S = 104.8 ps Cin = 2.3 ff Cout = 17.6 ff Cmax = 301.2 ff G = 751
  2129. ABC: Start-point = pi0 (\counter [3]). End-point = po3 ($auto$rtlil.cc:2290:MuxGate$3131).
  2130. ABC: + print_stats -m
  2131. ABC: netlist : i/o = 24/ 14 lat = 0 nd = 21 edge = 63 area =177.67 delay = 4.00 lev = 4
  2132. ABC: + write_blif /tmp/yosys-abc-WG4vP1/output.blif
  2133.  
  2134. 22.2.2. Re-integrating ABC results.
  2135. ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 1
  2136. ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 9
  2137. ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 3
  2138. ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 2
  2139. ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 2
  2140. ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 1
  2141. ABC RESULTS: sky130_fd_sc_hd__nor4_2 cells: 1
  2142. ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 1
  2143. ABC RESULTS: sky130_fd_sc_hd__or4b_2 cells: 1
  2144. ABC RESULTS: internal signals: 28
  2145. ABC RESULTS: input signals: 24
  2146. ABC RESULTS: output signals: 14
  2147. Removing temp directory.
  2148.  
  2149. 22.3. Extracting gate netlist of module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1' to `/tmp/yosys-abc-EgZ9fD/input.blif'..
  2150. Extracted 497 gates and 517 wires to a netlist network with 19 inputs and 9 outputs.
  2151.  
  2152. 22.3.1. Executing ABC.
  2153. Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-EgZ9fD/abc.script 2>&1
  2154. ABC: ABC command line: "source /tmp/yosys-abc-EgZ9fD/abc.script".
  2155. ABC:
  2156. ABC: + read_blif /tmp/yosys-abc-EgZ9fD/input.blif
  2157. ABC: + read_lib -w /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib
  2158. ABC: Parsing finished successfully. Parsing time = 0.09 sec
  2159. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
  2160. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
  2161. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
  2162. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
  2163. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
  2164. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
  2165. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
  2166. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
  2167. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
  2168. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
  2169. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
  2170. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
  2171. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
  2172. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
  2173. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
  2174. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
  2175. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
  2176. ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.12 sec
  2177. ABC: Memory = 7.77 MB. Time = 0.12 sec
  2178. ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
  2179. ABC: + read_constr -v /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  2180. ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
  2181. ABC: Setting output load to be 17.650000.
  2182. ABC: + read_constr /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  2183. ABC: + fx
  2184. ABC: + mfs
  2185. ABC: + strash
  2186. ABC: + refactor
  2187. ABC: + balance
  2188. ABC: + rewrite
  2189. ABC: + refactor
  2190. ABC: + balance
  2191. ABC: + rewrite
  2192. ABC: + rewrite -z
  2193. ABC: + balance
  2194. ABC: + refactor -z
  2195. ABC: + rewrite -z
  2196. ABC: + balance
  2197. ABC: + retime -D -D 10000 -M 5
  2198. ABC: + scleanup
  2199. ABC: Error: The network is combinational.
  2200. ABC: + fraig_store
  2201. ABC: + balance
  2202. ABC: + fraig_store
  2203. ABC: + balance
  2204. ABC: + rewrite
  2205. ABC: + refactor
  2206. ABC: + balance
  2207. ABC: + rewrite
  2208. ABC: + rewrite -z
  2209. ABC: + balance
  2210. ABC: + refactor -z
  2211. ABC: + rewrite -z
  2212. ABC: + balance
  2213. ABC: + fraig_store
  2214. ABC: + balance
  2215. ABC: + rewrite
  2216. ABC: + refactor
  2217. ABC: + balance
  2218. ABC: + rewrite
  2219. ABC: + rewrite -z
  2220. ABC: + balance
  2221. ABC: + refactor -z
  2222. ABC: + rewrite -z
  2223. ABC: + balance
  2224. ABC: + fraig_store
  2225. ABC: + balance
  2226. ABC: + rewrite
  2227. ABC: + refactor
  2228. ABC: + balance
  2229. ABC: + rewrite
  2230. ABC: + rewrite -z
  2231. ABC: + balance
  2232. ABC: + refactor -z
  2233. ABC: + rewrite -z
  2234. ABC: + balance
  2235. ABC: + fraig_store
  2236. ABC: + fraig_restore
  2237. ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
  2238. ABC: + retime -D -D 10000
  2239. ABC: + buffer -N 5 -S 1000.0
  2240. ABC: Node 56 has dup fanin 52.
  2241. ABC: Node 56 has dup fanin 55.
  2242. ABC: Node 56 has dup fanin 52.
  2243. ABC: Node 56 has dup fanin 55.
  2244. ABC: Node 60 has dup fanin 51.
  2245. ABC: Node 60 has dup fanin 56.
  2246. ABC: Node 60 has dup fanin 51.
  2247. ABC: Node 60 has dup fanin 56.
  2248. ABC: Node 67 has dup fanin 63.
  2249. ABC: Node 67 has dup fanin 66.
  2250. ABC: Node 67 has dup fanin 63.
  2251. ABC: Node 67 has dup fanin 66.
  2252. ABC: Node 68 has dup fanin 62.
  2253. ABC: Node 68 has dup fanin 67.
  2254. ABC: Node 68 has dup fanin 62.
  2255. ABC: Node 68 has dup fanin 67.
  2256. ABC: Node 73 has dup fanin 69.
  2257. ABC: Node 73 has dup fanin 72.
  2258. ABC: Node 73 has dup fanin 69.
  2259. ABC: Node 73 has dup fanin 72.
  2260. ABC: Node 74 has dup fanin 68.
  2261. ABC: Node 74 has dup fanin 73.
  2262. ABC: Node 74 has dup fanin 68.
  2263. ABC: Node 74 has dup fanin 73.
  2264. ABC: Node 75 has dup fanin 61.
  2265. ABC: Node 75 has dup fanin 74.
  2266. ABC: Node 75 has dup fanin 61.
  2267. ABC: Node 75 has dup fanin 74.
  2268. ABC: Node 83 has dup fanin 79.
  2269. ABC: Node 83 has dup fanin 82.
  2270. ABC: Node 83 has dup fanin 79.
  2271. ABC: Node 83 has dup fanin 82.
  2272. ABC: Node 84 has dup fanin 78.
  2273. ABC: Node 84 has dup fanin 83.
  2274. ABC: Node 84 has dup fanin 78.
  2275. ABC: Node 84 has dup fanin 83.
  2276. ABC: Node 89 has dup fanin 85.
  2277. ABC: Node 89 has dup fanin 88.
  2278. ABC: Node 89 has dup fanin 85.
  2279. ABC: Node 89 has dup fanin 88.
  2280. ABC: Node 90 has dup fanin 84.
  2281. ABC: Node 90 has dup fanin 89.
  2282. ABC: Node 90 has dup fanin 84.
  2283. ABC: Node 90 has dup fanin 89.
  2284. ABC: Node 91 has dup fanin 77.
  2285. ABC: Node 91 has dup fanin 90.
  2286. ABC: Node 91 has dup fanin 77.
  2287. ABC: Node 91 has dup fanin 90.
  2288. ABC: Node 96 has dup fanin 91.
  2289. ABC: Node 96 has dup fanin 95.
  2290. ABC: Node 96 has dup fanin 91.
  2291. ABC: Node 96 has dup fanin 95.
  2292. ABC: Node 99 has dup fanin 59.
  2293. ABC: Node 99 has dup fanin 60.
  2294. ABC: Node 99 has dup fanin 59.
  2295. ABC: Node 99 has dup fanin 60.
  2296. ABC: Node 100 has dup fanin 48.
  2297. ABC: Node 100 has dup fanin 50.
  2298. ABC: Node 100 has dup fanin 48.
  2299. ABC: Node 100 has dup fanin 50.
  2300. ABC: Node 107 has dup fanin 100.
  2301. ABC: Node 107 has dup fanin 105.
  2302. ABC: Node 107 has dup fanin 100.
  2303. ABC: Node 107 has dup fanin 105.
  2304. ABC: Node 110 has dup fanin 58.
  2305. ABC: Node 110 has dup fanin 75.
  2306. ABC: Node 110 has dup fanin 58.
  2307. ABC: Node 110 has dup fanin 75.
  2308. ABC: Node 113 has dup fanin 98.
  2309. ABC: Node 113 has dup fanin 112.
  2310. ABC: Node 113 has dup fanin 98.
  2311. ABC: Node 113 has dup fanin 112.
  2312. ABC: Node 115 has dup fanin 106.
  2313. ABC: Node 115 has dup fanin 107.
  2314. ABC: Node 115 has dup fanin 106.
  2315. ABC: Node 115 has dup fanin 107.
  2316. ABC: Node 116 has dup fanin 102.
  2317. ABC: Node 116 has dup fanin 104.
  2318. ABC: Node 116 has dup fanin 102.
  2319. ABC: Node 116 has dup fanin 104.
  2320. ABC: Node 122 has dup fanin 113.
  2321. ABC: Node 122 has dup fanin 121.
  2322. ABC: Node 122 has dup fanin 113.
  2323. ABC: Node 122 has dup fanin 121.
  2324. ABC: Node 137 has dup fanin 135.
  2325. ABC: Node 137 has dup fanin 136.
  2326. ABC: Node 137 has dup fanin 135.
  2327. ABC: Node 137 has dup fanin 136.
  2328. ABC: Node 138 has dup fanin 132.
  2329. ABC: Node 138 has dup fanin 137.
  2330. ABC: Node 138 has dup fanin 132.
  2331. ABC: Node 138 has dup fanin 137.
  2332. ABC: Node 139 has dup fanin 127.
  2333. ABC: Node 139 has dup fanin 138.
  2334. ABC: Node 139 has dup fanin 127.
  2335. ABC: Node 139 has dup fanin 138.
  2336. ABC: Node 144 has dup fanin 142.
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  2338. ABC: Node 144 has dup fanin 142.
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  2340. ABC: Node 148 has dup fanin 144.
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  2342. ABC: Node 148 has dup fanin 144.
  2343. ABC: Node 148 has dup fanin 147.
  2344. ABC: Node 156 has dup fanin 129.
  2345. ABC: Node 156 has dup fanin 131.
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  2355. ABC: Node 159 has dup fanin 158.
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  2364. ABC: Node 167 has dup fanin 153.
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  2368. ABC: Node 168 has dup fanin 166.
  2369. ABC: Node 168 has dup fanin 167.
  2370. ABC: Node 168 has dup fanin 166.
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  2375. ABC: Node 173 has dup fanin 172.
  2376. ABC: Node 181 has dup fanin 125.
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  2378. ABC: Node 181 has dup fanin 125.
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  2382. ABC: Node 182 has dup fanin 180.
  2383. ABC: Node 182 has dup fanin 181.
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  2386. ABC: Node 183 has dup fanin 179.
  2387. ABC: Node 183 has dup fanin 182.
  2388. ABC: Node 184 has dup fanin 161.
  2389. ABC: Node 184 has dup fanin 174.
  2390. ABC: Node 184 has dup fanin 161.
  2391. ABC: Node 184 has dup fanin 174.
  2392. ABC: Node 187 has dup fanin 160.
  2393. ABC: Node 187 has dup fanin 185.
  2394. ABC: Node 187 has dup fanin 160.
  2395. ABC: Node 187 has dup fanin 185.
  2396. ABC: Node 194 has dup fanin 192.
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  2398. ABC: Node 194 has dup fanin 192.
  2399. ABC: Node 194 has dup fanin 193.
  2400. ABC: Node 196 has dup fanin 194.
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  2402. ABC: Node 196 has dup fanin 194.
  2403. ABC: Node 196 has dup fanin 195.
  2404. ABC: Node 203 has dup fanin 201.
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  2406. ABC: Node 203 has dup fanin 201.
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  2408. ABC: Node 204 has dup fanin 198.
  2409. ABC: Node 204 has dup fanin 203.
  2410. ABC: Node 204 has dup fanin 198.
  2411. ABC: Node 204 has dup fanin 203.
  2412. ABC: Node 205 has dup fanin 197.
  2413. ABC: Node 205 has dup fanin 204.
  2414. ABC: Node 205 has dup fanin 197.
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  2416. ABC: Node 206 has dup fanin 196.
  2417. ABC: Node 206 has dup fanin 205.
  2418. ABC: Node 206 has dup fanin 196.
  2419. ABC: Node 206 has dup fanin 205.
  2420. ABC: Node 208 has dup fanin 206.
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  2422. ABC: Node 208 has dup fanin 206.
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  2424. ABC: Node 209 has dup fanin 189.
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  2426. ABC: Node 209 has dup fanin 189.
  2427. ABC: Node 209 has dup fanin 208.
  2428. ABC: Node 213 has dup fanin 186.
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  2431. ABC: Node 213 has dup fanin 187.
  2432. ABC: Node 214 has dup fanin 183.
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  2434. ABC: Node 214 has dup fanin 183.
  2435. ABC: Node 214 has dup fanin 184.
  2436. ABC: Node 216 has dup fanin 163.
  2437. ABC: Node 216 has dup fanin 165.
  2438. ABC: Node 216 has dup fanin 163.
  2439. ABC: Node 216 has dup fanin 165.
  2440. ABC: Node 217 has dup fanin 215.
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  2444. ABC: Node 222 has dup fanin 218.
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  2446. ABC: Node 222 has dup fanin 218.
  2447. ABC: Node 222 has dup fanin 221.
  2448. ABC: Node 224 has dup fanin 168.
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  2450. ABC: Node 224 has dup fanin 168.
  2451. ABC: Node 224 has dup fanin 173.
  2452. ABC: Node 225 has dup fanin 223.
  2453. ABC: Node 225 has dup fanin 224.
  2454. ABC: Node 225 has dup fanin 223.
  2455. ABC: Node 225 has dup fanin 224.
  2456. ABC: Node 227 has dup fanin 176.
  2457. ABC: Node 227 has dup fanin 178.
  2458. ABC: Node 227 has dup fanin 176.
  2459. ABC: Node 227 has dup fanin 178.
  2460. ABC: Node 228 has dup fanin 226.
  2461. ABC: Node 228 has dup fanin 227.
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  2463. ABC: Node 228 has dup fanin 227.
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  2465. ABC: Node 230 has dup fanin 229.
  2466. ABC: Node 230 has dup fanin 228.
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  2468. ABC: Node 233 has dup fanin 214.
  2469. ABC: Node 233 has dup fanin 231.
  2470. ABC: Node 233 has dup fanin 214.
  2471. ABC: Node 233 has dup fanin 231.
  2472. ABC: Node 240 has dup fanin 217.
  2473. ABC: Node 240 has dup fanin 222.
  2474. ABC: Node 240 has dup fanin 217.
  2475. ABC: Node 240 has dup fanin 222.
  2476. ABC: Node 241 has dup fanin 239.
  2477. ABC: Node 241 has dup fanin 240.
  2478. ABC: Node 241 has dup fanin 239.
  2479. ABC: Node 241 has dup fanin 240.
  2480. ABC: Node 247 has dup fanin 241.
  2481. ABC: Node 247 has dup fanin 246.
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  2483. ABC: Node 247 has dup fanin 246.
  2484. ABC: Node 248 has dup fanin 238.
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  2486. ABC: Node 248 has dup fanin 238.
  2487. ABC: Node 248 has dup fanin 247.
  2488. ABC: Node 249 has dup fanin 94.
  2489. ABC: Node 249 has dup fanin 248.
  2490. ABC: Node 249 has dup fanin 94.
  2491. ABC: Node 249 has dup fanin 248.
  2492. ABC: Node 250 has dup fanin 97.
  2493. ABC: Node 250 has dup fanin 249.
  2494. ABC: Node 250 has dup fanin 97.
  2495. ABC: Node 250 has dup fanin 249.
  2496. ABC: Node 255 has dup fanin 225.
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  2498. ABC: Node 255 has dup fanin 225.
  2499. ABC: Node 255 has dup fanin 230.
  2500. ABC: Node 256 has dup fanin 254.
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  2502. ABC: Node 256 has dup fanin 254.
  2503. ABC: Node 256 has dup fanin 255.
  2504. ABC: Node 258 has dup fanin 232.
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  2508. ABC: Node 261 has dup fanin 245.
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  2510. ABC: Node 261 has dup fanin 245.
  2511. ABC: Node 261 has dup fanin 256.
  2512. ABC: Node 269 has dup fanin 237.
  2513. ABC: Node 269 has dup fanin 237.
  2514. ABC: Node 281 has dup fanin 279.
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  2516. ABC: Node 281 has dup fanin 279.
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  2524. ABC: Node 284 has dup fanin 276.
  2525. ABC: Node 284 has dup fanin 283.
  2526. ABC: Node 291 has dup fanin 274.
  2527. ABC: Node 291 has dup fanin 275.
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  2529. ABC: Node 291 has dup fanin 275.
  2530. ABC: Node 292 has dup fanin 290.
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  2532. ABC: Node 292 has dup fanin 290.
  2533. ABC: Node 292 has dup fanin 291.
  2534. ABC: Node 293 has dup fanin 289.
  2535. ABC: Node 293 has dup fanin 292.
  2536. ABC: Node 293 has dup fanin 289.
  2537. ABC: Node 293 has dup fanin 292.
  2538. ABC: Node 295 has dup fanin 286.
  2539. ABC: Node 295 has dup fanin 294.
  2540. ABC: Node 295 has dup fanin 286.
  2541. ABC: Node 295 has dup fanin 294.
  2542. ABC: Node 297 has dup fanin 295.
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  2544. ABC: Node 297 has dup fanin 295.
  2545. ABC: Node 297 has dup fanin 296.
  2546. ABC: Node 300 has dup fanin 298.
  2547. ABC: Node 300 has dup fanin 299.
  2548. ABC: Node 300 has dup fanin 298.
  2549. ABC: Node 300 has dup fanin 299.
  2550. ABC: Node 306 has dup fanin 300.
  2551. ABC: Node 306 has dup fanin 301.
  2552. ABC: Node 306 has dup fanin 300.
  2553. ABC: Node 306 has dup fanin 301.
  2554. ABC: Node 316 has dup fanin 314.
  2555. ABC: Node 316 has dup fanin 315.
  2556. ABC: Node 316 has dup fanin 314.
  2557. ABC: Node 316 has dup fanin 315.
  2558. ABC: Node 320 has dup fanin 285.
  2559. ABC: Node 320 has dup fanin 319.
  2560. ABC: Node 320 has dup fanin 285.
  2561. ABC: Node 320 has dup fanin 319.
  2562. ABC: Node 322 has dup fanin 320.
  2563. ABC: Node 322 has dup fanin 321.
  2564. ABC: Node 322 has dup fanin 320.
  2565. ABC: Node 322 has dup fanin 321.
  2566. ABC: Node 329 has dup fanin 327.
  2567. ABC: Node 329 has dup fanin 328.
  2568. ABC: Node 329 has dup fanin 327.
  2569. ABC: Node 329 has dup fanin 328.
  2570. ABC: Node 346 has dup fanin 344.
  2571. ABC: Node 346 has dup fanin 345.
  2572. ABC: Node 346 has dup fanin 344.
  2573. ABC: Node 346 has dup fanin 345.
  2574. ABC: Node 350 has dup fanin 325.
  2575. ABC: Node 350 has dup fanin 349.
  2576. ABC: Node 350 has dup fanin 325.
  2577. ABC: Node 350 has dup fanin 349.
  2578. ABC: Node 354 has dup fanin 212.
  2579. ABC: Node 354 has dup fanin 353.
  2580. ABC: Node 354 has dup fanin 212.
  2581. ABC: Node 354 has dup fanin 353.
  2582. ABC: Node 363 has dup fanin 342.
  2583. ABC: Node 363 has dup fanin 346.
  2584. ABC: Node 363 has dup fanin 342.
  2585. ABC: Node 363 has dup fanin 346.
  2586. ABC: Node 365 has dup fanin 305.
  2587. ABC: Node 365 has dup fanin 364.
  2588. ABC: Node 365 has dup fanin 305.
  2589. ABC: Node 365 has dup fanin 364.
  2590. ABC: Node 368 has dup fanin 338.
  2591. ABC: Node 368 has dup fanin 367.
  2592. ABC: Node 368 has dup fanin 338.
  2593. ABC: Node 368 has dup fanin 367.
  2594. ABC: Node 374 has dup fanin 111.
  2595. ABC: Node 374 has dup fanin 373.
  2596. ABC: Node 374 has dup fanin 111.
  2597. ABC: Node 374 has dup fanin 373.
  2598. ABC: Node 388 has dup fanin 250.
  2599. ABC: Node 388 has dup fanin 251.
  2600. ABC: Node 388 has dup fanin 250.
  2601. ABC: Node 388 has dup fanin 251.
  2602. ABC: + upsize -D 10000
  2603. ABC: Current delay (6346.19 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
  2604. ABC: + dnsize -D 10000
  2605. ABC: + stime -p
  2606. ABC: WireLoad = "none" Gates = 405 ( 18.0 %) Cap = 6.3 ff ( 3.6 %) Area = 3385.75 ( 82.0 %) Delay = 6227.36 ps ( 13.3 %)
  2607. ABC: Path 0 -- 2 : 0 4 pi A = 0.00 Df = 12.2 -8.1 ps S = 25.3 ps Cin = 0.0 ff Cout = 9.9 ff Cmax = 0.0 ff G = 0
  2608. ABC: Path 1 -- 39 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df = 34.5 -1.6 ps S = 24.8 ps Cin = 4.5 ff Cout = 3.8 ff Cmax = 331.4 ff G = 80
  2609. ABC: Path 2 -- 40 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 179.7 -34.3 ps S = 151.1 ps Cin = 2.1 ff Cout = 12.0 ff Cmax = 130.0 ff G = 548
  2610. ABC: Path 3 -- 89 : 4 1 sky130_fd_sc_hd__o22a_2 A = 10.01 Df = 375.7 -36.8 ps S = 31.8 ps Cin = 2.4 ff Cout = 1.6 ff Cmax = 304.9 ff G = 63
  2611. ABC: Path 4 -- 91 : 2 3 sky130_fd_sc_hd__or2_2 A = 6.26 Df = 672.3 -231.0 ps S = 64.4 ps Cin = 1.5 ff Cout = 6.2 ff Cmax = 299.4 ff G = 405
  2612. ABC: Path 5 -- 92 : 4 3 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df = 919.1 -10.8 ps S = 53.0 ps Cin = 1.7 ff Cout = 6.2 ff Cmax = 300.3 ff G = 340
  2613. ABC: Path 6 -- 93 : 4 3 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1178.1 -28.6 ps S = 52.6 ps Cin = 1.7 ff Cout = 6.0 ff Cmax = 300.3 ff G = 335
  2614. ABC: Path 7 -- 99 : 4 3 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1444.5 -18.7 ps S = 53.0 ps Cin = 1.7 ff Cout = 6.2 ff Cmax = 300.3 ff G = 340
  2615. ABC: Path 8 -- 100 : 4 3 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1695.7 -20.7 ps S = 52.6 ps Cin = 1.7 ff Cout = 6.0 ff Cmax = 300.3 ff G = 335
  2616. ABC: Path 9 -- 108 : 4 2 sky130_fd_sc_hd__a2bb2o_2 A = 11.26 Df =1953.4 -18.8 ps S = 46.7 ps Cin = 1.7 ff Cout = 4.0 ff Cmax = 300.3 ff G = 219
  2617. ABC: Path 10 -- 109 : 2 4 sky130_fd_sc_hd__or2_2 A = 6.26 Df =2240.5 -195.3 ps S = 68.0 ps Cin = 1.5 ff Cout = 7.4 ff Cmax = 299.4 ff G = 487
  2618. ABC: Path 11 -- 359 : 4 3 sky130_fd_sc_hd__o22a_2 A = 10.01 Df =3179.3 -176.1 ps S = 70.2 ps Cin = 2.4 ff Cout = 10.9 ff Cmax = 304.9 ff G = 436
  2619. ABC: Path 12 -- 360 : 3 2 sky130_fd_sc_hd__nor3_2 A = 10.01 Df =3326.2 -276.2 ps S = 181.3 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 92.5 ff G = 154
  2620. ABC: Path 13 -- 369 : 2 2 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =3394.1 -230.9 ps S = 95.9 ps Cin = 4.4 ff Cout = 6.1 ff Cmax = 141.9 ff G = 131
  2621. ABC: Path 14 -- 370 : 2 2 sky130_fd_sc_hd__or2_2 A = 6.26 Df =3667.1 -386.4 ps S = 58.3 ps Cin = 1.5 ff Cout = 4.0 ff Cmax = 299.4 ff G = 262
  2622. ABC: Path 15 -- 377 : 2 2 sky130_fd_sc_hd__and2_2 A = 7.51 Df =3874.7 -441.4 ps S = 67.4 ps Cin = 1.5 ff Cout = 9.2 ff Cmax = 303.0 ff G = 600
  2623. ABC: Path 16 -- 378 : 4 1 sky130_fd_sc_hd__a2bb2oi_2 A = 15.01 Df =3993.4 -24.6 ps S = 66.8 ps Cin = 4.5 ff Cout = 1.5 ff Cmax = 130.0 ff G = 30
  2624. ABC: Path 17 -- 379 : 3 1 sky130_fd_sc_hd__or3_2 A = 7.51 Df =4381.8 -312.9 ps S = 70.3 ps Cin = 1.5 ff Cout = 1.8 ff Cmax = 310.4 ff G = 113
  2625. ABC: Path 18 -- 404 : 4 1 sky130_fd_sc_hd__or4_2 A = 8.76 Df =5010.5 -811.7 ps S = 92.2 ps Cin = 1.5 ff Cout = 1.8 ff Cmax = 310.4 ff G = 113
  2626. ABC: Path 19 -- 407 : 2 1 sky130_fd_sc_hd__or2b_2 A = 8.76 Df =5299.5-1020.2 ps S = 46.5 ps Cin = 1.6 ff Cout = 1.5 ff Cmax = 312.2 ff G = 93
  2627. ABC: Path 20 -- 410 : 3 5 sky130_fd_sc_hd__or3b_2 A = 8.76 Df =5814.0-1388.7 ps S = 114.3 ps Cin = 1.5 ff Cout = 14.1 ff Cmax = 269.2 ff G = 899
  2628. ABC: Path 21 -- 411 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =5970.0-1374.7 ps S = 154.4 ps Cin = 2.1 ff Cout = 12.3 ff Cmax = 130.0 ff G = 557
  2629. ABC: Path 22 -- 417 : 3 1 sky130_fd_sc_hd__o21a_2 A = 8.76 Df =6227.4-1423.4 ps S = 104.5 ps Cin = 2.4 ff Cout = 17.6 ff Cmax = 294.8 ff G = 740
  2630. ABC: Start-point = pi1 (\kernel_in [1]). End-point = po1 ($auto$rtlil.cc:2290:MuxGate$3161).
  2631. ABC: + print_stats -m
  2632. ABC: netlist : i/o = 19/ 9 lat = 0 nd = 405 edge = 1167 area =3385.82 delay =26.00 lev = 26
  2633. ABC: + write_blif /tmp/yosys-abc-EgZ9fD/output.blif
  2634.  
  2635. 22.3.2. Re-integrating ABC results.
  2636. ABC RESULTS: sky130_fd_sc_hd__a21bo_2 cells: 11
  2637. ABC RESULTS: sky130_fd_sc_hd__a21boi_2 cells: 3
  2638. ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 2
  2639. ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 4
  2640. ABC RESULTS: sky130_fd_sc_hd__a221o_2 cells: 1
  2641. ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 2
  2642. ABC RESULTS: sky130_fd_sc_hd__a2bb2o_2 cells: 82
  2643. ABC RESULTS: sky130_fd_sc_hd__a2bb2oi_2 cells: 6
  2644. ABC RESULTS: sky130_fd_sc_hd__a32o_2 cells: 2
  2645. ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 3
  2646. ABC RESULTS: sky130_fd_sc_hd__and2b_2 cells: 1
  2647. ABC RESULTS: sky130_fd_sc_hd__and4_2 cells: 20
  2648. ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 44
  2649. ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 29
  2650. ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 3
  2651. ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 10
  2652. ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 1
  2653. ABC RESULTS: sky130_fd_sc_hd__o2111a_2 cells: 1
  2654. ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 1
  2655. ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 8
  2656. ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 4
  2657. ABC RESULTS: sky130_fd_sc_hd__o21ba_2 cells: 19
  2658. ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 1
  2659. ABC RESULTS: sky130_fd_sc_hd__o22a_2 cells: 57
  2660. ABC RESULTS: sky130_fd_sc_hd__o22ai_2 cells: 1
  2661. ABC RESULTS: sky130_fd_sc_hd__o2bb2a_2 cells: 3
  2662. ABC RESULTS: sky130_fd_sc_hd__o31a_2 cells: 1
  2663. ABC RESULTS: sky130_fd_sc_hd__o41a_2 cells: 1
  2664. ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 70
  2665. ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 5
  2666. ABC RESULTS: sky130_fd_sc_hd__or3_2 cells: 3
  2667. ABC RESULTS: sky130_fd_sc_hd__or3b_2 cells: 1
  2668. ABC RESULTS: sky130_fd_sc_hd__or4_2 cells: 5
  2669. ABC RESULTS: internal signals: 489
  2670. ABC RESULTS: input signals: 19
  2671. ABC RESULTS: output signals: 9
  2672. Removing temp directory.
  2673.  
  2674. 22.4. Extracting gate netlist of module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1' to `/tmp/yosys-abc-UzbLjj/input.blif'..
  2675. Extracted 180 gates and 215 wires to a netlist network with 34 inputs and 33 outputs.
  2676.  
  2677. 22.4.1. Executing ABC.
  2678. Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-UzbLjj/abc.script 2>&1
  2679. ABC: ABC command line: "source /tmp/yosys-abc-UzbLjj/abc.script".
  2680. ABC:
  2681. ABC: + read_blif /tmp/yosys-abc-UzbLjj/input.blif
  2682. ABC: + read_lib -w /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib
  2683. ABC: Parsing finished successfully. Parsing time = 0.09 sec
  2684. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
  2685. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
  2686. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
  2687. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
  2688. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
  2689. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
  2690. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
  2691. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
  2692. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
  2693. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
  2694. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
  2695. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
  2696. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
  2697. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
  2698. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
  2699. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
  2700. ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
  2701. ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/user_proj_conv/runs/user_proj_conv/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.12 sec
  2702. ABC: Memory = 7.77 MB. Time = 0.12 sec
  2703. ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
  2704. ABC: + read_constr -v /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  2705. ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
  2706. ABC: Setting output load to be 17.650000.
  2707. ABC: + read_constr /project/openlane/user_proj_conv/runs/user_proj_conv/tmp/synthesis/yosys.sdc
  2708. ABC: + fx
  2709. ABC: + mfs
  2710. ABC: + strash
  2711. ABC: + refactor
  2712. ABC: + balance
  2713. ABC: + rewrite
  2714. ABC: + refactor
  2715. ABC: + balance
  2716. ABC: + rewrite
  2717. ABC: + rewrite -z
  2718. ABC: + balance
  2719. ABC: + refactor -z
  2720. ABC: + rewrite -z
  2721. ABC: + balance
  2722. ABC: + retime -D -D 10000 -M 5
  2723. ABC: + scleanup
  2724. ABC: Error: The network is combinational.
  2725. ABC: + fraig_store
  2726. ABC: + balance
  2727. ABC: + fraig_store
  2728. ABC: + balance
  2729. ABC: + rewrite
  2730. ABC: + refactor
  2731. ABC: + balance
  2732. ABC: + rewrite
  2733. ABC: + rewrite -z
  2734. ABC: + balance
  2735. ABC: + refactor -z
  2736. ABC: + rewrite -z
  2737. ABC: + balance
  2738. ABC: + fraig_store
  2739. ABC: + balance
  2740. ABC: + rewrite
  2741. ABC: + refactor
  2742. ABC: + balance
  2743. ABC: + rewrite
  2744. ABC: + rewrite -z
  2745. ABC: + balance
  2746. ABC: + refactor -z
  2747. ABC: + rewrite -z
  2748. ABC: + balance
  2749. ABC: + fraig_store
  2750. ABC: + balance
  2751. ABC: + rewrite
  2752. ABC: + refactor
  2753. ABC: + balance
  2754. ABC: + rewrite
  2755. ABC: + rewrite -z
  2756. ABC: + balance
  2757. ABC: + refactor -z
  2758. ABC: + rewrite -z
  2759. ABC: + balance
  2760. ABC: + fraig_store
  2761. ABC: + fraig_restore
  2762. ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
  2763. ABC: + retime -D -D 10000
  2764. ABC: + buffer -N 5 -S 1000.0
  2765. ABC: + upsize -D 10000
  2766. ABC: Current delay (7974.43 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
  2767. ABC: + dnsize -D 10000
  2768. ABC: + stime -p
  2769. ABC: WireLoad = "none" Gates = 114 ( 34.2 %) Cap = 9.5 ff ( 4.9 %) Area = 775.74 ( 65.8 %) Delay = 4746.70 ps ( 64.9 %)
  2770. ABC: Path 0 -- 22 : 0 3 pi A = 0.00 Df = 10.8 -7.3 ps S = 23.5 ps Cin = 0.0 ff Cout = 8.6 ff Cmax = 0.0 ff G = 0
  2771. ABC: Path 1 -- 103 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =2674.5-1049.8 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2772. ABC: Path 2 -- 104 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =2711.6-1036.0 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2773. ABC: Path 3 -- 105 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =2774.1-1045.7 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2774. ABC: Path 4 -- 106 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =2811.1-1031.9 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2775. ABC: Path 5 -- 107 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =2873.6-1041.6 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2776. ABC: Path 6 -- 108 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =2910.7-1027.8 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2777. ABC: Path 7 -- 109 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =2973.2-1037.5 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2778. ABC: Path 8 -- 110 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3010.3-1023.7 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2779. ABC: Path 9 -- 111 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3072.8-1033.4 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2780. ABC: Path 10 -- 112 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3109.8-1019.6 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2781. ABC: Path 11 -- 113 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3172.3-1029.3 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2782. ABC: Path 12 -- 114 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3209.4-1015.5 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2783. ABC: Path 13 -- 115 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3271.9-1025.2 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2784. ABC: Path 14 -- 116 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3309.0-1011.4 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2785. ABC: Path 15 -- 117 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3371.5-1021.1 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2786. ABC: Path 16 -- 118 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3408.5-1007.3 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2787. ABC: Path 17 -- 119 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3471.0-1017.0 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2788. ABC: Path 18 -- 120 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3508.1-1003.2 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2789. ABC: Path 19 -- 121 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3570.6-1012.9 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2790. ABC: Path 20 -- 122 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3607.7 -999.1 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2791. ABC: Path 21 -- 123 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3670.2-1008.9 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2792. ABC: Path 22 -- 124 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3707.2 -995.0 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2793. ABC: Path 23 -- 125 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3769.7-1004.8 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2794. ABC: Path 24 -- 126 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3806.8 -991.0 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2795. ABC: Path 25 -- 127 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3869.3-1000.7 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2796. ABC: Path 26 -- 128 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =3906.4 -986.9 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2797. ABC: Path 27 -- 129 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =3968.9 -996.6 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2798. ABC: Path 28 -- 130 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =4005.9 -982.8 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2799. ABC: Path 29 -- 131 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =4068.5 -992.5 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2800. ABC: Path 30 -- 132 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =4105.5 -978.7 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2801. ABC: Path 31 -- 133 : 2 2 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =4168.0 -988.4 ps S = 57.0 ps Cin = 4.4 ff Cout = 7.1 ff Cmax = 295.7 ff G = 154
  2802. ABC: Path 32 -- 134 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =4205.1 -974.6 ps S = 40.4 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 151
  2803. ABC: Path 33 -- 135 : 2 4 sky130_fd_sc_hd__nand2_2 A = 6.26 Df =4277.8 -987.4 ps S = 71.0 ps Cin = 4.4 ff Cout = 9.9 ff Cmax = 295.7 ff G = 215
  2804. ABC: Path 34 -- 138 : 2 3 sky130_fd_sc_hd__or2_2 A = 6.26 Df =4408.1 -822.4 ps S = 73.4 ps Cin = 1.5 ff Cout = 9.8 ff Cmax = 299.4 ff G = 637
  2805. ABC: Path 35 -- 141 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df =4445.9 -794.1 ps S = 45.1 ps Cin = 4.5 ff Cout = 7.1 ff Cmax = 331.4 ff G = 149
  2806. ABC: Path 36 -- 146 : 4 1 sky130_fd_sc_hd__a211oi_2 A = 12.51 Df =4746.7 -357.6 ps S = 374.1 ps Cin = 4.4 ff Cout = 17.6 ff Cmax = 88.8 ff G = 405
  2807. ABC: Start-point = pi21 (\counter [11]). End-point = po2 ($auto$rtlil.cc:2290:MuxGate$3281).
  2808. ABC: + print_stats -m
  2809. ABC: netlist : i/o = 34/ 33 lat = 0 nd = 114 edge = 278 area =775.75 delay =60.00 lev = 60
  2810. ABC: + write_blif /tmp/yosys-abc-UzbLjj/output.blif
  2811.  
  2812. 22.4.2. Re-integrating ABC results.
  2813. ABC RESULTS: sky130_fd_sc_hd__a211oi_2 cells: 2
  2814. ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 6
  2815. ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 33
  2816. ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 27
  2817. ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 2
  2818. ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 1
  2819. ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 27
  2820. ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 2
  2821. ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 2
  2822. ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 1
  2823. ABC RESULTS: sky130_fd_sc_hd__or4_2 cells: 11
  2824. ABC RESULTS: internal signals: 148
  2825. ABC RESULTS: input signals: 34
  2826. ABC RESULTS: output signals: 33
  2827. Removing temp directory.
  2828.  
  2829. 22.5. Extracting gate netlist of module `\user_proj_conv' to `/tmp/yosys-abc-t6QOd1/input.blif'..
  2830. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
  2831. Don't call ABC as there is nothing to map.
  2832. Removing temp directory.
  2833.  
  2834. 23. Executing SETUNDEF pass (replace undef values with defined constants).
  2835.  
  2836. 24. Executing HILOMAP pass (mapping to constant drivers).
  2837.  
  2838. 25. Executing SPLITNETS pass (splitting up multi-bit signals).
  2839.  
  2840. 26. Executing OPT_CLEAN pass (remove unused cells and wires).
  2841. Finding unused cells or wires in module $paramod\convolve\BITS=9..
  2842. Finding unused cells or wires in module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  2843. Finding unused cells or wires in module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  2844. Finding unused cells or wires in module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  2845. Finding unused cells or wires in module \user_proj_conv..
  2846. Removed 0 unused cells and 1082 unused wires.
  2847. <suppressed ~33 debug messages>
  2848.  
  2849. 27. Executing INSBUF pass (insert buffer cells for connected wires).
  2850. Added user_proj_conv.$auto$insbuf.cc:79:execute$4266: \io_oeb [37] -> \io_oeb [20]
  2851. Added user_proj_conv.$auto$insbuf.cc:79:execute$4267: \io_oeb [37] -> \io_oeb [21]
  2852. Added user_proj_conv.$auto$insbuf.cc:79:execute$4268: \io_oeb [37] -> \io_oeb [22]
  2853. Added user_proj_conv.$auto$insbuf.cc:79:execute$4269: \io_oeb [37] -> \io_oeb [23]
  2854. Added user_proj_conv.$auto$insbuf.cc:79:execute$4270: \io_oeb [37] -> \io_oeb [24]
  2855. Added user_proj_conv.$auto$insbuf.cc:79:execute$4271: \io_oeb [37] -> \io_oeb [25]
  2856. Added user_proj_conv.$auto$insbuf.cc:79:execute$4272: \io_oeb [37] -> \io_oeb [26]
  2857. Added user_proj_conv.$auto$insbuf.cc:79:execute$4273: \io_oeb [37] -> \io_oeb [27]
  2858. Added user_proj_conv.$auto$insbuf.cc:79:execute$4274: \io_oeb [37] -> \io_oeb [28]
  2859. Added user_proj_conv.$auto$insbuf.cc:79:execute$4275: \io_oeb [37] -> \io_oeb [29]
  2860. Added user_proj_conv.$auto$insbuf.cc:79:execute$4276: \io_oeb [37] -> \io_oeb [30]
  2861. Added user_proj_conv.$auto$insbuf.cc:79:execute$4277: \io_oeb [37] -> \io_oeb [31]
  2862. Added user_proj_conv.$auto$insbuf.cc:79:execute$4278: \io_oeb [37] -> \io_oeb [32]
  2863. Added user_proj_conv.$auto$insbuf.cc:79:execute$4279: \io_oeb [37] -> \io_oeb [33]
  2864. Added user_proj_conv.$auto$insbuf.cc:79:execute$4280: \io_oeb [37] -> \io_oeb [34]
  2865. Added user_proj_conv.$auto$insbuf.cc:79:execute$4281: \io_oeb [37] -> \io_oeb [35]
  2866. Added user_proj_conv.$auto$insbuf.cc:79:execute$4282: \io_oeb [37] -> \io_oeb [36]
  2867. Added user_proj_conv.$auto$insbuf.cc:79:execute$4283: \io_out [29] -> \io_out [20]
  2868. Added user_proj_conv.$auto$insbuf.cc:79:execute$4284: \io_out [30] -> \io_out [21]
  2869. Added user_proj_conv.$auto$insbuf.cc:79:execute$4285: \io_out [31] -> \io_out [22]
  2870. Added user_proj_conv.$auto$insbuf.cc:79:execute$4286: \io_out [32] -> \io_out [23]
  2871. Added user_proj_conv.$auto$insbuf.cc:79:execute$4287: \io_out [33] -> \io_out [24]
  2872. Added user_proj_conv.$auto$insbuf.cc:79:execute$4288: \io_out [34] -> \io_out [25]
  2873. Added user_proj_conv.$auto$insbuf.cc:79:execute$4289: \io_out [35] -> \io_out [26]
  2874. Added user_proj_conv.$auto$insbuf.cc:79:execute$4290: \io_out [36] -> \io_out [27]
  2875. Added user_proj_conv.$auto$insbuf.cc:79:execute$4291: \io_out [37] -> \io_out [28]
  2876.  
  2877. 28. Executing CHECK pass (checking for obvious problems).
  2878. checking module $paramod\convolve\BITS=9..
  2879. Warning: Wire $paramod\convolve\BITS=9.$abc$2475$and$/project/openlane/user_proj_conv/../../verilog/rtl/user_proj_conv.v:180$125_Y is used but has no driver.
  2880. checking module $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1..
  2881. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\ready is used but has no driver.
  2882. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [8] is used but has no driver.
  2883. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [7] is used but has no driver.
  2884. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [6] is used but has no driver.
  2885. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [5] is used but has no driver.
  2886. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [4] is used but has no driver.
  2887. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [3] is used but has no driver.
  2888. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [2] is used but has no driver.
  2889. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [1] is used but has no driver.
  2890. Warning: Wire $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.\out [0] is used but has no driver.
  2891. checking module $paramod\multiplier\BITS=9\KERNEL_SIZE=1..
  2892. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [8] is used but has no driver.
  2893. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [7] is used but has no driver.
  2894. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [6] is used but has no driver.
  2895. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [5] is used but has no driver.
  2896. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [4] is used but has no driver.
  2897. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [3] is used but has no driver.
  2898. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [2] is used but has no driver.
  2899. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [1] is used but has no driver.
  2900. Warning: Wire $paramod\multiplier\BITS=9\KERNEL_SIZE=1.\pixel_out [0] is used but has no driver.
  2901. checking module $paramod\shift_register\BITS=9\KERNEL_SIZE=1..
  2902. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\ready is used but has no driver.
  2903. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [8] is used but has no driver.
  2904. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [7] is used but has no driver.
  2905. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [6] is used but has no driver.
  2906. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [5] is used but has no driver.
  2907. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [4] is used but has no driver.
  2908. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [3] is used but has no driver.
  2909. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [2] is used but has no driver.
  2910. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [1] is used but has no driver.
  2911. Warning: Wire $paramod\shift_register\BITS=9\KERNEL_SIZE=1.\out [0] is used but has no driver.
  2912. checking module user_proj_conv..
  2913. Warning: Wire user_proj_conv.\wbs_dat_o [31] is used but has no driver.
  2914. Warning: Wire user_proj_conv.\wbs_dat_o [30] is used but has no driver.
  2915. Warning: Wire user_proj_conv.\wbs_dat_o [29] is used but has no driver.
  2916. Warning: Wire user_proj_conv.\wbs_dat_o [28] is used but has no driver.
  2917. Warning: Wire user_proj_conv.\wbs_dat_o [27] is used but has no driver.
  2918. Warning: Wire user_proj_conv.\wbs_dat_o [26] is used but has no driver.
  2919. Warning: Wire user_proj_conv.\wbs_dat_o [25] is used but has no driver.
  2920. Warning: Wire user_proj_conv.\wbs_dat_o [24] is used but has no driver.
  2921. Warning: Wire user_proj_conv.\wbs_dat_o [23] is used but has no driver.
  2922. Warning: Wire user_proj_conv.\wbs_dat_o [22] is used but has no driver.
  2923. Warning: Wire user_proj_conv.\wbs_dat_o [21] is used but has no driver.
  2924. Warning: Wire user_proj_conv.\wbs_dat_o [20] is used but has no driver.
  2925. Warning: Wire user_proj_conv.\wbs_dat_o [19] is used but has no driver.
  2926. Warning: Wire user_proj_conv.\wbs_dat_o [18] is used but has no driver.
  2927. Warning: Wire user_proj_conv.\wbs_dat_o [17] is used but has no driver.
  2928. Warning: Wire user_proj_conv.\wbs_dat_o [16] is used but has no driver.
  2929. Warning: Wire user_proj_conv.\wbs_dat_o [15] is used but has no driver.
  2930. Warning: Wire user_proj_conv.\wbs_dat_o [14] is used but has no driver.
  2931. Warning: Wire user_proj_conv.\wbs_dat_o [13] is used but has no driver.
  2932. Warning: Wire user_proj_conv.\wbs_dat_o [12] is used but has no driver.
  2933. Warning: Wire user_proj_conv.\wbs_dat_o [11] is used but has no driver.
  2934. Warning: Wire user_proj_conv.\wbs_dat_o [10] is used but has no driver.
  2935. Warning: Wire user_proj_conv.\wbs_dat_o [9] is used but has no driver.
  2936. Warning: Wire user_proj_conv.\wbs_dat_o [8] is used but has no driver.
  2937. Warning: Wire user_proj_conv.\wbs_dat_o [7] is used but has no driver.
  2938. Warning: Wire user_proj_conv.\wbs_dat_o [6] is used but has no driver.
  2939. Warning: Wire user_proj_conv.\wbs_dat_o [5] is used but has no driver.
  2940. Warning: Wire user_proj_conv.\wbs_dat_o [4] is used but has no driver.
  2941. Warning: Wire user_proj_conv.\wbs_dat_o [3] is used but has no driver.
  2942. Warning: Wire user_proj_conv.\wbs_dat_o [2] is used but has no driver.
  2943. Warning: Wire user_proj_conv.\wbs_dat_o [1] is used but has no driver.
  2944. Warning: Wire user_proj_conv.\wbs_dat_o [0] is used but has no driver.
  2945. Warning: Wire user_proj_conv.\wbs_ack_o is used but has no driver.
  2946. Warning: Wire user_proj_conv.\la_data_out [127] is used but has no driver.
  2947. Warning: Wire user_proj_conv.\la_data_out [126] is used but has no driver.
  2948. Warning: Wire user_proj_conv.\la_data_out [125] is used but has no driver.
  2949. Warning: Wire user_proj_conv.\la_data_out [124] is used but has no driver.
  2950. Warning: Wire user_proj_conv.\la_data_out [123] is used but has no driver.
  2951. Warning: Wire user_proj_conv.\la_data_out [122] is used but has no driver.
  2952. Warning: Wire user_proj_conv.\la_data_out [121] is used but has no driver.
  2953. Warning: Wire user_proj_conv.\la_data_out [120] is used but has no driver.
  2954. Warning: Wire user_proj_conv.\la_data_out [119] is used but has no driver.
  2955. Warning: Wire user_proj_conv.\la_data_out [118] is used but has no driver.
  2956. Warning: Wire user_proj_conv.\la_data_out [117] is used but has no driver.
  2957. Warning: Wire user_proj_conv.\la_data_out [116] is used but has no driver.
  2958. Warning: Wire user_proj_conv.\la_data_out [115] is used but has no driver.
  2959. Warning: Wire user_proj_conv.\la_data_out [114] is used but has no driver.
  2960. Warning: Wire user_proj_conv.\la_data_out [113] is used but has no driver.
  2961. Warning: Wire user_proj_conv.\la_data_out [112] is used but has no driver.
  2962. Warning: Wire user_proj_conv.\la_data_out [111] is used but has no driver.
  2963. Warning: Wire user_proj_conv.\la_data_out [110] is used but has no driver.
  2964. Warning: Wire user_proj_conv.\la_data_out [109] is used but has no driver.
  2965. Warning: Wire user_proj_conv.\la_data_out [108] is used but has no driver.
  2966. Warning: Wire user_proj_conv.\la_data_out [107] is used but has no driver.
  2967. Warning: Wire user_proj_conv.\la_data_out [106] is used but has no driver.
  2968. Warning: Wire user_proj_conv.\la_data_out [105] is used but has no driver.
  2969. Warning: Wire user_proj_conv.\la_data_out [104] is used but has no driver.
  2970. Warning: Wire user_proj_conv.\la_data_out [103] is used but has no driver.
  2971. Warning: Wire user_proj_conv.\la_data_out [102] is used but has no driver.
  2972. Warning: Wire user_proj_conv.\la_data_out [101] is used but has no driver.
  2973. Warning: Wire user_proj_conv.\la_data_out [100] is used but has no driver.
  2974. Warning: Wire user_proj_conv.\la_data_out [99] is used but has no driver.
  2975. Warning: Wire user_proj_conv.\la_data_out [98] is used but has no driver.
  2976. Warning: Wire user_proj_conv.\la_data_out [97] is used but has no driver.
  2977. Warning: Wire user_proj_conv.\la_data_out [96] is used but has no driver.
  2978. Warning: Wire user_proj_conv.\la_data_out [95] is used but has no driver.
  2979. Warning: Wire user_proj_conv.\la_data_out [94] is used but has no driver.
  2980. Warning: Wire user_proj_conv.\la_data_out [93] is used but has no driver.
  2981. Warning: Wire user_proj_conv.\la_data_out [92] is used but has no driver.
  2982. Warning: Wire user_proj_conv.\la_data_out [91] is used but has no driver.
  2983. Warning: Wire user_proj_conv.\la_data_out [90] is used but has no driver.
  2984. Warning: Wire user_proj_conv.\la_data_out [89] is used but has no driver.
  2985. Warning: Wire user_proj_conv.\la_data_out [88] is used but has no driver.
  2986. Warning: Wire user_proj_conv.\la_data_out [87] is used but has no driver.
  2987. Warning: Wire user_proj_conv.\la_data_out [86] is used but has no driver.
  2988. Warning: Wire user_proj_conv.\la_data_out [85] is used but has no driver.
  2989. Warning: Wire user_proj_conv.\la_data_out [84] is used but has no driver.
  2990. Warning: Wire user_proj_conv.\la_data_out [83] is used but has no driver.
  2991. Warning: Wire user_proj_conv.\la_data_out [82] is used but has no driver.
  2992. Warning: Wire user_proj_conv.\la_data_out [81] is used but has no driver.
  2993. Warning: Wire user_proj_conv.\la_data_out [80] is used but has no driver.
  2994. Warning: Wire user_proj_conv.\la_data_out [79] is used but has no driver.
  2995. Warning: Wire user_proj_conv.\la_data_out [78] is used but has no driver.
  2996. Warning: Wire user_proj_conv.\la_data_out [77] is used but has no driver.
  2997. Warning: Wire user_proj_conv.\la_data_out [76] is used but has no driver.
  2998. Warning: Wire user_proj_conv.\la_data_out [75] is used but has no driver.
  2999. Warning: Wire user_proj_conv.\la_data_out [74] is used but has no driver.
  3000. Warning: Wire user_proj_conv.\la_data_out [73] is used but has no driver.
  3001. Warning: Wire user_proj_conv.\la_data_out [72] is used but has no driver.
  3002. Warning: Wire user_proj_conv.\la_data_out [71] is used but has no driver.
  3003. Warning: Wire user_proj_conv.\la_data_out [70] is used but has no driver.
  3004. Warning: Wire user_proj_conv.\la_data_out [69] is used but has no driver.
  3005. Warning: Wire user_proj_conv.\la_data_out [68] is used but has no driver.
  3006. Warning: Wire user_proj_conv.\la_data_out [67] is used but has no driver.
  3007. Warning: Wire user_proj_conv.\la_data_out [66] is used but has no driver.
  3008. Warning: Wire user_proj_conv.\la_data_out [65] is used but has no driver.
  3009. Warning: Wire user_proj_conv.\la_data_out [64] is used but has no driver.
  3010. Warning: Wire user_proj_conv.\la_data_out [63] is used but has no driver.
  3011. Warning: Wire user_proj_conv.\la_data_out [62] is used but has no driver.
  3012. Warning: Wire user_proj_conv.\la_data_out [61] is used but has no driver.
  3013. Warning: Wire user_proj_conv.\la_data_out [60] is used but has no driver.
  3014. Warning: Wire user_proj_conv.\la_data_out [59] is used but has no driver.
  3015. Warning: Wire user_proj_conv.\la_data_out [58] is used but has no driver.
  3016. Warning: Wire user_proj_conv.\la_data_out [57] is used but has no driver.
  3017. Warning: Wire user_proj_conv.\la_data_out [56] is used but has no driver.
  3018. Warning: Wire user_proj_conv.\la_data_out [55] is used but has no driver.
  3019. Warning: Wire user_proj_conv.\la_data_out [54] is used but has no driver.
  3020. Warning: Wire user_proj_conv.\la_data_out [53] is used but has no driver.
  3021. Warning: Wire user_proj_conv.\la_data_out [52] is used but has no driver.
  3022. Warning: Wire user_proj_conv.\la_data_out [51] is used but has no driver.
  3023. Warning: Wire user_proj_conv.\la_data_out [50] is used but has no driver.
  3024. Warning: Wire user_proj_conv.\la_data_out [49] is used but has no driver.
  3025. Warning: Wire user_proj_conv.\la_data_out [48] is used but has no driver.
  3026. Warning: Wire user_proj_conv.\la_data_out [47] is used but has no driver.
  3027. Warning: Wire user_proj_conv.\la_data_out [46] is used but has no driver.
  3028. Warning: Wire user_proj_conv.\la_data_out [45] is used but has no driver.
  3029. Warning: Wire user_proj_conv.\la_data_out [44] is used but has no driver.
  3030. Warning: Wire user_proj_conv.\la_data_out [43] is used but has no driver.
  3031. Warning: Wire user_proj_conv.\la_data_out [42] is used but has no driver.
  3032. Warning: Wire user_proj_conv.\la_data_out [41] is used but has no driver.
  3033. Warning: Wire user_proj_conv.\la_data_out [40] is used but has no driver.
  3034. Warning: Wire user_proj_conv.\la_data_out [39] is used but has no driver.
  3035. Warning: Wire user_proj_conv.\la_data_out [38] is used but has no driver.
  3036. Warning: Wire user_proj_conv.\la_data_out [37] is used but has no driver.
  3037. Warning: Wire user_proj_conv.\la_data_out [36] is used but has no driver.
  3038. Warning: Wire user_proj_conv.\la_data_out [35] is used but has no driver.
  3039. Warning: Wire user_proj_conv.\la_data_out [34] is used but has no driver.
  3040. Warning: Wire user_proj_conv.\la_data_out [33] is used but has no driver.
  3041. Warning: Wire user_proj_conv.\la_data_out [32] is used but has no driver.
  3042. Warning: Wire user_proj_conv.\la_data_out [31] is used but has no driver.
  3043. Warning: Wire user_proj_conv.\la_data_out [30] is used but has no driver.
  3044. Warning: Wire user_proj_conv.\la_data_out [29] is used but has no driver.
  3045. Warning: Wire user_proj_conv.\la_data_out [28] is used but has no driver.
  3046. Warning: Wire user_proj_conv.\la_data_out [27] is used but has no driver.
  3047. Warning: Wire user_proj_conv.\la_data_out [26] is used but has no driver.
  3048. Warning: Wire user_proj_conv.\la_data_out [25] is used but has no driver.
  3049. Warning: Wire user_proj_conv.\la_data_out [24] is used but has no driver.
  3050. Warning: Wire user_proj_conv.\la_data_out [23] is used but has no driver.
  3051. Warning: Wire user_proj_conv.\la_data_out [22] is used but has no driver.
  3052. Warning: Wire user_proj_conv.\la_data_out [21] is used but has no driver.
  3053. Warning: Wire user_proj_conv.\la_data_out [20] is used but has no driver.
  3054. Warning: Wire user_proj_conv.\la_data_out [19] is used but has no driver.
  3055. Warning: Wire user_proj_conv.\la_data_out [18] is used but has no driver.
  3056. Warning: Wire user_proj_conv.\la_data_out [17] is used but has no driver.
  3057. Warning: Wire user_proj_conv.\la_data_out [16] is used but has no driver.
  3058. Warning: Wire user_proj_conv.\la_data_out [15] is used but has no driver.
  3059. Warning: Wire user_proj_conv.\la_data_out [14] is used but has no driver.
  3060. Warning: Wire user_proj_conv.\la_data_out [13] is used but has no driver.
  3061. Warning: Wire user_proj_conv.\la_data_out [12] is used but has no driver.
  3062. Warning: Wire user_proj_conv.\la_data_out [11] is used but has no driver.
  3063. Warning: Wire user_proj_conv.\la_data_out [10] is used but has no driver.
  3064. Warning: Wire user_proj_conv.\la_data_out [9] is used but has no driver.
  3065. Warning: Wire user_proj_conv.\la_data_out [8] is used but has no driver.
  3066. Warning: Wire user_proj_conv.\la_data_out [7] is used but has no driver.
  3067. Warning: Wire user_proj_conv.\la_data_out [6] is used but has no driver.
  3068. Warning: Wire user_proj_conv.\la_data_out [5] is used but has no driver.
  3069. Warning: Wire user_proj_conv.\la_data_out [4] is used but has no driver.
  3070. Warning: Wire user_proj_conv.\la_data_out [3] is used but has no driver.
  3071. Warning: Wire user_proj_conv.\la_data_out [2] is used but has no driver.
  3072. Warning: Wire user_proj_conv.\la_data_out [1] is used but has no driver.
  3073. Warning: Wire user_proj_conv.\la_data_out [0] is used but has no driver.
  3074. Warning: Wire user_proj_conv.\irq [2] is used but has no driver.
  3075. Warning: Wire user_proj_conv.\irq [1] is used but has no driver.
  3076. Warning: Wire user_proj_conv.\irq [0] is used but has no driver.
  3077. Warning: Wire user_proj_conv.\io_out [28] is used but has no driver.
  3078. Warning: Wire user_proj_conv.\io_out [27] is used but has no driver.
  3079. Warning: Wire user_proj_conv.\io_out [26] is used but has no driver.
  3080. Warning: Wire user_proj_conv.\io_out [25] is used but has no driver.
  3081. Warning: Wire user_proj_conv.\io_out [24] is used but has no driver.
  3082. Warning: Wire user_proj_conv.\io_out [23] is used but has no driver.
  3083. Warning: Wire user_proj_conv.\io_out [22] is used but has no driver.
  3084. Warning: Wire user_proj_conv.\io_out [21] is used but has no driver.
  3085. Warning: Wire user_proj_conv.\io_out [20] is used but has no driver.
  3086. Warning: Wire user_proj_conv.\io_out [19] is used but has no driver.
  3087. Warning: Wire user_proj_conv.\io_out [18] is used but has no driver.
  3088. Warning: Wire user_proj_conv.\io_out [17] is used but has no driver.
  3089. Warning: Wire user_proj_conv.\io_out [16] is used but has no driver.
  3090. Warning: Wire user_proj_conv.\io_out [15] is used but has no driver.
  3091. Warning: Wire user_proj_conv.\io_out [14] is used but has no driver.
  3092. Warning: Wire user_proj_conv.\io_out [13] is used but has no driver.
  3093. Warning: Wire user_proj_conv.\io_out [12] is used but has no driver.
  3094. Warning: Wire user_proj_conv.\io_out [11] is used but has no driver.
  3095. Warning: Wire user_proj_conv.\io_out [10] is used but has no driver.
  3096. Warning: Wire user_proj_conv.\io_out [9] is used but has no driver.
  3097. Warning: Wire user_proj_conv.\io_out [8] is used but has no driver.
  3098. Warning: Wire user_proj_conv.\io_out [7] is used but has no driver.
  3099. Warning: Wire user_proj_conv.\io_out [6] is used but has no driver.
  3100. Warning: Wire user_proj_conv.\io_out [5] is used but has no driver.
  3101. Warning: Wire user_proj_conv.\io_out [4] is used but has no driver.
  3102. Warning: Wire user_proj_conv.\io_out [3] is used but has no driver.
  3103. Warning: Wire user_proj_conv.\io_out [2] is used but has no driver.
  3104. Warning: Wire user_proj_conv.\io_out [1] is used but has no driver.
  3105. Warning: Wire user_proj_conv.\io_out [0] is used but has no driver.
  3106. Warning: Wire user_proj_conv.\io_oeb [36] is used but has no driver.
  3107. Warning: Wire user_proj_conv.\io_oeb [35] is used but has no driver.
  3108. Warning: Wire user_proj_conv.\io_oeb [34] is used but has no driver.
  3109. Warning: Wire user_proj_conv.\io_oeb [33] is used but has no driver.
  3110. Warning: Wire user_proj_conv.\io_oeb [32] is used but has no driver.
  3111. Warning: Wire user_proj_conv.\io_oeb [31] is used but has no driver.
  3112. Warning: Wire user_proj_conv.\io_oeb [30] is used but has no driver.
  3113. Warning: Wire user_proj_conv.\io_oeb [29] is used but has no driver.
  3114. Warning: Wire user_proj_conv.\io_oeb [28] is used but has no driver.
  3115. Warning: Wire user_proj_conv.\io_oeb [27] is used but has no driver.
  3116. Warning: Wire user_proj_conv.\io_oeb [26] is used but has no driver.
  3117. Warning: Wire user_proj_conv.\io_oeb [25] is used but has no driver.
  3118. Warning: Wire user_proj_conv.\io_oeb [24] is used but has no driver.
  3119. Warning: Wire user_proj_conv.\io_oeb [23] is used but has no driver.
  3120. Warning: Wire user_proj_conv.\io_oeb [22] is used but has no driver.
  3121. Warning: Wire user_proj_conv.\io_oeb [21] is used but has no driver.
  3122. Warning: Wire user_proj_conv.\io_oeb [20] is used but has no driver.
  3123. Warning: Wire user_proj_conv.\io_oeb [19] is used but has no driver.
  3124. Warning: Wire user_proj_conv.\io_oeb [18] is used but has no driver.
  3125. Warning: Wire user_proj_conv.\io_oeb [17] is used but has no driver.
  3126. Warning: Wire user_proj_conv.\io_oeb [16] is used but has no driver.
  3127. Warning: Wire user_proj_conv.\io_oeb [15] is used but has no driver.
  3128. Warning: Wire user_proj_conv.\io_oeb [14] is used but has no driver.
  3129. Warning: Wire user_proj_conv.\io_oeb [13] is used but has no driver.
  3130. Warning: Wire user_proj_conv.\io_oeb [12] is used but has no driver.
  3131. Warning: Wire user_proj_conv.\io_oeb [11] is used but has no driver.
  3132. Warning: Wire user_proj_conv.\io_oeb [10] is used but has no driver.
  3133. Warning: Wire user_proj_conv.\io_oeb [9] is used but has no driver.
  3134. Warning: Wire user_proj_conv.\io_oeb [8] is used but has no driver.
  3135. Warning: Wire user_proj_conv.\io_oeb [7] is used but has no driver.
  3136. Warning: Wire user_proj_conv.\io_oeb [6] is used but has no driver.
  3137. Warning: Wire user_proj_conv.\io_oeb [5] is used but has no driver.
  3138. Warning: Wire user_proj_conv.\io_oeb [4] is used but has no driver.
  3139. Warning: Wire user_proj_conv.\io_oeb [3] is used but has no driver.
  3140. Warning: Wire user_proj_conv.\io_oeb [2] is used but has no driver.
  3141. Warning: Wire user_proj_conv.\io_oeb [1] is used but has no driver.
  3142. Warning: Wire user_proj_conv.\io_oeb [0] is used but has no driver.
  3143. Warning: Wire user_proj_conv.\io_oeb [37] is used but has no driver.
  3144. Warning: Wire user_proj_conv.\clk is used but has no driver.
  3145. found and reported 262 problems.
  3146.  
  3147. 29. Printing statistics.
  3148.  
  3149. === $paramod\convolve\BITS=9 ===
  3150.  
  3151. Number of wires: 28
  3152. Number of wire bits: 52
  3153. Number of public wires: 27
  3154. Number of public wire bits: 51
  3155. Number of memories: 0
  3156. Number of memory bits: 0
  3157. Number of processes: 0
  3158. Number of cells: 4
  3159. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  3160. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  3161. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  3162. sky130_fd_sc_hd__and2_2 1
  3163.  
  3164. Area for cell type $paramod\multiplier\BITS=9\KERNEL_SIZE=1 is unknown!
  3165. Area for cell type $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 is unknown!
  3166. Area for cell type $paramod\shift_register\BITS=9\KERNEL_SIZE=1 is unknown!
  3167.  
  3168. Chip area for module '$paramod\convolve\BITS=9': 7.507200
  3169.  
  3170. === $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 ===
  3171.  
  3172. Number of wires: 30
  3173. Number of wire bits: 46
  3174. Number of public wires: 10
  3175. Number of public wire bits: 26
  3176. Number of memories: 0
  3177. Number of memory bits: 0
  3178. Number of processes: 0
  3179. Number of cells: 34
  3180. sky130_fd_sc_hd__a21oi_2 1
  3181. sky130_fd_sc_hd__a22o_2 9
  3182. sky130_fd_sc_hd__and2_2 3
  3183. sky130_fd_sc_hd__buf_1 2
  3184. sky130_fd_sc_hd__dfxtp_2 13
  3185. sky130_fd_sc_hd__inv_2 2
  3186. sky130_fd_sc_hd__nor3_2 1
  3187. sky130_fd_sc_hd__nor4_2 1
  3188. sky130_fd_sc_hd__o21a_2 1
  3189. sky130_fd_sc_hd__or4b_2 1
  3190.  
  3191. Chip area for module '$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1': 454.185600
  3192.  
  3193. === $paramod\multiplier\BITS=9\KERNEL_SIZE=1 ===
  3194.  
  3195. Number of wires: 410
  3196. Number of wire bits: 434
  3197. Number of public wires: 5
  3198. Number of public wire bits: 29
  3199. Number of memories: 0
  3200. Number of memory bits: 0
  3201. Number of processes: 0
  3202. Number of cells: 414
  3203. sky130_fd_sc_hd__a21bo_2 11
  3204. sky130_fd_sc_hd__a21boi_2 3
  3205. sky130_fd_sc_hd__a21o_2 2
  3206. sky130_fd_sc_hd__a21oi_2 4
  3207. sky130_fd_sc_hd__a221o_2 1
  3208. sky130_fd_sc_hd__a22o_2 2
  3209. sky130_fd_sc_hd__a2bb2o_2 82
  3210. sky130_fd_sc_hd__a2bb2oi_2 6
  3211. sky130_fd_sc_hd__a32o_2 2
  3212. sky130_fd_sc_hd__and2_2 3
  3213. sky130_fd_sc_hd__and2b_2 1
  3214. sky130_fd_sc_hd__and4_2 20
  3215. sky130_fd_sc_hd__buf_1 44
  3216. sky130_fd_sc_hd__dfxtp_2 9
  3217. sky130_fd_sc_hd__inv_2 29
  3218. sky130_fd_sc_hd__nand2_2 3
  3219. sky130_fd_sc_hd__nor2_2 10
  3220. sky130_fd_sc_hd__nor3_2 1
  3221. sky130_fd_sc_hd__o2111a_2 1
  3222. sky130_fd_sc_hd__o211a_2 1
  3223. sky130_fd_sc_hd__o21a_2 8
  3224. sky130_fd_sc_hd__o21ai_2 4
  3225. sky130_fd_sc_hd__o21ba_2 19
  3226. sky130_fd_sc_hd__o221a_2 1
  3227. sky130_fd_sc_hd__o22a_2 57
  3228. sky130_fd_sc_hd__o22ai_2 1
  3229. sky130_fd_sc_hd__o2bb2a_2 3
  3230. sky130_fd_sc_hd__o31a_2 1
  3231. sky130_fd_sc_hd__o41a_2 1
  3232. sky130_fd_sc_hd__or2_2 70
  3233. sky130_fd_sc_hd__or2b_2 5
  3234. sky130_fd_sc_hd__or3_2 3
  3235. sky130_fd_sc_hd__or3b_2 1
  3236. sky130_fd_sc_hd__or4_2 5
  3237.  
  3238. Chip area for module '$paramod\multiplier\BITS=9\KERNEL_SIZE=1': 3577.180800
  3239.  
  3240. === $paramod\shift_register\BITS=9\KERNEL_SIZE=1 ===
  3241.  
  3242. Number of wires: 151
  3243. Number of wire bits: 167
  3244. Number of public wires: 38
  3245. Number of public wire bits: 54
  3246. Number of memories: 0
  3247. Number of memory bits: 0
  3248. Number of processes: 0
  3249. Number of cells: 155
  3250. sky130_fd_sc_hd__a211oi_2 2
  3251. sky130_fd_sc_hd__buf_1 6
  3252. sky130_fd_sc_hd__conb_1 9
  3253. sky130_fd_sc_hd__dfxtp_2 32
  3254. sky130_fd_sc_hd__inv_2 33
  3255. sky130_fd_sc_hd__nand2_2 27
  3256. sky130_fd_sc_hd__nor2_2 2
  3257. sky130_fd_sc_hd__nor3_2 1
  3258. sky130_fd_sc_hd__o211a_2 27
  3259. sky130_fd_sc_hd__o21a_2 2
  3260. sky130_fd_sc_hd__o221a_2 2
  3261. sky130_fd_sc_hd__or2_2 1
  3262. sky130_fd_sc_hd__or4_2 11
  3263.  
  3264. Chip area for module '$paramod\shift_register\BITS=9\KERNEL_SIZE=1': 1490.179200
  3265.  
  3266. === user_proj_conv ===
  3267.  
  3268. Number of wires: 18
  3269. Number of wire bits: 608
  3270. Number of public wires: 18
  3271. Number of public wire bits: 608
  3272. Number of memories: 0
  3273. Number of memory bits: 0
  3274. Number of processes: 0
  3275. Number of cells: 233
  3276. $paramod\convolve\BITS=9 1
  3277. sky130_fd_sc_hd__buf_2 26
  3278. sky130_fd_sc_hd__conb_1 204
  3279. sky130_fd_sc_hd__mux2_1 2
  3280.  
  3281. Area for cell type $paramod\convolve\BITS=9 is unknown!
  3282.  
  3283. Chip area for module '\user_proj_conv': 918.380800
  3284.  
  3285. === design hierarchy ===
  3286.  
  3287. user_proj_conv 1
  3288. $paramod\convolve\BITS=9 1
  3289. $paramod\kernel_mem\BITS=9\KERNEL_SIZE=1 1
  3290. $paramod\multiplier\BITS=9\KERNEL_SIZE=1 1
  3291. $paramod\shift_register\BITS=9\KERNEL_SIZE=1 1
  3292.  
  3293. Number of wires: 637
  3294. Number of wire bits: 1307
  3295. Number of public wires: 98
  3296. Number of public wire bits: 768
  3297. Number of memories: 0
  3298. Number of memory bits: 0
  3299. Number of processes: 0
  3300. Number of cells: 836
  3301. sky130_fd_sc_hd__a211oi_2 2
  3302. sky130_fd_sc_hd__a21bo_2 11
  3303. sky130_fd_sc_hd__a21boi_2 3
  3304. sky130_fd_sc_hd__a21o_2 2
  3305. sky130_fd_sc_hd__a21oi_2 5
  3306. sky130_fd_sc_hd__a221o_2 1
  3307. sky130_fd_sc_hd__a22o_2 11
  3308. sky130_fd_sc_hd__a2bb2o_2 82
  3309. sky130_fd_sc_hd__a2bb2oi_2 6
  3310. sky130_fd_sc_hd__a32o_2 2
  3311. sky130_fd_sc_hd__and2_2 7
  3312. sky130_fd_sc_hd__and2b_2 1
  3313. sky130_fd_sc_hd__and4_2 20
  3314. sky130_fd_sc_hd__buf_1 52
  3315. sky130_fd_sc_hd__buf_2 26
  3316. sky130_fd_sc_hd__conb_1 213
  3317. sky130_fd_sc_hd__dfxtp_2 54
  3318. sky130_fd_sc_hd__inv_2 64
  3319. sky130_fd_sc_hd__mux2_1 2
  3320. sky130_fd_sc_hd__nand2_2 30
  3321. sky130_fd_sc_hd__nor2_2 12
  3322. sky130_fd_sc_hd__nor3_2 3
  3323. sky130_fd_sc_hd__nor4_2 1
  3324. sky130_fd_sc_hd__o2111a_2 1
  3325. sky130_fd_sc_hd__o211a_2 28
  3326. sky130_fd_sc_hd__o21a_2 11
  3327. sky130_fd_sc_hd__o21ai_2 4
  3328. sky130_fd_sc_hd__o21ba_2 19
  3329. sky130_fd_sc_hd__o221a_2 3
  3330. sky130_fd_sc_hd__o22a_2 57
  3331. sky130_fd_sc_hd__o22ai_2 1
  3332. sky130_fd_sc_hd__o2bb2a_2 3
  3333. sky130_fd_sc_hd__o31a_2 1
  3334. sky130_fd_sc_hd__o41a_2 1
  3335. sky130_fd_sc_hd__or2_2 71
  3336. sky130_fd_sc_hd__or2b_2 5
  3337. sky130_fd_sc_hd__or3_2 3
  3338. sky130_fd_sc_hd__or3b_2 1
  3339. sky130_fd_sc_hd__or4_2 16
  3340. sky130_fd_sc_hd__or4b_2 1
  3341.  
  3342. Chip area for top module '\user_proj_conv': 6447.433600
  3343.  
  3344. 30. Executing Verilog backend.
  3345. Dumping module `$paramod\convolve\BITS=9'.
  3346. Dumping module `$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  3347. Dumping module `$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  3348. Dumping module `$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  3349. Dumping module `\user_proj_conv'.
  3350.  
  3351. 31. Executing Liberty frontend.
  3352. Imported 428 cell types from liberty file.
  3353.  
  3354. 32. Executing Verilog-2005 frontend: /project/openlane/user_proj_conv/runs/user_proj_conv/results/synthesis/user_proj_conv.synthesis.v
  3355. Parsing SystemVerilog input from `/project/openlane/user_proj_conv/runs/user_proj_conv/results/synthesis/user_proj_conv.synthesis.v' to AST representation.
  3356. Generating RTLIL representation for module `\$paramod\convolve\BITS=9'.
  3357. Generating RTLIL representation for module `\$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1'.
  3358. Generating RTLIL representation for module `\$paramod\multiplier\BITS=9\KERNEL_SIZE=1'.
  3359. Generating RTLIL representation for module `\$paramod\shift_register\BITS=9\KERNEL_SIZE=1'.
  3360. Generating RTLIL representation for module `\user_proj_conv'.
  3361. Successfully finished Verilog frontend.
  3362.  
  3363. 33. Executing SYNTH pass.
  3364.  
  3365. 33.1. Executing HIERARCHY pass (managing design hierarchy).
  3366.  
  3367. 33.1.1. Analyzing design hierarchy..
  3368. Top module: \user_proj_conv
  3369. Used module: \$paramod\convolve\BITS=9
  3370. Used module: \$paramod\shift_register\BITS=9\KERNEL_SIZE=1
  3371. Used module: \$paramod\multiplier\BITS=9\KERNEL_SIZE=1
  3372. Used module: \$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  3373.  
  3374. 33.1.2. Analyzing design hierarchy..
  3375. Top module: \user_proj_conv
  3376. Used module: \$paramod\convolve\BITS=9
  3377. Used module: \$paramod\shift_register\BITS=9\KERNEL_SIZE=1
  3378. Used module: \$paramod\multiplier\BITS=9\KERNEL_SIZE=1
  3379. Used module: \$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1
  3380. Removed 0 unused modules.
  3381.  
  3382. 33.2. Executing PROC pass (convert processes to netlists).
  3383.  
  3384. 33.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
  3385. Cleaned up 0 empty switches.
  3386.  
  3387. 33.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
  3388. Removed a total of 0 dead cases.
  3389.  
  3390. 33.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
  3391. Removed 0 redundant assignments.
  3392. Promoted 0 assignments to connections.
  3393.  
  3394. 33.2.4. Executing PROC_INIT pass (extract init attributes).
  3395.  
  3396. 33.2.5. Executing PROC_ARST pass (detect async resets in processes).
  3397.  
  3398. 33.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
  3399.  
  3400. 33.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
  3401.  
  3402. 33.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
  3403.  
  3404. 33.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
  3405. Cleaned up 0 empty switches.
  3406.  
  3407. 33.3. Executing FLATTEN pass (flatten design).
  3408. Deleting now unused module \$paramod\shift_register\BITS=9\KERNEL_SIZE=1.
  3409. Deleting now unused module \$paramod\multiplier\BITS=9\KERNEL_SIZE=1.
  3410. Deleting now unused module \$paramod\kernel_mem\BITS=9\KERNEL_SIZE=1.
  3411. Deleting now unused module \$paramod\convolve\BITS=9.
  3412. <suppressed ~4 debug messages>
  3413.  
  3414. 33.4. Executing OPT_EXPR pass (perform const folding).
  3415. Optimizing module user_proj_conv.
  3416.  
  3417. 33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
  3418. Finding unused cells or wires in module \user_proj_conv..
  3419.  
  3420. 33.6. Executing CHECK pass (checking for obvious problems).
  3421. checking module user_proj_conv..
  3422. found and reported 0 problems.
  3423.  
  3424. 33.7. Executing OPT pass (performing simple optimizations).
  3425.  
  3426. 33.7.1. Executing OPT_EXPR pass (perform const folding).
  3427. Optimizing module user_proj_conv.
  3428.  
  3429. 33.7.2. Executing OPT_MERGE pass (detect identical cells).
  3430. Finding identical cells in module `\user_proj_conv'.
  3431. Removed a total of 0 cells.
  3432.  
  3433. 33.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  3434. Running muxtree optimizer on module \user_proj_conv..
  3435. Creating internal representation of mux trees.
  3436. No muxes found in this module.
  3437. Removed 0 multiplexer ports.
  3438.  
  3439. 33.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  3440. Optimizing cells in module \user_proj_conv.
  3441. Performed a total of 0 changes.
  3442.  
  3443. 33.7.5. Executing OPT_MERGE pass (detect identical cells).
  3444. Finding identical cells in module `\user_proj_conv'.
  3445. Removed a total of 0 cells.
  3446.  
  3447. 33.7.6. Executing OPT_DFF pass (perform DFF optimizations).
  3448.  
  3449. 33.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  3450. Finding unused cells or wires in module \user_proj_conv..
  3451.  
  3452. 33.7.8. Executing OPT_EXPR pass (perform const folding).
  3453. Optimizing module user_proj_conv.
  3454.  
  3455. 33.7.9. Finished OPT passes. (There is nothing left to do.)
  3456.  
  3457. 33.8. Executing FSM pass (extract and optimize FSM).
  3458.  
  3459. 33.8.1. Executing FSM_DETECT pass (finding FSMs in design).
  3460.  
  3461. 33.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
  3462.  
  3463. 33.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
  3464.  
  3465. 33.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  3466. Finding unused cells or wires in module \user_proj_conv..
  3467.  
  3468. 33.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
  3469.  
  3470. 33.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
  3471.  
  3472. 33.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
  3473.  
  3474. 33.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
  3475.  
  3476. 33.9. Executing OPT pass (performing simple optimizations).
  3477.  
  3478. 33.9.1. Executing OPT_EXPR pass (perform const folding).
  3479. Optimizing module user_proj_conv.
  3480.  
  3481. 33.9.2. Executing OPT_MERGE pass (detect identical cells).
  3482. Finding identical cells in module `\user_proj_conv'.
  3483. Removed a total of 0 cells.
  3484.  
  3485. 33.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  3486. Running muxtree optimizer on module \user_proj_conv..
  3487. Creating internal representation of mux trees.
  3488. No muxes found in this module.
  3489. Removed 0 multiplexer ports.
  3490.  
  3491. 33.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  3492. Optimizing cells in module \user_proj_conv.
  3493. Performed a total of 0 changes.
  3494.  
  3495. 33.9.5. Executing OPT_MERGE pass (detect identical cells).
  3496. Finding identical cells in module `\user_proj_conv'.
  3497. Removed a total of 0 cells.
  3498.  
  3499. 33.9.6. Executing OPT_DFF pass (perform DFF optimizations).
  3500.  
  3501. 33.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  3502. Finding unused cells or wires in module \user_proj_conv..
  3503.  
  3504. 33.9.8. Executing OPT_EXPR pass (perform const folding).
  3505. Optimizing module user_proj_conv.
  3506.  
  3507. 33.9.9. Finished OPT passes. (There is nothing left to do.)
  3508.  
  3509. 33.10. Executing WREDUCE pass (reducing word size of cells).
  3510.  
  3511. 33.11. Executing PEEPOPT pass (run peephole optimizers).
  3512.  
  3513. 33.12. Executing OPT_CLEAN pass (remove unused cells and wires).
  3514. Finding unused cells or wires in module \user_proj_conv..
  3515.  
  3516. 33.13. Executing ALUMACC pass (create $alu and $macc cells).
  3517. Extracting $alu and $macc cells in module user_proj_conv:
  3518. created 0 $alu and 0 $macc cells.
  3519.  
  3520. 33.14. Executing SHARE pass (SAT-based resource sharing).
  3521.  
  3522. 33.15. Executing OPT pass (performing simple optimizations).
  3523.  
  3524. 33.15.1. Executing OPT_EXPR pass (perform const folding).
  3525. Optimizing module user_proj_conv.
  3526.  
  3527. 33.15.2. Executing OPT_MERGE pass (detect identical cells).
  3528. Finding identical cells in module `\user_proj_conv'.
  3529. Removed a total of 0 cells.
  3530.  
  3531. 33.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  3532. Running muxtree optimizer on module \user_proj_conv..
  3533. Creating internal representation of mux trees.
  3534. No muxes found in this module.
  3535. Removed 0 multiplexer ports.
  3536.  
  3537. 33.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  3538. Optimizing cells in module \user_proj_conv.
  3539. Performed a total of 0 changes.
  3540.  
  3541. 33.15.5. Executing OPT_MERGE pass (detect identical cells).
  3542. Finding identical cells in module `\user_proj_conv'.
  3543. Removed a total of 0 cells.
  3544.  
  3545. 33.15.6. Executing OPT_DFF pass (perform DFF optimizations).
  3546.  
  3547. 33.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  3548. Finding unused cells or wires in module \user_proj_conv..
  3549.  
  3550. 33.15.8. Executing OPT_EXPR pass (perform const folding).
  3551. Optimizing module user_proj_conv.
  3552.  
  3553. 33.15.9. Finished OPT passes. (There is nothing left to do.)
  3554.  
  3555. 33.16. Executing MEMORY pass.
  3556.  
  3557. 33.16.1. Executing OPT_MEM pass (optimize memories).
  3558. Performed a total of 0 transformations.
  3559.  
  3560. 33.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
  3561.  
  3562. 33.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
  3563. Finding unused cells or wires in module \user_proj_conv..
  3564.  
  3565. 33.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
  3566.  
  3567. 33.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
  3568. Finding unused cells or wires in module \user_proj_conv..
  3569.  
  3570. 33.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
  3571.  
  3572. 33.17. Executing OPT_CLEAN pass (remove unused cells and wires).
  3573. Finding unused cells or wires in module \user_proj_conv..
  3574.  
  3575. 33.18. Executing OPT pass (performing simple optimizations).
  3576.  
  3577. 33.18.1. Executing OPT_EXPR pass (perform const folding).
  3578. Optimizing module user_proj_conv.
  3579.  
  3580. 33.18.2. Executing OPT_MERGE pass (detect identical cells).
  3581. Finding identical cells in module `\user_proj_conv'.
  3582. Removed a total of 0 cells.
  3583.  
  3584. 33.18.3. Executing OPT_DFF pass (perform DFF optimizations).
  3585.  
  3586. 33.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  3587. Finding unused cells or wires in module \user_proj_conv..
  3588.  
  3589. 33.18.5. Finished fast OPT passes.
  3590.  
  3591. 33.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
  3592.  
  3593. 33.20. Executing OPT pass (performing simple optimizations).
  3594.  
  3595. 33.20.1. Executing OPT_EXPR pass (perform const folding).
  3596. Optimizing module user_proj_conv.
  3597.  
  3598. 33.20.2. Executing OPT_MERGE pass (detect identical cells).
  3599. Finding identical cells in module `\user_proj_conv'.
  3600. Removed a total of 0 cells.
  3601.  
  3602. 33.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  3603. Running muxtree optimizer on module \user_proj_conv..
  3604. Creating internal representation of mux trees.
  3605. No muxes found in this module.
  3606. Removed 0 multiplexer ports.
  3607.  
  3608. 33.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  3609. Optimizing cells in module \user_proj_conv.
  3610. Performed a total of 0 changes.
  3611.  
  3612. 33.20.5. Executing OPT_MERGE pass (detect identical cells).
  3613. Finding identical cells in module `\user_proj_conv'.
  3614. Removed a total of 0 cells.
  3615.  
  3616. 33.20.6. Executing OPT_SHARE pass.
  3617.  
  3618. 33.20.7. Executing OPT_DFF pass (perform DFF optimizations).
  3619.  
  3620. 33.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
  3621. Finding unused cells or wires in module \user_proj_conv..
  3622.  
  3623. 33.20.9. Executing OPT_EXPR pass (perform const folding).
  3624. Optimizing module user_proj_conv.
  3625.  
  3626. 33.20.10. Finished OPT passes. (There is nothing left to do.)
  3627.  
  3628. 33.21. Executing TECHMAP pass (map to technology primitives).
  3629.  
  3630. 33.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
  3631. Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
  3632. Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
  3633. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
  3634. Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
  3635. Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
  3636. Generating RTLIL representation for module `\_90_simplemap_various'.
  3637. Generating RTLIL representation for module `\_90_simplemap_registers'.
  3638. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
  3639. Generating RTLIL representation for module `\_90_shift_shiftx'.
  3640. Generating RTLIL representation for module `\_90_fa'.
  3641. Generating RTLIL representation for module `\_90_lcu'.
  3642. Generating RTLIL representation for module `\_90_alu'.
  3643. Generating RTLIL representation for module `\_90_macc'.
  3644. Generating RTLIL representation for module `\_90_alumacc'.
  3645. Generating RTLIL representation for module `\$__div_mod_u'.
  3646. Generating RTLIL representation for module `\$__div_mod_trunc'.
  3647. Generating RTLIL representation for module `\_90_div'.
  3648. Generating RTLIL representation for module `\_90_mod'.
  3649. Generating RTLIL representation for module `\$__div_mod_floor'.
  3650. Generating RTLIL representation for module `\_90_divfloor'.
  3651. Generating RTLIL representation for module `\_90_modfloor'.
  3652. Generating RTLIL representation for module `\_90_pow'.
  3653. Generating RTLIL representation for module `\_90_pmux'.
  3654. Generating RTLIL representation for module `\_90_lut'.
  3655. Successfully finished Verilog frontend.
  3656.  
  3657. 33.21.2. Continuing TECHMAP pass.
  3658. No more expansions possible.
  3659. <suppressed ~67 debug messages>
  3660.  
  3661. 33.22. Executing OPT pass (performing simple optimizations).
  3662.  
  3663. 33.22.1. Executing OPT_EXPR pass (perform const folding).
  3664. Optimizing module user_proj_conv.
  3665.  
  3666. 33.22.2. Executing OPT_MERGE pass (detect identical cells).
  3667. Finding identical cells in module `\user_proj_conv'.
  3668. Removed a total of 0 cells.
  3669.  
  3670. 33.22.3. Executing OPT_DFF pass (perform DFF optimizations).
  3671.  
  3672. 33.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  3673. Finding unused cells or wires in module \user_proj_conv..
  3674.  
  3675. 33.22.5. Finished fast OPT passes.
  3676.  
  3677. 33.23. Executing ABC pass (technology mapping using ABC).
  3678.  
  3679. 33.23.1. Extracting gate netlist of module `\user_proj_conv' to `<abc-temp-dir>/input.blif'..
  3680. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
  3681. Don't call ABC as there is nothing to map.
  3682. Removing temp directory.
  3683.  
  3684. 33.24. Executing OPT pass (performing simple optimizations).
  3685.  
  3686. 33.24.1. Executing OPT_EXPR pass (perform const folding).
  3687. Optimizing module user_proj_conv.
  3688.  
  3689. 33.24.2. Executing OPT_MERGE pass (detect identical cells).
  3690. Finding identical cells in module `\user_proj_conv'.
  3691. Removed a total of 0 cells.
  3692.  
  3693. 33.24.3. Executing OPT_DFF pass (perform DFF optimizations).
  3694.  
  3695. 33.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  3696. Finding unused cells or wires in module \user_proj_conv..
  3697.  
  3698. 33.24.5. Finished fast OPT passes.
  3699.  
  3700. 33.25. Executing HIERARCHY pass (managing design hierarchy).
  3701.  
  3702. 33.25.1. Analyzing design hierarchy..
  3703. Top module: \user_proj_conv
  3704.  
  3705. 33.25.2. Analyzing design hierarchy..
  3706. Top module: \user_proj_conv
  3707. Removed 0 unused modules.
  3708.  
  3709. 33.26. Printing statistics.
  3710.  
  3711. === user_proj_conv ===
  3712.  
  3713. Number of wires: 637
  3714. Number of wire bits: 1307
  3715. Number of public wires: 637
  3716. Number of public wire bits: 1307
  3717. Number of memories: 0
  3718. Number of memory bits: 0
  3719. Number of processes: 0
  3720. Number of cells: 836
  3721. sky130_fd_sc_hd__a211oi_2 2
  3722. sky130_fd_sc_hd__a21bo_2 11
  3723. sky130_fd_sc_hd__a21boi_2 3
  3724. sky130_fd_sc_hd__a21o_2 2
  3725. sky130_fd_sc_hd__a21oi_2 5
  3726. sky130_fd_sc_hd__a221o_2 1
  3727. sky130_fd_sc_hd__a22o_2 11
  3728. sky130_fd_sc_hd__a2bb2o_2 82
  3729. sky130_fd_sc_hd__a2bb2oi_2 6
  3730. sky130_fd_sc_hd__a32o_2 2
  3731. sky130_fd_sc_hd__and2_2 7
  3732. sky130_fd_sc_hd__and2b_2 1
  3733. sky130_fd_sc_hd__and4_2 20
  3734. sky130_fd_sc_hd__buf_1 52
  3735. sky130_fd_sc_hd__buf_2 26
  3736. sky130_fd_sc_hd__conb_1 213
  3737. sky130_fd_sc_hd__dfxtp_2 54
  3738. sky130_fd_sc_hd__inv_2 64
  3739. sky130_fd_sc_hd__mux2_1 2
  3740. sky130_fd_sc_hd__nand2_2 30
  3741. sky130_fd_sc_hd__nor2_2 12
  3742. sky130_fd_sc_hd__nor3_2 3
  3743. sky130_fd_sc_hd__nor4_2 1
  3744. sky130_fd_sc_hd__o2111a_2 1
  3745. sky130_fd_sc_hd__o211a_2 28
  3746. sky130_fd_sc_hd__o21a_2 11
  3747. sky130_fd_sc_hd__o21ai_2 4
  3748. sky130_fd_sc_hd__o21ba_2 19
  3749. sky130_fd_sc_hd__o221a_2 3
  3750. sky130_fd_sc_hd__o22a_2 57
  3751. sky130_fd_sc_hd__o22ai_2 1
  3752. sky130_fd_sc_hd__o2bb2a_2 3
  3753. sky130_fd_sc_hd__o31a_2 1
  3754. sky130_fd_sc_hd__o41a_2 1
  3755. sky130_fd_sc_hd__or2_2 71
  3756. sky130_fd_sc_hd__or2b_2 5
  3757. sky130_fd_sc_hd__or3_2 3
  3758. sky130_fd_sc_hd__or3b_2 1
  3759. sky130_fd_sc_hd__or4_2 16
  3760. sky130_fd_sc_hd__or4b_2 1
  3761.  
  3762. 33.27. Executing CHECK pass (checking for obvious problems).
  3763. checking module user_proj_conv..
  3764. found and reported 0 problems.
  3765.  
  3766. 34. Executing SPLITNETS pass (splitting up multi-bit signals).
  3767.  
  3768. 35. Executing OPT_CLEAN pass (remove unused cells and wires).
  3769. Finding unused cells or wires in module \user_proj_conv..
  3770. Removed 0 unused cells and 94 unused wires.
  3771. <suppressed ~94 debug messages>
  3772.  
  3773. 36. Executing INSBUF pass (insert buffer cells for connected wires).
  3774. Added user_proj_conv.$auto$insbuf.cc:79:execute$4364: \U1.kernel_mem.reset -> \io_oeb [37]
  3775. Added user_proj_conv.$auto$insbuf.cc:79:execute$4365: \U1.img_output[0] -> \io_out [29]
  3776. Added user_proj_conv.$auto$insbuf.cc:79:execute$4366: \U1.img_output[1] -> \io_out [30]
  3777. Added user_proj_conv.$auto$insbuf.cc:79:execute$4367: \U1.img_output[2] -> \io_out [31]
  3778. Added user_proj_conv.$auto$insbuf.cc:79:execute$4368: \U1.img_output[3] -> \io_out [32]
  3779. Added user_proj_conv.$auto$insbuf.cc:79:execute$4369: \U1.img_output[4] -> \io_out [33]
  3780. Added user_proj_conv.$auto$insbuf.cc:79:execute$4370: \U1.img_output[5] -> \io_out [34]
  3781. Added user_proj_conv.$auto$insbuf.cc:79:execute$4371: \U1.img_output[6] -> \io_out [35]
  3782. Added user_proj_conv.$auto$insbuf.cc:79:execute$4372: \U1.img_output[7] -> \io_out [36]
  3783. Added user_proj_conv.$auto$insbuf.cc:79:execute$4373: \U1.img_output[8] -> \io_out [37]
  3784.  
  3785. 37. Executing Verilog backend.
  3786. Dumping module `\user_proj_conv'.
  3787.  
  3788. 38. Executing CHECK pass (checking for obvious problems).
  3789. checking module user_proj_conv..
  3790. found and reported 0 problems.
  3791.  
  3792. 39. Printing statistics.
  3793.  
  3794. === user_proj_conv ===
  3795.  
  3796. Number of wires: 623
  3797. Number of wire bits: 1213
  3798. Number of public wires: 623
  3799. Number of public wire bits: 1213
  3800. Number of memories: 0
  3801. Number of memory bits: 0
  3802. Number of processes: 0
  3803. Number of cells: 846
  3804. sky130_fd_sc_hd__a211oi_2 2
  3805. sky130_fd_sc_hd__a21bo_2 11
  3806. sky130_fd_sc_hd__a21boi_2 3
  3807. sky130_fd_sc_hd__a21o_2 2
  3808. sky130_fd_sc_hd__a21oi_2 5
  3809. sky130_fd_sc_hd__a221o_2 1
  3810. sky130_fd_sc_hd__a22o_2 11
  3811. sky130_fd_sc_hd__a2bb2o_2 82
  3812. sky130_fd_sc_hd__a2bb2oi_2 6
  3813. sky130_fd_sc_hd__a32o_2 2
  3814. sky130_fd_sc_hd__and2_2 7
  3815. sky130_fd_sc_hd__and2b_2 1
  3816. sky130_fd_sc_hd__and4_2 20
  3817. sky130_fd_sc_hd__buf_1 52
  3818. sky130_fd_sc_hd__buf_2 36
  3819. sky130_fd_sc_hd__conb_1 213
  3820. sky130_fd_sc_hd__dfxtp_2 54
  3821. sky130_fd_sc_hd__inv_2 64
  3822. sky130_fd_sc_hd__mux2_1 2
  3823. sky130_fd_sc_hd__nand2_2 30
  3824. sky130_fd_sc_hd__nor2_2 12
  3825. sky130_fd_sc_hd__nor3_2 3
  3826. sky130_fd_sc_hd__nor4_2 1
  3827. sky130_fd_sc_hd__o2111a_2 1
  3828. sky130_fd_sc_hd__o211a_2 28
  3829. sky130_fd_sc_hd__o21a_2 11
  3830. sky130_fd_sc_hd__o21ai_2 4
  3831. sky130_fd_sc_hd__o21ba_2 19
  3832. sky130_fd_sc_hd__o221a_2 3
  3833. sky130_fd_sc_hd__o22a_2 57
  3834. sky130_fd_sc_hd__o22ai_2 1
  3835. sky130_fd_sc_hd__o2bb2a_2 3
  3836. sky130_fd_sc_hd__o31a_2 1
  3837. sky130_fd_sc_hd__o41a_2 1
  3838. sky130_fd_sc_hd__or2_2 71
  3839. sky130_fd_sc_hd__or2b_2 5
  3840. sky130_fd_sc_hd__or3_2 3
  3841. sky130_fd_sc_hd__or3b_2 1
  3842. sky130_fd_sc_hd__or4_2 16
  3843. sky130_fd_sc_hd__or4b_2 1
  3844.  
  3845. Chip area for module '\user_proj_conv': 6497.481600
  3846.  
  3847. Warnings: 263 unique messages, 273 total
  3848. End of script. Logfile hash: a683a0d0e6, CPU: user 2.95s system 0.04s, MEM: 51.36 MB peak
  3849. Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
  3850. Time spent: 48% 3x abc (2 sec), 11% 6x stat (0 sec), ...
  3851.  
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