Dziala z assign

// File: vga_timing.v
// This is the vga timing design for EE178 Lab #4.

// The `timescale directive specifies what the
// simulation time units are (1 ns here) and what
// the simulator time step should be (1 ps here).

`timescale 1 ns / 1 ps

// Declare the module and its ports. This is
// using Verilog-2001 syntax.

module vga_timing (
  output reg [10:0] vcount,             //zmiana na reg
  output wire vsync,
  output wire vblnk,
  output reg [10:0] hcount,
  output wire hsync,
  output wire hblnk,
  input wire pclk
  );

    reg [10:0] vcount_nxt = 0;
    reg [10:0] hcount_nxt = 0;

    always@(posedge pclk)
        begin
            vcount <= vcount_nxt;
            hcount <= hcount_nxt;
        end

    always @(*)
        begin
                if(hcount < 1055)
                    begin
                        hcount_nxt = hcount + 1;
                        vcount_nxt = vcount;
                    end
                else
                    begin
                        hcount_nxt = 0;
                        if(vcount < 628)
                            vcount_nxt = vcount + 1;
                        else
                            vcount_nxt = 0;
                    end
        end

        assign vblnk = (vcount >= 600);
        assign vsync = (vcount >= 601 && vcount <= 605);
        assign hblnk = (hcount >= 800);
        assign hsync = (hcount >= 840 && hcount <= 968);

  // Describe the actual circuit for the assignment.
  // Video timing controller set for 800x600@60fps
  // using a 40 MHz pixel clock per VESA spec.

endmodule