Verilog Datapath

module dataPath(ia, ib, ic, id, m_, st, rst, total, done, error);
input [7:0] ia;
input [7:0] ib;
input [7:0] ic;
input [7:0] id;
input [0:0] m_;

reg [3:0] d = 0;
wire [3:0] q;
input [0:0] st;
input [0:0] rst;
reg [0:0] clk = 0;


reg [0:0] m = 0;
reg [7:0] a = 0;
reg [7:0] b = 0;
wire [7:0] s;
wire [7:0] c;
wire [0:0] ovf;
wrongEightCLA _cla(m, 0, a, b, s, c, ovf);

output reg [0:0] done = 0;
output reg [0:0] error = 0;
output reg [7:0] total = 0;
ff ff1(d, clk, rst, q);
    always
        #1 clk = ~clk;
    always @ (st)
    begin
        assign d = 0;
        m <= 0;
        a <= 0;
        b <= 0;
        total <= 0;
        done <= 0;
    end
    always @ (rst)
    begin
        error <= 0;
    end
    always
    begin
        #2
        //$display("%d",ovf);
        //if(ovf)
        //  assign error = 1;

        if(!error & !done)
        begin
            case (q)
            0:
            begin
                a <= s;
                b <= ia;
                assign d = q+1;
            end
            1:
            begin
                a <= s;
                b <= ib;
                assign d = q+1;
            end
            2:
            begin
                a <= s;
                b <= ic;
                assign d = q+1;
            end
            3:
            begin
                m <= m_;
                a <= s;
                b <= id;
                assign d = q+1;
            end
            default:
            begin
                total <= s;
                done <= 1;
            end
            endcase
        end
    end

endmodule