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MrRockchip

a88xm-e coreboot getpir

MrRockchip
Dec 6th, 2020 (edited)
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  1. also see "example_3"
  2.  
  3. Accessing memory
  4. Probing PIRQ table in memory.
  5. Found PCI IRQ routing table signature at 0xf0780.
  6. SIGNATURE = $PIR
  7. VERSION = 0100
  8. SIZE = 368
  9. MAX_DEVICES_ON_BUS = 32 + 16 * 21
  10. INT_ROUTER_BUS = 0x00
  11. INT_ROUTER DEVICE = (0x14 << 3) | 0x4
  12. IRQ_DEVOTED_TO_PCI = 0
  13. VENDOR = 0x1022
  14. DEVICE = 0x780b
  15. MINIPORT = 0
  16. CHECKSUM = 0x16
  17. bus , dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
  18. 0x00, (0x00 << 3) | 0x2, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x0, 0x0},
  19. 0x00, (0x01 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
  20. 0x00, (0x02 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x0, 0x0},
  21. 0x00, (0x04 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x0, 0x0},
  22. 0x00, (0x05 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x0, 0x0},
  23. 0x00, (0x06 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0}}, 0x0, 0x0},
  24. 0x00, (0x10 << 3) | 0x0, {{0x03, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
  25. 0x00, (0x11 << 3) | 0x0, {{0x04, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
  26. 0x00, (0x12 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
  27. 0x00, (0x16 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
  28. 0x00, (0x13 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
  29. 0x00, (0x14 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x0, 0x0},
  30. 0x00, (0x14 << 3) | 0x4, {{0x05, 0xccf0}, {0x06, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
  31. 0x00, (0x15 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0}}, 0x0, 0x0},
  32. 0x00, (0x15 << 3) | 0x1, {{0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0}, {0x02, 0xccf0}}, 0x0, 0x0},
  33. 0x00, (0x15 << 3) | 0x2, {{0x04, 0xccf0}, {0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}}, 0x0, 0x0},
  34. 0x00, (0x15 << 3) | 0x3, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x0, 0x0},
  35. 0x01, (0x00 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x1, 0x0},
  36. 0x02, (0x00 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}}, 0x2, 0x0},
  37. 0x03, (0x00 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0}}, 0x3, 0x0},
  38. 0x04, (0x00 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0}}, 0x4, 0x0},
  39. Validating...
  40. CHECKSUM = 0x16
  41. checksum is ok.
  42. Creating irq_tables.c ...
  43. Done, you can move the file to the coreboot tree now.
  44.  
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