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z3ntu

FP2 full downstream dts (compiled)

z3ntu
Oct 12th, 2017
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. model = "Qualcomm MSM 8974Pro-AA/AB MTP";
  7. compatible = "qcom,msm8974-mtp", "qcom,msm8974", "qcom,mtp";
  8. interrupt-parent = <0x1>;
  9. qcom,msm-id = <0xd0 0x10000 0xd1 0x10000 0xd3 0x10000 0xd4 0x10000 0xd6 0x10000 0xd7 0x10000 0xd9 0x10000 0xda 0x10000>;
  10. qcom,board-id = <0x8 0x0>;
  11.  
  12. chosen {
  13. };
  14.  
  15. aliases {
  16. spi0 = "/soc/spi@f9923000";
  17. spi7 = "/soc/spi@f9966000";
  18. sdhc1 = "/soc/sdhci@f9824900";
  19. sdhc2 = "/soc/sdhci@f98a4900";
  20. sdhc3 = "/soc/sdhci@f9864900";
  21. sdhc4 = "/soc/sdhci@f98e4900";
  22. smd1 = "/soc/qcom,smdtty/qcom,smdtty-apps-fm";
  23. smd2 = "/soc/qcom,smdtty/smdtty-apps-riva-bt-acl";
  24. smd3 = "/soc/qcom,smdtty/qcom,smdtty-apps-riva-bt-cmd";
  25. smd4 = "/soc/qcom,smdtty/qcom,smdtty-mbalbridge";
  26. smd5 = "/soc/qcom,smdtty/smdtty-apps-riva-ant-cmd";
  27. smd6 = "/soc/qcom,smdtty/smdtty-apps-riva-ant-data";
  28. smd7 = "/soc/qcom,smdtty/qcom,smdtty-data1";
  29. smd11 = "/soc/qcom,smdtty/qcom,smdtty-data11";
  30. smd21 = "/soc/qcom,smdtty/qcom,smdtty-data21";
  31. smd27 = "/soc/qcom,smdtty/smdtty-gpsnmea";
  32. smd36 = "/soc/qcom,smdtty/smdtty-loopback";
  33. serial0 = "/soc/serial@f991e000";
  34. };
  35.  
  36. memory {
  37. #address-cells = <0x1>;
  38. #size-cells = <0x1>;
  39. device_type = "memory";
  40. reg = <0x0 0x0>;
  41.  
  42. secure_region {
  43. linux,contiguous-region;
  44. reg = <0x0 0xfc00000>;
  45. label = "secure_mem";
  46. linux,phandle = <0x1b>;
  47. phandle = <0x1b>;
  48. };
  49.  
  50. adsp_region {
  51. linux,contiguous-region;
  52. reg = <0x0 0x4100000>;
  53. label = "adsp_mem";
  54. linux,phandle = <0x1c>;
  55. phandle = <0x1c>;
  56. };
  57.  
  58. qsecom_region {
  59. linux,contiguous-region;
  60. reg = <0x0 0x1100000>;
  61. label = "qseecom_mem";
  62. linux,phandle = <0x1d>;
  63. phandle = <0x1d>;
  64. };
  65. };
  66.  
  67. cpus {
  68. #size-cells = <0x0>;
  69. #address-cells = <0x1>;
  70.  
  71. cpu@0 {
  72. device_type = "cpu";
  73. compatible = "qcom,krait";
  74. reg = <0x0>;
  75. };
  76.  
  77. cpu@1 {
  78. device_type = "cpu";
  79. compatible = "qcom,krait";
  80. reg = <0x1>;
  81. };
  82.  
  83. cpu@2 {
  84. device_type = "cpu";
  85. compatible = "qcom,krait";
  86. reg = <0x2>;
  87. };
  88.  
  89. cpu@3 {
  90. device_type = "cpu";
  91. compatible = "qcom,krait";
  92. reg = <0x3>;
  93. };
  94. };
  95.  
  96. soc {
  97. #address-cells = <0x1>;
  98. #size-cells = <0x1>;
  99. ranges;
  100.  
  101. qcom,msm-cam@fd8C0000 {
  102. compatible = "qcom,msm-cam";
  103. reg = <0xfd8c0000 0x10000>;
  104. reg-names = "msm-cam";
  105. };
  106.  
  107. qcom,csiphy@fda0ac00 {
  108. cell-index = <0x0>;
  109. compatible = "qcom,csiphy";
  110. reg = <0xfda0ac00 0x200 0xfda00030 0x4>;
  111. reg-names = "csiphy", "csiphy_clk_mux";
  112. interrupts = <0x0 0x4e 0x0>;
  113. interrupt-names = "csiphy";
  114. };
  115.  
  116. qcom,csiphy@fda0b000 {
  117. cell-index = <0x1>;
  118. compatible = "qcom,csiphy";
  119. reg = <0xfda0b000 0x200 0xfda00038 0x4>;
  120. reg-names = "csiphy", "csiphy_clk_mux";
  121. interrupts = <0x0 0x4f 0x0>;
  122. interrupt-names = "csiphy";
  123. };
  124.  
  125. qcom,csiphy@fda0b400 {
  126. cell-index = <0x2>;
  127. compatible = "qcom,csiphy";
  128. reg = <0xfda0b400 0x200 0xfda00040 0x4>;
  129. reg-names = "csiphy", "csiphy_clk_mux";
  130. interrupts = <0x0 0x50 0x0>;
  131. interrupt-names = "csiphy";
  132. };
  133.  
  134. qcom,csid@fda08000 {
  135. cell-index = <0x0>;
  136. compatible = "qcom,csid";
  137. reg = <0xfda08000 0x100>;
  138. reg-names = "csid";
  139. interrupts = <0x0 0x33 0x0>;
  140. interrupt-names = "csid";
  141. qcom,csi-vdd-voltage = <0x1b7740>;
  142. qcom,mipi-csi-vdd-supply = <0x2>;
  143. };
  144.  
  145. qcom,csid@fda08400 {
  146. cell-index = <0x1>;
  147. compatible = "qcom,csid";
  148. reg = <0xfda08400 0x100>;
  149. reg-names = "csid";
  150. interrupts = <0x0 0x34 0x0>;
  151. interrupt-names = "csid";
  152. qcom,csi-vdd-voltage = <0x1b7740>;
  153. qcom,mipi-csi-vdd-supply = <0x2>;
  154. };
  155.  
  156. qcom,csid@fda08800 {
  157. cell-index = <0x2>;
  158. compatible = "qcom,csid";
  159. reg = <0xfda08800 0x100>;
  160. reg-names = "csid";
  161. interrupts = <0x0 0x35 0x0>;
  162. interrupt-names = "csid";
  163. qcom,csi-vdd-voltage = <0x1b7740>;
  164. qcom,mipi-csi-vdd-supply = <0x2>;
  165. };
  166.  
  167. qcom,csid@fda08C00 {
  168. cell-index = <0x3>;
  169. compatible = "qcom,csid";
  170. reg = <0xfda08c00 0x100>;
  171. reg-names = "csid";
  172. interrupts = <0x0 0x36 0x0>;
  173. interrupt-names = "csid";
  174. qcom,csi-vdd-voltage = <0x1b7740>;
  175. qcom,mipi-csi-vdd-supply = <0x2>;
  176. };
  177.  
  178. qcom,ispif@fda0A000 {
  179. cell-index = <0x0>;
  180. compatible = "qcom,ispif-v3.0", "qcom,ispif";
  181. reg = <0xfda0a000 0x500 0xfda00020 0x10>;
  182. reg-names = "ispif", "csi_clk_mux";
  183. interrupts = <0x0 0x37 0x0>;
  184. interrupt-names = "ispif";
  185. qcom,num-isps = <0x2>;
  186. };
  187.  
  188. qcom,vfe@fda10000 {
  189. cell-index = <0x0>;
  190. compatible = "qcom,vfe40";
  191. reg = <0xfda10000 0x1000 0xfda40000 0x200 0xfd4a8000 0x4>;
  192. reg-names = "vfe", "vfe_vbif", "tcsr";
  193. interrupts = <0x0 0x39 0x0>;
  194. interrupt-names = "vfe";
  195. vdd-supply = <0x3>;
  196. };
  197.  
  198. qcom,vfe@fda14000 {
  199. cell-index = <0x1>;
  200. compatible = "qcom,vfe40";
  201. reg = <0xfda14000 0x1000 0xfda40000 0x200 0xfd4a8000 0x4>;
  202. reg-names = "vfe", "vfe_vbif", "tcsr";
  203. interrupts = <0x0 0x3a 0x0>;
  204. interrupt-names = "vfe";
  205. vdd-supply = <0x3>;
  206. };
  207.  
  208. qcom,jpeg@fda1c000 {
  209. cell-index = <0x0>;
  210. compatible = "qcom,jpeg";
  211. reg = <0xfda1c000 0x400>;
  212. reg-names = "jpeg";
  213. interrupts = <0x0 0x3b 0x0>;
  214. interrupt-names = "jpeg";
  215. vdd-supply = <0x4>;
  216. };
  217.  
  218. qcom,jpeg@fda20000 {
  219. cell-index = <0x1>;
  220. compatible = "qcom,jpeg";
  221. reg = <0xfda20000 0x400>;
  222. reg-names = "jpeg";
  223. interrupts = <0x0 0x3c 0x0>;
  224. interrupt-names = "jpeg";
  225. vdd-supply = <0x4>;
  226. };
  227.  
  228. qcom,jpeg@fda24000 {
  229. cell-index = <0x2>;
  230. compatible = "qcom,jpeg";
  231. reg = <0xfda24000 0x400>;
  232. reg-names = "jpeg";
  233. interrupts = <0x0 0x3d 0x0>;
  234. interrupt-names = "jpeg";
  235. vdd-supply = <0x4>;
  236. };
  237.  
  238. qcom,irqrouter@fda00000 {
  239. cell-index = <0x0>;
  240. compatible = "qcom,irqrouter";
  241. reg = <0xfda00000 0x100>;
  242. reg-names = "irqrouter";
  243. };
  244.  
  245. qcom,cpp@fda04000 {
  246. cell-index = <0x0>;
  247. compatible = "qcom,cpp";
  248. reg = <0xfda04000 0x100 0xfda40000 0x200 0xfda18000 0x18>;
  249. reg-names = "cpp", "cpp_vbif", "cpp_hw";
  250. interrupts = <0x0 0x31 0x0>;
  251. interrupt-names = "cpp";
  252. vdd-supply = <0x3>;
  253. };
  254.  
  255. qcom,cci@fda0C000 {
  256. cell-index = <0x0>;
  257. compatible = "qcom,cci";
  258. reg = <0xfda0c000 0x1000>;
  259. #address-cells = <0x1>;
  260. #size-cells = <0x0>;
  261. reg-names = "cci";
  262. interrupts = <0x0 0x32 0x0>;
  263. interrupt-names = "cci";
  264. gpios = <0x5 0x13 0x0 0x5 0x14 0x0 0x5 0x15 0x0 0x5 0x16 0x0>;
  265. qcom,gpio-tbl-num = <0x0 0x1 0x2 0x3>;
  266. qcom,gpio-tbl-flags = <0x1 0x1 0x1 0x1>;
  267. qcom,gpio-tbl-label = "CCI_I2C_DATA0", "CCI_I2C_CLK0", "CCI_I2C_DATA1", "CCI_I2C_CLK1";
  268.  
  269. qcom,cci-master0 {
  270. status = "ok";
  271. qcom,hw-thigh = <0x4e>;
  272. qcom,hw-tlow = <0x72>;
  273. qcom,hw-tsu-sto = <0x1c>;
  274. qcom,hw-tsu-sta = <0x1c>;
  275. qcom,hw-thd-dat = <0xa>;
  276. qcom,hw-thd-sta = <0x4d>;
  277. qcom,hw-tbuf = <0x76>;
  278. qcom,hw-scl-stretch-en = <0x0>;
  279. qcom,hw-trdhld = <0x6>;
  280. qcom,hw-tsp = <0x1>;
  281. };
  282.  
  283. qcom,cci-master1 {
  284. status = "ok";
  285. qcom,hw-thigh = <0x4e>;
  286. qcom,hw-tlow = <0x72>;
  287. qcom,hw-tsu-sto = <0x1c>;
  288. qcom,hw-tsu-sta = <0x1c>;
  289. qcom,hw-thd-dat = <0xa>;
  290. qcom,hw-thd-sta = <0x4d>;
  291. qcom,hw-tbuf = <0x76>;
  292. qcom,hw-scl-stretch-en = <0x0>;
  293. qcom,hw-trdhld = <0x6>;
  294. qcom,hw-tsp = <0x1>;
  295. };
  296.  
  297. qcom,eeprom@20 {
  298. cell-index = <0x0>;
  299. reg = <0x20>;
  300. qcom,eeprom-name = "sunny_q8v18a";
  301. compatible = "qcom,eeprom";
  302. qcom,slave-addr = <0x20>;
  303. qcom,cci-master = <0x0>;
  304. qcom,num-blocks = <0x4>;
  305. qcom,page0 = <0x1 0x100 0x2 0x1 0x1 0x1>;
  306. qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x1>;
  307. qcom,mem0 = <0x0 0x0 0x2 0x0 0x1 0x0>;
  308. qcom,page1 = <0x1 0x3d84 0x2 0xc0 0x1 0x1>;
  309. qcom,poll1 = <0x0 0x0 0x2 0x0 0x1 0x1>;
  310. qcom,mem1 = <0x0 0x3d00 0x2 0x0 0x1 0x0>;
  311. qcom,page2 = <0x1 0x3d88 0x2 0x7010 0x2 0x1>;
  312. qcom,poll2 = <0x0 0x0 0x2 0x0 0x1 0x1>;
  313. qcom,mem2 = <0x0 0x3d00 0x2 0x0 0x1 0x0>;
  314. qcom,page3 = <0x1 0x3d8a 0x2 0x70f4 0x2 0x1>;
  315. qcom,pageen3 = <0x1 0x3d81 0x2 0x1 0x1 0xa>;
  316. qcom,poll3 = <0x0 0x0 0x2 0x0 0x1 0x1>;
  317. qcom,mem3 = <0xe4 0x7010 0x2 0x0 0x1 0x1>;
  318. cam_vdig-supply = <0x6>;
  319. cam_vana-supply = <0x7>;
  320. cam_vio-supply = <0x8>;
  321. qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio";
  322. qcom,cam-vreg-type = <0x0 0x0 0x1>;
  323. qcom,cam-vreg-min-voltage = <0x12b128 0x2b7cd0 0x0>;
  324. qcom,cam-vreg-max-voltage = <0x12b128 0x2b7cd0 0x0>;
  325. qcom,cam-vreg-op-mode = <0x19a28 0x13880 0x0>;
  326. qcom,gpio-no-mux = <0x0>;
  327. gpios = <0x5 0xf 0x0 0x5 0x5a 0x0 0x5 0x59 0x0>;
  328. qcom,gpio-reset = <0x1>;
  329. qcom,gpio-standby = <0x2>;
  330. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  331. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  332. qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0", "CAM_STANDBY0";
  333. qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio", "sensor_gpio";
  334. qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio", "sensor_cam_mclk", "sensor_gpio_reset", "sensor_gpio_standby";
  335. qcom,cam-power-seq-cfg-val = <0x1 0x1 0x1 0x16e3600 0x1 0x1>;
  336. qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x5 0x5 0xa>;
  337. linux,phandle = <0x9>;
  338. phandle = <0x9>;
  339. };
  340.  
  341. qcom,actuator@18 {
  342. cell-index = <0x0>;
  343. reg = <0x18>;
  344. compatible = "qcom,actuator";
  345. qcom,cci-master = <0x0>;
  346. linux,phandle = <0xa>;
  347. phandle = <0xa>;
  348. };
  349.  
  350. qcom,actuator@36 {
  351. cell-index = <0x1>;
  352. reg = <0x36>;
  353. compatible = "qcom,actuator";
  354. qcom,cci-master = <0x0>;
  355. };
  356.  
  357. qcom,camera@90 {
  358. compatible = "qcom,mt9m114";
  359. reg = <0x90>;
  360. qcom,slave-id = <0x90 0x0 0x2481>;
  361. qcom,csiphy-sd-index = <0x1>;
  362. qcom,csid-sd-index = <0x0>;
  363. qcom,mount-angle = <0x0>;
  364. qcom,sensor-name = "mt9m114";
  365. cam_vdig-supply = <0x6>;
  366. cam_vana-supply = <0x7>;
  367. cam_vio-supply = <0x8>;
  368. qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio";
  369. qcom,cam-vreg-type = <0x0 0x0 0x1>;
  370. qcom,cam-vreg-min-voltage = <0x12b128 0x2b7cd0 0x0>;
  371. qcom,cam-vreg-max-voltage = <0x12b128 0x2b7cd0 0x0>;
  372. qcom,cam-vreg-op-mode = <0x19a28 0x13880 0x0>;
  373. qcom,gpio-no-mux = <0x0>;
  374. gpios = <0x5 0x10 0x0 0x5 0x5c 0x0>;
  375. qcom,gpio-reset = <0x1>;
  376. qcom,gpio-req-tbl-num = <0x0 0x1>;
  377. qcom,gpio-req-tbl-flags = <0x1 0x0>;
  378. qcom,gpio-req-tbl-label = "CAMIF_MCLK", "CAM_RESET1";
  379. qcom,gpio-set-tbl-num = <0x1 0x1>;
  380. qcom,gpio-set-tbl-flags = <0x0 0x2>;
  381. qcom,gpio-set-tbl-delay = <0x3e8 0xfa0>;
  382. qcom,csi-lane-assign = <0x4320>;
  383. qcom,csi-lane-mask = <0x3>;
  384. qcom,sensor-position = <0x1>;
  385. qcom,sensor-mode = <0x1>;
  386. qcom,cci-master = <0x0>;
  387. };
  388.  
  389. qcom,camera@0 {
  390. cell-index = <0x0>;
  391. compatible = "qcom,camera";
  392. reg = <0x0>;
  393. qcom,csiphy-sd-index = <0x0>;
  394. qcom,csid-sd-index = <0x0>;
  395. qcom,mount-angle = <0x5a>;
  396. qcom,eeprom-src = <0x9>;
  397. qcom,actuator-src = <0xa>;
  398. qcom,led-flash-src = <0xb>;
  399. cam_vdig-supply = <0x6>;
  400. cam_vana-supply = <0x7>;
  401. cam_vio-supply = <0x8>;
  402. cam_vaf-supply = <0xc>;
  403. qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", "cam_vaf";
  404. qcom,cam-vreg-type = <0x0 0x1 0x0 0x0>;
  405. qcom,cam-vreg-min-voltage = <0x12b128 0x0 0x2b7cd0 0x2dc6c0>;
  406. qcom,cam-vreg-max-voltage = <0x12b128 0x0 0x2b7cd0 0x2dc6c0>;
  407. qcom,cam-vreg-op-mode = <0x19a28 0x0 0x13880 0x186a0>;
  408. qcom,gpio-no-mux = <0x0>;
  409. gpios = <0x5 0xf 0x0 0x5 0x5a 0x0 0x5 0x59 0x0>;
  410. qcom,gpio-reset = <0x1>;
  411. qcom,gpio-standby = <0x2>;
  412. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  413. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  414. qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0", "CAM_STANDBY0";
  415. qcom,sensor-position = <0x0>;
  416. qcom,sensor-mode = <0x0>;
  417. qcom,cci-master = <0x0>;
  418. status = "ok";
  419. };
  420.  
  421. qcom,camera@1 {
  422. cell-index = <0x1>;
  423. compatible = "qcom,camera";
  424. reg = <0x1>;
  425. qcom,csiphy-sd-index = <0x1>;
  426. qcom,csid-sd-index = <0x0>;
  427. qcom,mount-angle = <0x5a>;
  428. cam_vdig-supply = <0x6>;
  429. cam_vana-supply = <0x7>;
  430. cam_vio-supply = <0x8>;
  431. qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", "cam_vaf";
  432. qcom,cam-vreg-type = <0x0 0x1 0x0 0x0>;
  433. qcom,cam-vreg-min-voltage = <0x12b128 0x0 0x2b7cd0 0x2dc6c0>;
  434. qcom,cam-vreg-max-voltage = <0x12b128 0x0 0x2b7cd0 0x2dc6c0>;
  435. qcom,cam-vreg-op-mode = <0x19a28 0x0 0x13880 0x186a0>;
  436. gpios = <0x5 0x10 0x0 0x5 0x5c 0x0 0x5 0x5b 0x0>;
  437. qcom,gpio-reset = <0x1>;
  438. qcom,gpio-standby = <0x2>;
  439. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  440. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  441. qcom,gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1", "CAM_STANDBY1";
  442. qcom,sensor-position = <0x0>;
  443. qcom,sensor-mode = <0x0>;
  444. qcom,cci-master = <0x0>;
  445. status = "ok";
  446. };
  447.  
  448. qcom,camera@2 {
  449. cell-index = <0x2>;
  450. compatible = "qcom,camera";
  451. reg = <0x2>;
  452. qcom,csiphy-sd-index = <0x2>;
  453. qcom,csid-sd-index = <0x2>;
  454. qcom,mount-angle = <0x10e>;
  455. cam_vdig-supply = <0x6>;
  456. cam_vana-supply = <0xd>;
  457. cam_vio-supply = <0x8>;
  458. qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio";
  459. qcom,cam-vreg-type = <0x0 0x0 0x1>;
  460. qcom,cam-vreg-min-voltage = <0x12b128 0x2dc6c0 0x0>;
  461. qcom,cam-vreg-max-voltage = <0x12b128 0x2dc6c0 0x0>;
  462. qcom,cam-vreg-op-mode = <0x19a28 0x13880 0x0>;
  463. qcom,gpio-no-mux = <0x0>;
  464. gpios = <0x5 0x11 0x0 0x5 0x12 0x0>;
  465. #qcom,gpio-reset = <0x1>;
  466. qcom,gpio-vdig = <0x1>;
  467. qcom,gpio-req-tbl-num = <0x0 0x1>;
  468. qcom,gpio-req-tbl-flags = <0x1 0x0>;
  469. qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_VDIG";
  470. qcom,sensor-position = <0x1>;
  471. qcom,sensor-mode = <0x1>;
  472. qcom,cci-master = <0x1>;
  473. };
  474. };
  475.  
  476. tmc@fc322000 {
  477. compatible = "arm,coresight-tmc";
  478. reg = <0xfc322000 0x1000 0xfc37c000 0x3000>;
  479. reg-names = "tmc-base", "bam-base";
  480. interrupts = <0x0 0xa6 0x0>;
  481. interrupt-names = "byte-cntr-irq";
  482. qcom,memory-size = <0x100000>;
  483. coresight-id = <0x0>;
  484. coresight-name = "coresight-tmc-etr";
  485. coresight-nr-inports = <0x1>;
  486. coresight-ctis = <0xe 0xf>;
  487. linux,phandle = <0x12>;
  488. phandle = <0x12>;
  489. };
  490.  
  491. tpiu@fc318000 {
  492. compatible = "arm,coresight-tpiu";
  493. reg = <0xfc318000 0x1000>;
  494. reg-names = "tpiu-base";
  495. coresight-id = <0x1>;
  496. coresight-name = "coresight-tpiu";
  497. coresight-nr-inports = <0x1>;
  498. vdd-supply = <0x10>;
  499. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  500. qcom,vdd-current-level = <0x2328 0xc3500>;
  501. vdd-io-supply = <0x11>;
  502. qcom,vdd-io-voltage-level = <0x2d0370 0x2d0370>;
  503. qcom,vdd-io-current-level = <0x6 0x55f0>;
  504. linux,phandle = <0x13>;
  505. phandle = <0x13>;
  506. };
  507.  
  508. replicator@fc31c000 {
  509. compatible = "qcom,coresight-replicator";
  510. reg = <0xfc31c000 0x1000>;
  511. reg-names = "replicator-base";
  512. coresight-id = <0x2>;
  513. coresight-name = "coresight-replicator";
  514. coresight-nr-inports = <0x1>;
  515. coresight-outports = <0x0 0x1>;
  516. coresight-child-list = <0x12 0x13>;
  517. coresight-child-ports = <0x0 0x0>;
  518. linux,phandle = <0x14>;
  519. phandle = <0x14>;
  520. };
  521.  
  522. tmc@fc307000 {
  523. compatible = "arm,coresight-tmc";
  524. reg = <0xfc307000 0x1000>;
  525. reg-names = "tmc-base";
  526. coresight-id = <0x3>;
  527. coresight-name = "coresight-tmc-etf";
  528. coresight-nr-inports = <0x1>;
  529. coresight-outports = <0x0>;
  530. coresight-child-list = <0x14>;
  531. coresight-child-ports = <0x0>;
  532. coresight-default-sink;
  533. coresight-ctis = <0xe 0xf>;
  534. linux,phandle = <0x15>;
  535. phandle = <0x15>;
  536. };
  537.  
  538. funnel@fc31b000 {
  539. compatible = "arm,coresight-funnel";
  540. reg = <0xfc31b000 0x1000>;
  541. reg-names = "funnel-base";
  542. coresight-id = <0x4>;
  543. coresight-name = "coresight-funnel-merg";
  544. coresight-nr-inports = <0x2>;
  545. coresight-outports = <0x0>;
  546. coresight-child-list = <0x15>;
  547. coresight-child-ports = <0x0>;
  548. linux,phandle = <0x16>;
  549. phandle = <0x16>;
  550. };
  551.  
  552. funnel@fc319000 {
  553. compatible = "arm,coresight-funnel";
  554. reg = <0xfc319000 0x1000>;
  555. reg-names = "funnel-base";
  556. coresight-id = <0x5>;
  557. coresight-name = "coresight-funnel-in0";
  558. coresight-nr-inports = <0x8>;
  559. coresight-outports = <0x0>;
  560. coresight-child-list = <0x16>;
  561. coresight-child-ports = <0x0>;
  562. linux,phandle = <0x19>;
  563. phandle = <0x19>;
  564. };
  565.  
  566. funnel@fc31a000 {
  567. compatible = "arm,coresight-funnel";
  568. reg = <0xfc31a000 0x1000>;
  569. reg-names = "funnel-base";
  570. coresight-id = <0x6>;
  571. coresight-name = "coresight-funnel-in1";
  572. coresight-nr-inports = <0x8>;
  573. coresight-outports = <0x0>;
  574. coresight-child-list = <0x16>;
  575. coresight-child-ports = <0x1>;
  576. linux,phandle = <0x17>;
  577. phandle = <0x17>;
  578. };
  579.  
  580. funnel@fc345000 {
  581. compatible = "arm,coresight-funnel";
  582. reg = <0xfc345000 0x1000>;
  583. reg-names = "funnel-base";
  584. coresight-id = <0x7>;
  585. coresight-name = "coresight-funnel-kpss";
  586. coresight-nr-inports = <0x4>;
  587. coresight-outports = <0x0>;
  588. coresight-child-list = <0x17>;
  589. coresight-child-ports = <0x5>;
  590. linux,phandle = <0x18>;
  591. phandle = <0x18>;
  592. };
  593.  
  594. funnel@fc364000 {
  595. compatible = "arm,coresight-funnel";
  596. reg = <0xfc364000 0x1000>;
  597. reg-names = "funnel-base";
  598. coresight-id = <0x8>;
  599. coresight-name = "coresight-funnel-mmss";
  600. coresight-nr-inports = <0x8>;
  601. coresight-outports = <0x0>;
  602. coresight-child-list = <0x17>;
  603. coresight-child-ports = <0x1>;
  604. linux,phandle = <0x21>;
  605. phandle = <0x21>;
  606. };
  607.  
  608. stm@fc321000 {
  609. compatible = "arm,coresight-stm";
  610. reg = <0xfc321000 0x1000 0xfa280000 0x180000>;
  611. reg-names = "stm-base", "stm-data-base";
  612. coresight-id = <0x9>;
  613. coresight-name = "coresight-stm";
  614. coresight-nr-inports = <0x0>;
  615. coresight-outports = <0x0>;
  616. coresight-child-list = <0x17>;
  617. coresight-child-ports = <0x7>;
  618. };
  619.  
  620. etm@fc33c000 {
  621. compatible = "arm,coresight-etm";
  622. reg = <0xfc33c000 0x1000>;
  623. reg-names = "etm-base";
  624. coresight-id = <0xa>;
  625. coresight-name = "coresight-etm0";
  626. coresight-nr-inports = <0x0>;
  627. coresight-outports = <0x0>;
  628. coresight-child-list = <0x18>;
  629. coresight-child-ports = <0x0>;
  630. qcom,pc-save;
  631. qcom,round-robin;
  632. };
  633.  
  634. etm@fc33d000 {
  635. compatible = "arm,coresight-etm";
  636. reg = <0xfc33d000 0x1000>;
  637. reg-names = "etm-base";
  638. coresight-id = <0xb>;
  639. coresight-name = "coresight-etm1";
  640. coresight-nr-inports = <0x0>;
  641. coresight-outports = <0x0>;
  642. coresight-child-list = <0x18>;
  643. coresight-child-ports = <0x1>;
  644. qcom,pc-save;
  645. qcom,round-robin;
  646. };
  647.  
  648. etm@fc33e000 {
  649. compatible = "arm,coresight-etm";
  650. reg = <0xfc33e000 0x1000>;
  651. reg-names = "etm-base";
  652. coresight-id = <0xc>;
  653. coresight-name = "coresight-etm2";
  654. coresight-nr-inports = <0x0>;
  655. coresight-outports = <0x0>;
  656. coresight-child-list = <0x18>;
  657. coresight-child-ports = <0x2>;
  658. qcom,pc-save;
  659. qcom,round-robin;
  660. };
  661.  
  662. etm@fc33f000 {
  663. compatible = "arm,coresight-etm";
  664. reg = <0xfc33f000 0x1000>;
  665. reg-names = "etm-base";
  666. coresight-id = <0xd>;
  667. coresight-name = "coresight-etm3";
  668. coresight-nr-inports = <0x0>;
  669. coresight-outports = <0x0>;
  670. coresight-child-list = <0x18>;
  671. coresight-child-ports = <0x3>;
  672. qcom,pc-save;
  673. qcom,round-robin;
  674. };
  675.  
  676. audio_etm0 {
  677. compatible = "qcom,coresight-audio-etm";
  678. coresight-id = <0xe>;
  679. coresight-name = "coresight-audio-etm0";
  680. coresight-nr-inports = <0x0>;
  681. coresight-outports = <0x0>;
  682. coresight-child-list = <0x19>;
  683. coresight-child-ports = <0x2>;
  684. };
  685.  
  686. modem_etm0 {
  687. compatible = "qcom,coresight-modem-etm";
  688. coresight-id = <0xf>;
  689. coresight-name = "coresight-modem-etm0";
  690. coresight-nr-inports = <0x0>;
  691. coresight-outports = <0x0>;
  692. coresight-child-list = <0x19>;
  693. coresight-child-ports = <0x1>;
  694. };
  695.  
  696. wcn_etm0 {
  697. compatible = "qcom,coresight-wcn-etm";
  698. coresight-id = <0x10>;
  699. coresight-name = "coresight-wcn-etm0";
  700. coresight-nr-inports = <0x0>;
  701. coresight-outports = <0x0>;
  702. coresight-child-list = <0x17>;
  703. coresight-child-ports = <0x2>;
  704. };
  705.  
  706. rpm_etm0 {
  707. compatible = "qcom,coresight-rpm-etm";
  708. coresight-id = <0x11>;
  709. coresight-name = "coresight-rpm-etm0";
  710. coresight-nr-inports = <0x0>;
  711. coresight-outports = <0x0>;
  712. coresight-child-list = <0x19>;
  713. coresight-child-ports = <0x0>;
  714. };
  715.  
  716. csr@fc302000 {
  717. compatible = "qcom,coresight-csr";
  718. reg = <0xfc302000 0x1000>;
  719. reg-names = "csr-base";
  720. coresight-id = <0x12>;
  721. coresight-name = "coresight-csr";
  722. coresight-nr-inports = <0x0>;
  723. qcom,blk-size = <0x3>;
  724. };
  725.  
  726. cti@fc308000 {
  727. compatible = "arm,coresight-cti";
  728. reg = <0xfc308000 0x1000>;
  729. reg-names = "cti-base";
  730. coresight-id = <0x13>;
  731. coresight-name = "coresight-cti0";
  732. coresight-nr-inports = <0x0>;
  733. linux,phandle = <0xe>;
  734. phandle = <0xe>;
  735. };
  736.  
  737. cti@fc309000 {
  738. compatible = "arm,coresight-cti";
  739. reg = <0xfc309000 0x1000>;
  740. reg-names = "cti-base";
  741. coresight-id = <0x14>;
  742. coresight-name = "coresight-cti1";
  743. coresight-nr-inports = <0x0>;
  744. };
  745.  
  746. cti@fc30a000 {
  747. compatible = "arm,coresight-cti";
  748. reg = <0xfc30a000 0x1000>;
  749. reg-names = "cti-base";
  750. coresight-id = <0x15>;
  751. coresight-name = "coresight-cti2";
  752. coresight-nr-inports = <0x0>;
  753. };
  754.  
  755. cti@fc30b000 {
  756. compatible = "arm,coresight-cti";
  757. reg = <0xfc30b000 0x1000>;
  758. reg-names = "cti-base";
  759. coresight-id = <0x16>;
  760. coresight-name = "coresight-cti3";
  761. coresight-nr-inports = <0x0>;
  762. };
  763.  
  764. cti@fc30c000 {
  765. compatible = "arm,coresight-cti";
  766. reg = <0xfc30c000 0x1000>;
  767. reg-names = "cti-base";
  768. coresight-id = <0x17>;
  769. coresight-name = "coresight-cti4";
  770. coresight-nr-inports = <0x0>;
  771. };
  772.  
  773. cti@fc30d000 {
  774. compatible = "arm,coresight-cti";
  775. reg = <0xfc30d000 0x1000>;
  776. reg-names = "cti-base";
  777. coresight-id = <0x18>;
  778. coresight-name = "coresight-cti5";
  779. coresight-nr-inports = <0x0>;
  780. };
  781.  
  782. cti@fc30e000 {
  783. compatible = "arm,coresight-cti";
  784. reg = <0xfc30e000 0x1000>;
  785. reg-names = "cti-base";
  786. coresight-id = <0x19>;
  787. coresight-name = "coresight-cti6";
  788. coresight-nr-inports = <0x0>;
  789. };
  790.  
  791. cti@fc30f000 {
  792. compatible = "arm,coresight-cti";
  793. reg = <0xfc30f000 0x1000>;
  794. reg-names = "cti-base";
  795. coresight-id = <0x1a>;
  796. coresight-name = "coresight-cti7";
  797. coresight-nr-inports = <0x0>;
  798. };
  799.  
  800. cti@fc310000 {
  801. compatible = "arm,coresight-cti";
  802. reg = <0xfc310000 0x1000>;
  803. reg-names = "cti-base";
  804. coresight-id = <0x1b>;
  805. coresight-name = "coresight-cti8";
  806. coresight-nr-inports = <0x0>;
  807. linux,phandle = <0xf>;
  808. phandle = <0xf>;
  809. };
  810.  
  811. cti@fc340000 {
  812. compatible = "arm,coresight-cti";
  813. reg = <0xfc340000 0x1000>;
  814. reg-names = "cti-base";
  815. coresight-id = <0x1c>;
  816. coresight-name = "coresight-cti-l2";
  817. coresight-nr-inports = <0x0>;
  818. };
  819.  
  820. cti@fc341000 {
  821. compatible = "arm,coresight-cti";
  822. reg = <0xfc341000 0x1000>;
  823. reg-names = "cti-base";
  824. coresight-id = <0x1d>;
  825. coresight-name = "coresight-cti-cpu0";
  826. coresight-nr-inports = <0x0>;
  827. };
  828.  
  829. cti@fc342000 {
  830. compatible = "arm,coresight-cti";
  831. reg = <0xfc342000 0x1000>;
  832. reg-names = "cti-base";
  833. coresight-id = <0x1e>;
  834. coresight-name = "coresight-cti-cpu1";
  835. coresight-nr-inports = <0x0>;
  836. };
  837.  
  838. cti@fc343000 {
  839. compatible = "arm,coresight-cti";
  840. reg = <0xfc343000 0x1000>;
  841. reg-names = "cti-base";
  842. coresight-id = <0x1f>;
  843. coresight-name = "coresight-cti-cpu2";
  844. coresight-nr-inports = <0x0>;
  845. };
  846.  
  847. cti@fc344000 {
  848. compatible = "arm,coresight-cti";
  849. reg = <0xfc344000 0x1000>;
  850. reg-names = "cti-base";
  851. coresight-id = <0x20>;
  852. coresight-name = "coresight-cti-cpu3";
  853. coresight-nr-inports = <0x0>;
  854. };
  855.  
  856. cti@fc348000 {
  857. compatible = "arm,coresight-cti";
  858. reg = <0xfc348000 0x1000>;
  859. reg-names = "cti-base";
  860. coresight-id = <0x21>;
  861. coresight-name = "coresight-cti-video-cpu0";
  862. coresight-nr-inports = <0x0>;
  863. };
  864.  
  865. cti@fc34d000 {
  866. compatible = "arm,coresight-cti";
  867. reg = <0xfc34d000 0x1000>;
  868. reg-names = "cti-base";
  869. coresight-id = <0x22>;
  870. coresight-name = "coresight-cti-wcn-cpu0";
  871. coresight-nr-inports = <0x0>;
  872. };
  873.  
  874. cti@fc350000 {
  875. compatible = "arm,coresight-cti";
  876. reg = <0xfc350000 0x1000>;
  877. reg-names = "cti-base";
  878. coresight-id = <0x23>;
  879. coresight-name = "coresight-cti-modem-cpu0";
  880. coresight-nr-inports = <0x0>;
  881. };
  882.  
  883. cti@fc354000 {
  884. compatible = "arm,coresight-cti";
  885. reg = <0xfc354000 0x1000>;
  886. reg-names = "cti-base";
  887. coresight-id = <0x24>;
  888. coresight-name = "coresight-cti-audio-cpu0";
  889. coresight-nr-inports = <0x0>;
  890. };
  891.  
  892. cti@fc358000 {
  893. compatible = "arm,coresight-cti";
  894. reg = <0xfc358000 0x1000>;
  895. reg-names = "cti-base";
  896. coresight-id = <0x25>;
  897. coresight-name = "coresight-cti-rpm-cpu0";
  898. coresight-nr-inports = <0x0>;
  899. };
  900.  
  901. hwevent@fdf30018 {
  902. compatible = "qcom,coresight-hwevent";
  903. reg = <0xfdf30018 0x80 0xf9011080 0x80 0xfd4ab160 0x80 0xfc401600 0x80>;
  904. reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux";
  905. coresight-id = <0x26>;
  906. coresight-name = "coresight-hwevent";
  907. coresight-nr-inports = <0x0>;
  908. qcom,hwevent-clks = "core_mmss_clk";
  909. };
  910.  
  911. fuse@fc4be024 {
  912. compatible = "arm,coresight-fuse";
  913. reg = <0xfc4be024 0x8>;
  914. reg-names = "fuse-base";
  915. coresight-id = <0x27>;
  916. coresight-name = "coresight-fuse";
  917. coresight-nr-inports = <0x0>;
  918. };
  919.  
  920. qcom,gdsc@fd8c1024 {
  921. compatible = "qcom,gdsc";
  922. regulator-name = "gdsc_venus";
  923. reg = <0xfd8c1024 0x4>;
  924. status = "ok";
  925. qcom,clock-names = "core_clk";
  926. qcom,skip-logic-collapse;
  927. linux,phandle = <0x3c>;
  928. phandle = <0x3c>;
  929. };
  930.  
  931. qcom,gdsc@fd8c1040 {
  932. compatible = "qcom,gdsc";
  933. regulator-name = "gdsc_venus_core0";
  934. reg = <0xfd8c1040 0x4>;
  935. status = "disabled";
  936. };
  937.  
  938. qcom,gdsc@fd8c1044 {
  939. compatible = "qcom,gdsc";
  940. regulator-name = "gdsc_venus_core1";
  941. reg = <0xfd8c1044 0x4>;
  942. status = "disabled";
  943. };
  944.  
  945. qcom,gdsc@fd8c1404 {
  946. compatible = "qcom,gdsc";
  947. regulator-name = "gdsc_vpu";
  948. reg = <0xfd8c1404 0x4>;
  949. status = "disabled";
  950. };
  951.  
  952. qcom,gdsc@fd8c2304 {
  953. compatible = "qcom,gdsc";
  954. regulator-name = "gdsc_mdss";
  955. reg = <0xfd8c2304 0x4>;
  956. status = "ok";
  957. qcom,clock-names = "core_clk", "lut_clk";
  958. linux,phandle = <0x22>;
  959. phandle = <0x22>;
  960. };
  961.  
  962. qcom,gdsc@fd8c35a4 {
  963. compatible = "qcom,gdsc";
  964. regulator-name = "gdsc_jpeg";
  965. reg = <0xfd8c35a4 0x4>;
  966. status = "ok";
  967. qcom,clock-names = "core0_clk", "core1_clk", "core2_clk";
  968. linux,phandle = <0x4>;
  969. phandle = <0x4>;
  970. };
  971.  
  972. qcom,gdsc@fd8c36a4 {
  973. compatible = "qcom,gdsc";
  974. regulator-name = "gdsc_vfe";
  975. reg = <0xfd8c36a4 0x4>;
  976. status = "ok";
  977. qcom,clock-names = "core0_clk", "core1_clk", "csi0_clk", "csi1_clk", "cpp_clk";
  978. linux,phandle = <0x3>;
  979. phandle = <0x3>;
  980. };
  981.  
  982. qcom,gdsc@fd8c4024 {
  983. compatible = "qcom,gdsc";
  984. regulator-name = "gdsc_oxili_gx";
  985. reg = <0xfd8c4024 0x4>;
  986. status = "ok";
  987. parent-supply = <0x1a>;
  988. qcom,clock-names = "core_clk";
  989. linux,phandle = <0x1f>;
  990. phandle = <0x1f>;
  991. };
  992.  
  993. qcom,gdsc@fd8c4034 {
  994. compatible = "qcom,gdsc";
  995. regulator-name = "gdsc_oxili_cx";
  996. reg = <0xfd8c4034 0x4>;
  997. status = "ok";
  998. linux,phandle = <0x1e>;
  999. phandle = <0x1e>;
  1000. };
  1001.  
  1002. qcom,gdsc@fc400404 {
  1003. compatible = "qcom,gdsc";
  1004. regulator-name = "gdsc_usb_hsic";
  1005. reg = <0xfc400404 0x4>;
  1006. status = "ok";
  1007. };
  1008.  
  1009. qcom,gdsc@fc401ac4 {
  1010. compatible = "qcom,gdsc";
  1011. regulator-name = "gdsc_pcie_0";
  1012. reg = <0xfc401ac4 0x4>;
  1013. status = "disabled";
  1014. };
  1015.  
  1016. qcom,gdsc@fc401b44 {
  1017. compatible = "qcom,gdsc";
  1018. regulator-name = "gdsc_pcie_1";
  1019. reg = <0xfc401b44 0x4>;
  1020. status = "disabled";
  1021. };
  1022.  
  1023. qcom,gdsc@fc401e84 {
  1024. compatible = "qcom,gdsc";
  1025. regulator-name = "gdsc_usb30";
  1026. reg = <0xfc401e84 0x4>;
  1027. status = "disabled";
  1028. };
  1029.  
  1030. qcom,gdsc@fc401ec0 {
  1031. compatible = "qcom,gdsc";
  1032. regulator-name = "gdsc_usb30_sec";
  1033. reg = <0xfc401ec0 0x4>;
  1034. status = "disabled";
  1035. };
  1036.  
  1037. qcom,gdsc@fd8c1804 {
  1038. compatible = "qcom,gdsc";
  1039. regulator-name = "gdsc_vcap";
  1040. reg = <0xfd8c1804 0x4>;
  1041. status = "disabled";
  1042. };
  1043.  
  1044. qcom,ion {
  1045. compatible = "qcom,msm-ion";
  1046. #address-cells = <0x1>;
  1047. #size-cells = <0x0>;
  1048.  
  1049. qcom,ion-heap@25 {
  1050. reg = <0x19>;
  1051. qcom,ion-heap-type = "SYSTEM";
  1052. };
  1053.  
  1054. qcom,ion-heap@21 {
  1055. reg = <0x15>;
  1056. qcom,ion-heap-type = "SYSTEM_CONTIG";
  1057. };
  1058.  
  1059. qcom,ion-heap@8 {
  1060. compatible = "qcom,msm-ion-reserve";
  1061. reg = <0x8>;
  1062. qcom,heap-align = <0x1000>;
  1063. linux,contiguous-region = <0x1b>;
  1064. qcom,ion-heap-type = "SECURE_DMA";
  1065. qcom,default-prefetch-size = <0x6c00000>;
  1066. };
  1067.  
  1068. qcom,ion-heap@22 {
  1069. compatible = "qcom,msm-ion-reserve";
  1070. reg = <0x16>;
  1071. qcom,heap-align = <0x1000>;
  1072. linux,contiguous-region = <0x1c>;
  1073. qcom,ion-heap-type = "DMA";
  1074. };
  1075.  
  1076. qcom,ion-heap@27 {
  1077. compatible = "qcom,msm-ion-reserve";
  1078. reg = <0x1b>;
  1079. linux,contiguous-region = <0x1d>;
  1080. qcom,ion-heap-type = "DMA";
  1081. };
  1082.  
  1083. qcom,ion-heap@28 {
  1084. compatible = "qcom,msm-ion-reserve";
  1085. reg = <0x1c>;
  1086. qcom,heap-align = <0x1000>;
  1087. qcom,memory-reservation-type = "EBI1";
  1088. qcom,memory-reservation-size = <0x614000>;
  1089. qcom,ion-heap-type = "CARVEOUT";
  1090. };
  1091.  
  1092. qcom,ion-heap@23 {
  1093. compatible = "qcom,msm-ion-reserve";
  1094. reg = <0x17>;
  1095. qcom,heap-align = <0x1000>;
  1096. qcom,memory-fixed = <0x5a00000 0x2100000>;
  1097. qcom,ion-heap-type = "CARVEOUT";
  1098. };
  1099.  
  1100. qcom,ion-heap@26 {
  1101. compatible = "qcom,msm-ion-reserve";
  1102. reg = <0x1a>;
  1103. qcom,heap-align = <0x1000>;
  1104. qcom,memory-fixed = <0x8000000 0x5000000>;
  1105. qcom,ion-heap-type = "CARVEOUT";
  1106. };
  1107. };
  1108.  
  1109. qcom,kgsl-3d0@fdb00000 {
  1110. label = "kgsl-3d0";
  1111. compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
  1112. reg = <0xfdb00000 0x10000 0xfdb20000 0x10000>;
  1113. reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_shader_memory";
  1114. interrupts = <0x0 0x21 0x0>;
  1115. interrupt-names = "kgsl_3d0_irq";
  1116. qcom,id = <0x0>;
  1117. qcom,chipid = <0x3030002>;
  1118. qcom,initial-pwrlevel = <0x3>;
  1119. qcom,idle-timeout = <0x8>;
  1120. qcom,strtstp-sleepwake;
  1121. qcom,clk-map = <0x6>;
  1122. qcom,msm-bus,name = "grp3d";
  1123. qcom,msm-bus,num-cases = <0xf>;
  1124. qcom,msm-bus,num-paths = <0x2>;
  1125. qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x0 0x0 0x59 0x25c 0x0 0x0 0x1a 0x200 0x124f80 0x2579c0 0x59 0x25c 0x0 0x30d400 0x1a 0x200 0x124f80 0x2579c0 0x59 0x25c 0x0 0x30d400 0x1a 0x200 0x0 0x382700 0x59 0x25c 0x0 0x30d400 0x1a 0x200 0x124f80 0x2579c0 0x59 0x25c 0x0 0x509100 0x1a 0x200 0x0 0x382700 0x59 0x25c 0x0 0x509100 0x1a 0x200 0x0 0x4af380 0x59 0x25c 0x0 0x509100 0x1a 0x200 0x0 0x382700 0x59 0x25c 0x0 0x5ef880 0x1a 0x200 0x0 0x4af380 0x59 0x25c 0x0 0x5ef880 0x1a 0x200 0x0 0x71e440 0x59 0x25c 0x0 0x5ef880 0x1a 0x200 0x0 0x382700 0x59 0x25c 0x0 0x70e270 0x1a 0x200 0x0 0x4af380 0x59 0x25c 0x0 0x70e270 0x1a 0x200 0x0 0x71e440 0x59 0x25c 0x0 0x70e270 0x1a 0x200 0x0 0x4af380 0x59 0x25c 0x0 0x8d1d00 0x1a 0x200 0x0 0x71e440 0x59 0x25c 0x0 0x8d1d00>;
  1126. vddcx-supply = <0x1e>;
  1127. vdd-supply = <0x1f>;
  1128. iommu = <0x20>;
  1129. coresight-id = <0x43>;
  1130. coresight-name = "coresight-gfx";
  1131. coresight-nr-inports = <0x0>;
  1132. coresight-outports = <0x0>;
  1133. coresight-child-list = <0x21>;
  1134. coresight-child-ports = <0x7>;
  1135. qcom,bus-control;
  1136.  
  1137. qcom,gpu-pwrlevels {
  1138. #address-cells = <0x1>;
  1139. #size-cells = <0x0>;
  1140. compatible = "qcom,gpu-pwrlevels";
  1141.  
  1142. qcom,gpu-pwrlevel@0 {
  1143. reg = <0x0>;
  1144. qcom,gpu-freq = <0x22739480>;
  1145. qcom,bus-freq = <0xe>;
  1146. qcom,io-fraction = <0x65>;
  1147. };
  1148.  
  1149. qcom,gpu-pwrlevel@1 {
  1150. reg = <0x1>;
  1151. qcom,gpu-freq = <0x1b8faa00>;
  1152. qcom,bus-freq = <0xb>;
  1153. qcom,io-fraction = <0x65>;
  1154. };
  1155.  
  1156. qcom,gpu-pwrlevel@2 {
  1157. reg = <0x2>;
  1158. qcom,gpu-freq = <0x172fab40>;
  1159. qcom,bus-freq = <0x8>;
  1160. qcom,io-fraction = <0x65>;
  1161. };
  1162.  
  1163. qcom,gpu-pwrlevel@3 {
  1164. reg = <0x3>;
  1165. qcom,gpu-freq = <0x13ab6680>;
  1166. qcom,bus-freq = <0x5>;
  1167. qcom,io-fraction = <0x65>;
  1168. };
  1169.  
  1170. qcom,gpu-pwrlevel@4 {
  1171. reg = <0x4>;
  1172. qcom,gpu-freq = <0xbebc200>;
  1173. qcom,bus-freq = <0x2>;
  1174. qcom,io-fraction = <0x65>;
  1175. };
  1176.  
  1177. qcom,gpu-pwrlevel@5 {
  1178. reg = <0x5>;
  1179. qcom,gpu-freq = <0x19bfcc0>;
  1180. qcom,bus-freq = <0x0>;
  1181. qcom,io-fraction = <0x65>;
  1182. };
  1183. };
  1184.  
  1185. qcom,dcvs-core-info {
  1186. #address-cells = <0x1>;
  1187. #size-cells = <0x0>;
  1188. compatible = "qcom,dcvs-core-info";
  1189. qcom,num-cores = <0x1>;
  1190. qcom,sensors = <0x0>;
  1191. qcom,core-core-type = <0x1>;
  1192. qcom,algo-disable-pc-threshold = <0x0>;
  1193. qcom,algo-em-win-size-min-us = <0x186a0>;
  1194. qcom,algo-em-win-size-max-us = <0x493e0>;
  1195. qcom,algo-em-max-util-pct = <0x61>;
  1196. qcom,algo-group-id = <0x5f>;
  1197. qcom,algo-max-freq-chg-time-us = <0x186a0>;
  1198. qcom,algo-slack-mode-dynamic = <0x186a0>;
  1199. qcom,algo-slack-weight-thresh-pct = <0x0>;
  1200. qcom,algo-slack-time-min-us = <0x9858>;
  1201. qcom,algo-slack-time-max-us = <0x9858>;
  1202. qcom,algo-ss-win-size-min-us = <0xf4240>;
  1203. qcom,algo-ss-win-size-max-us = <0xf4240>;
  1204. qcom,algo-ss-util-pct = <0x5f>;
  1205. qcom,algo-ss-no-corr-below-freq = <0x0>;
  1206. qcom,energy-active-coeff-a = <0x9bc>;
  1207. qcom,energy-active-coeff-b = <0x0>;
  1208. qcom,energy-active-coeff-c = <0x0>;
  1209. qcom,energy-leakage-coeff-a = <0xb>;
  1210. qcom,energy-leakage-coeff-b = <0x265de>;
  1211. qcom,energy-leakage-coeff-c = <0x0>;
  1212. qcom,energy-leakage-coeff-d = <0x0>;
  1213. qcom,power-current-temp = <0x19>;
  1214. qcom,power-num-freq = <0x4>;
  1215.  
  1216. qcom,dcvs-freq@0 {
  1217. reg = <0x0>;
  1218. qcom,freq = <0x0>;
  1219. qcom,voltage = <0x0>;
  1220. qcom,is_trans_level = <0x0>;
  1221. qcom,active-energy-offset = <0x64>;
  1222. qcom,leakage-energy-offset = <0x0>;
  1223. };
  1224.  
  1225. qcom,dcvs-freq@1 {
  1226. reg = <0x1>;
  1227. qcom,freq = <0x0>;
  1228. qcom,voltage = <0x0>;
  1229. qcom,is_trans_level = <0x0>;
  1230. qcom,active-energy-offset = <0x64>;
  1231. qcom,leakage-energy-offset = <0x0>;
  1232. };
  1233.  
  1234. qcom,dcvs-freq@2 {
  1235. reg = <0x2>;
  1236. qcom,freq = <0x0>;
  1237. qcom,voltage = <0x0>;
  1238. qcom,is_trans_level = <0x0>;
  1239. qcom,active-energy-offset = <0x64>;
  1240. qcom,leakage-energy-offset = <0x0>;
  1241. };
  1242.  
  1243. qcom,dcvs-freq@3 {
  1244. reg = <0x3>;
  1245. qcom,freq = <0x0>;
  1246. qcom,voltage = <0x0>;
  1247. qcom,is_trans_level = <0x0>;
  1248. qcom,active-energy-offset = <0xce301>;
  1249. qcom,leakage-energy-offset = <0x0>;
  1250. };
  1251. };
  1252. };
  1253.  
  1254. qcom,mdss_mdp@fd900000 {
  1255. compatible = "qcom,mdss_mdp";
  1256. reg = <0xfd900000 0x22100 0xfd924000 0x1000>;
  1257. reg-names = "mdp_phys", "vbif_phys";
  1258. interrupts = <0x0 0x48 0x0>;
  1259. vdd-supply = <0x22>;
  1260. qcom,max-bandwidth-low-kbps = <0x29f630>;
  1261. qcom,max-bandwidth-high-kbps = <0x2dc6c0>;
  1262. qcom,msm-bus,name = "mdss_mdp";
  1263. qcom,msm-bus,num-cases = <0x3>;
  1264. qcom,msm-bus,num-paths = <0x1>;
  1265. qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800>;
  1266. qcom,mdss-ab-factor = <0x2 0x1>;
  1267. qcom,mdss-ib-factor = <0x6 0x5>;
  1268. qcom,mdss-clk-factor = <0x5 0x4>;
  1269. qcom,mdss-ib-factor-overlap = <0x7 0x4>;
  1270. qcom,max-clk-rate = <0x1312d000>;
  1271. qcom,mdss-pipe-vig-off = <0x1200 0x1600 0x1a00>;
  1272. qcom,mdss-pipe-rgb-off = <0x1e00 0x2200 0x2600>;
  1273. qcom,mdss-pipe-dma-off = <0x2a00 0x2e00>;
  1274. qcom,mdss-pipe-vig-fetch-id = <0x1 0x4 0x7>;
  1275. qcom,mdss-pipe-rgb-fetch-id = <0x10 0x11 0x12>;
  1276. qcom,mdss-pipe-dma-fetch-id = <0xa 0xd>;
  1277. qcom,mdss-pipe-vig-xin-id = <0x0 0x4 0x8>;
  1278. qcom,mdss-pipe-rgb-xin-id = <0x1 0x5 0x9>;
  1279. qcom,mdss-pipe-dma-xin-id = <0x2 0xa>;
  1280. qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x3ac 0x0 0x0 0x3b4 0x0 0x0 0x3bc 0x0 0x0>;
  1281. qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x3ac 0x4 0x8 0x3b4 0x4 0x8 0x3bc 0x4 0x8>;
  1282. qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x3ac 0x8 0xc 0x3b4 0x8 0xc>;
  1283. qcom,mdss-smp-data = <0x16 0x1000>;
  1284. qcom,mdss-ctl-off = <0x600 0x700 0x800 0x900 0xa00>;
  1285. qcom,mdss-mixer-intf-off = <0x3200 0x3600 0x3a00>;
  1286. qcom,mdss-mixer-wb-off = <0x3e00 0x4200>;
  1287. qcom,mdss-dspp-off = <0x4600 0x4a00 0x4e00>;
  1288. qcom,mdss-wb-off = <0x11100 0x11500 0x11900 0x11d00 0x12100>;
  1289. qcom,mdss-intf-off = <0x12500 0x12700 0x12900 0x12b00>;
  1290. qcom,mdss-has-wfd-blk;
  1291. qcom,vbif-settings = <0x4 0x1>;
  1292. qcom,mdp-settings = <0x2e0 0xe9 0x2e4 0x55 0x3ac 0xc0000ccc 0x3b4 0xc0000ccc 0x3bc 0xcccccc 0x4a8 0xcccc0c0 0x4b0 0xccccc0c0 0x4b8 0xccccc000>;
  1293. qcom,mdss-prefill-outstanding-buffer-bytes = <0x400>;
  1294. qcom,mdss-prefill-y-buffer-bytes = <0x1000>;
  1295. qcom,mdss-prefill-scaler-buffer-lines-bilinear = <0x2>;
  1296. qcom,mdss-prefill-scaler-buffer-lines-caf = <0x4>;
  1297. qcom,mdss-prefill-post-scaler-buffer-pixels = <0x0>;
  1298. qcom,mdss-prefill-pingpong-buffer-pixels = <0x1000>;
  1299. qcom,mdss-prefill-fbc-lines = <0x2>;
  1300. qcom,mdss-pingpong-off = <0x12d00 0x12e00 0x12f00>;
  1301. qcom,mdss-has-bwc;
  1302. qcom,mdss-has-decimation;
  1303. qcom,mdss-ad-off = <0x13100 0x13300>;
  1304. vdd-cx-supply = <0x23>;
  1305. qcom,mdss-pref-prim-intf = "dsi";
  1306. batfet-supply = <0x24>;
  1307. linux,phandle = <0x29>;
  1308. phandle = <0x29>;
  1309.  
  1310. qcom,mdss_fb_primary {
  1311. cell-index = <0x0>;
  1312. compatible = "qcom,mdss-fb";
  1313. qcom,memory-reservation-type = "EBI1";
  1314. qcom,memory-reservation-size = <0x800000>;
  1315. qcom,memblock-reserve = <0x3200000 0x1e00000>;
  1316. linux,phandle = <0x28>;
  1317. phandle = <0x28>;
  1318. };
  1319.  
  1320. qcom,mdss_fb_external {
  1321. cell-index = <0x1>;
  1322. compatible = "qcom,mdss-fb";
  1323. linux,phandle = <0x2e>;
  1324. phandle = <0x2e>;
  1325. };
  1326.  
  1327. qcom,mdss_fb_wfd {
  1328. cell-index = <0x2>;
  1329. compatible = "qcom,mdss-fb";
  1330. linux,phandle = <0x2f>;
  1331. phandle = <0x2f>;
  1332. };
  1333.  
  1334. qcom,mdss_dsi_orise_720p_video {
  1335. label = "orise 720p video mode dsi panel";
  1336. qcom,dsi-ctrl-phandle = <0x25>;
  1337. qcom,mdss-pan-res = <0x2d0 0x500>;
  1338. qcom,mdss-pan-bpp = <0x18>;
  1339. qcom,mdss-pan-dest = "display_2";
  1340. qcom,mdss-pan-porch-values = <0x20 0xc 0x90 0x3 0x4 0x9>;
  1341. qcom,mdss-pan-underflow-clr = <0xff>;
  1342. qcom,mdss-pan-bl-levels = <0x1 0xff>;
  1343. qcom,mdss-pan-dsi-mode = <0x0>;
  1344. qcom,mdss-pan-dsi-h-pulse-mode = <0x0>;
  1345. qcom,mdss-pan-dsi-h-power-stop = <0x0 0x0 0x0>;
  1346. qcom,mdss-pan-dsi-bllp-power-stop = <0x1 0x1>;
  1347. qcom,mdss-pan-dsi-traffic-mode = <0x1>;
  1348. qcom,mdss-pan-dsi-dst-format = <0x3>;
  1349. qcom,mdss-pan-dsi-vc = <0x0>;
  1350. qcom,mdss-pan-dsi-rgb-swap = <0x0>;
  1351. qcom,mdss-pan-dsi-data-lanes = <0x1 0x1 0x1 0x1>;
  1352. qcom,mdss-pan-dsi-dlane-swap = <0x0>;
  1353. qcom,mdss-pan-dsi-t-clk = <0x1b 0x4>;
  1354. qcom,mdss-pan-dsi-stream = <0x0>;
  1355. qcom,mdss-pan-dsi-mdp-tr = <0x0>;
  1356. qcom,mdss-pan-dsi-dma-tr = <0x4>;
  1357. qcom,mdss-pan-dsi-framerate = <0x3c>;
  1358. qcom,panel-phy-regulatorSettings = [03 01 01 00 20 00 01];
  1359. qcom,panel-phy-timingSettings = <0x69291f00 0x5555192a 0x2a030400>;
  1360. qcom,panel-phy-strengthCtrl = [77 06];
  1361. qcom,panel-phy-bistCtrl = [00 00 b1 ff 00 00];
  1362. qcom,panel-phy-laneConfig = [00 c2 45 00 00 00 00 01 75 00 c2 45 00 00 00 00 01 75 00 c2 45 00 00 00 00 01 75 00 c2 45 00 00 00 00 01 75 00 02 45 00 00 00 00 01 97];
  1363. qcom,panel-on-cmds = [05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
  1364. qcom,on-cmds-dsi-state = "DSI_LP_MODE";
  1365. qcom,panel-off-cmds = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  1366. qcom,off-cmds-dsi-state = "DSI_LP_MODE";
  1367. };
  1368.  
  1369. qcom,mdss_dsi_toshiba_720p_video {
  1370. qcom,mdss-dsi-panel-name = "toshiba 720p video mode dsi panel";
  1371. qcom,mdss-dsi-panel-controller = <0x26>;
  1372. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  1373. qcom,mdss-dsi-panel-destination = "display_1";
  1374. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1375. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1376. qcom,mdss-dsi-stream = <0x0>;
  1377. qcom,mdss-dsi-panel-width = <0x2d0>;
  1378. qcom,mdss-dsi-panel-height = <0x500>;
  1379. qcom,mdss-dsi-h-front-porch = <0x90>;
  1380. qcom,mdss-dsi-h-back-porch = <0x20>;
  1381. qcom,mdss-dsi-h-pulse-width = <0xc>;
  1382. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1383. qcom,mdss-dsi-v-back-porch = <0x3>;
  1384. qcom,mdss-dsi-v-front-porch = <0x9>;
  1385. qcom,mdss-dsi-v-pulse-width = <0x4>;
  1386. qcom,mdss-dsi-h-left-border = <0x0>;
  1387. qcom,mdss-dsi-h-right-border = <0x0>;
  1388. qcom,mdss-dsi-v-top-border = <0x0>;
  1389. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1390. qcom,mdss-dsi-bpp = <0x18>;
  1391. qcom,mdss-dsi-underflow-color = <0xff>;
  1392. qcom,mdss-dsi-border-color = <0x0>;
  1393. qcom,mdss-dsi-on-command = [23 01 00 00 0a 00 02 b0 00 23 01 00 00 0a 00 02 b2 00 23 01 00 00 0a 00 02 b3 0c 23 01 00 00 0a 00 02 b4 02 29 01 00 00 00 00 06 c0 40 02 7f c8 08 29 01 00 00 00 00 10 c1 00 a8 00 00 00 00 00 9d 08 27 00 00 00 00 00 29 01 00 00 00 00 06 c2 00 00 09 00 00 23 01 00 00 0a 00 02 c3 04 29 01 00 00 00 00 04 c4 4d 83 00 29 01 00 00 00 00 0b c6 12 00 08 71 00 00 00 80 00 04 23 01 00 00 0a 00 02 c7 22 29 01 00 00 00 00 05 c8 4c 0c 0c 0c 29 01 00 00 00 00 0e c9 00 40 00 16 32 2e 3a 43 3e 3c 45 79 3f 29 01 00 00 00 00 0e ca 00 46 1a 23 21 1c 25 31 2d 49 5f 7f 3f 29 01 00 00 00 00 0e cb 00 4c 20 3a 42 40 47 4b 42 3e 46 7e 3f 29 01 00 00 00 00 0e cc 00 41 19 21 1d 14 18 1f 1d 25 3f 73 3f 29 01 00 00 00 00 0e cd 23 79 5a 5f 57 4c 51 51 45 3f 4b 7f 3f 29 01 00 00 00 00 0e ce 00 40 14 20 1a 0e 0e 13 08 00 05 46 1c 29 01 00 00 00 00 04 d0 6a 64 01 29 01 00 00 00 00 03 d1 77 d4 23 01 00 00 0a 00 02 d3 33 29 01 00 00 00 00 03 d5 0f 0f 29 01 00 00 00 00 07 d8 34 64 23 25 62 32 29 01 00 00 00 00 0c de 10 7b 11 0a 00 00 00 00 00 00 00 29 01 00 00 00 00 09 fd 04 55 53 00 70 ff 10 73 23 01 00 00 0a 00 02 e2 00 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00];
  1394. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  1395. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1396. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1397. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  1398. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  1399. qcom,mdss-dsi-bllp-eof-power-mode;
  1400. qcom,mdss-dsi-bllp-power-mode;
  1401. qcom,mdss-dsi-lane-0-state;
  1402. qcom,mdss-dsi-lane-1-state;
  1403. qcom,mdss-dsi-lane-2-state;
  1404. qcom,mdss-dsi-lane-3-state;
  1405. qcom,mdss-dsi-panel-timings = <0xb0231b00 0x94931e25 0x15030400>;
  1406. qcom,mdss-dsi-t-clk-post = <0x4>;
  1407. qcom,mdss-dsi-t-clk-pre = <0x1b>;
  1408. qcom,mdss-dsi-bl-min-level = <0x1>;
  1409. qcom,mdss-dsi-bl-max-level = <0xfff>;
  1410. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1411. qcom,mdss-dsi-mdp-trigger = "none";
  1412. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  1413. qcom,mdss-dsi-pan-enable-dynamic-fps;
  1414. qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode";
  1415. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>;
  1416. };
  1417.  
  1418. qcom,mdss_dsi_sharp_qhd_video {
  1419. qcom,mdss-dsi-panel-name = "sharp QHD LS043T1LE01 video mode dsi panel";
  1420. qcom,mdss-dsi-panel-controller = <0x26>;
  1421. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  1422. qcom,mdss-dsi-panel-destination = "display_1";
  1423. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1424. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1425. qcom,mdss-dsi-stream = <0x0>;
  1426. qcom,mdss-dsi-panel-width = <0x21c>;
  1427. qcom,mdss-dsi-panel-height = <0x3c0>;
  1428. qcom,mdss-dsi-h-front-porch = <0x30>;
  1429. qcom,mdss-dsi-h-back-porch = <0x50>;
  1430. qcom,mdss-dsi-h-pulse-width = <0x20>;
  1431. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1432. qcom,mdss-dsi-v-back-porch = <0xf>;
  1433. qcom,mdss-dsi-v-front-porch = <0x3>;
  1434. qcom,mdss-dsi-v-pulse-width = <0xa>;
  1435. qcom,mdss-dsi-h-left-border = <0x0>;
  1436. qcom,mdss-dsi-h-right-border = <0x0>;
  1437. qcom,mdss-dsi-v-top-border = <0x0>;
  1438. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1439. qcom,mdss-dsi-bpp = <0x18>;
  1440. qcom,mdss-dsi-color-order = "rgb_swap_bgr";
  1441. qcom,mdss-dsi-underflow-color = <0xff>;
  1442. qcom,mdss-dsi-border-color = <0x0>;
  1443. qcom,mdss-dsi-on-command = [05 01 00 00 32 00 02 01 00 05 01 00 00 0a 00 02 11 00 15 01 00 00 0a 00 02 53 2c 15 01 00 00 0a 00 02 51 ff 05 01 00 00 0a 00 02 29 00 15 01 00 00 0a 00 02 ae 03 15 01 00 00 0a 00 02 3a 77];
  1444. qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 78 00 02 10 00];
  1445. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1446. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1447. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  1448. qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
  1449. qcom,mdss-dsi-bllp-eof-power-mode;
  1450. qcom,mdss-dsi-bllp-power-mode;
  1451. qcom,mdss-dsi-lane-0-state;
  1452. qcom,mdss-dsi-lane-1-state;
  1453. qcom,mdss-dsi-panel-timings = <0x461d2000 0x393a2121 0x32030400>;
  1454. qcom,mdss-dsi-t-clk-post = <0x4>;
  1455. qcom,mdss-dsi-t-clk-pre = <0x1c>;
  1456. qcom,mdss-dsi-bl-min-level = <0x1>;
  1457. qcom,mdss-dsi-bl-max-level = <0xfff>;
  1458. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1459. qcom,mdss-dsi-mdp-trigger = "trigger_sw";
  1460. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  1461. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>;
  1462. };
  1463.  
  1464. qcom,mdss_dsi_generic_720p_cmd {
  1465. qcom,mdss-dsi-panel-name = "generic 720p cmd mode dsi panel";
  1466. qcom,mdss-dsi-panel-controller = <0x26>;
  1467. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  1468. qcom,mdss-dsi-panel-destination = "display_1";
  1469. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1470. qcom,mdss-dsi-stream = <0x0>;
  1471. qcom,mdss-dsi-panel-width = <0x300>;
  1472. qcom,mdss-dsi-panel-height = <0x500>;
  1473. qcom,mdss-dsi-h-front-porch = <0x1a>;
  1474. qcom,mdss-dsi-h-back-porch = <0x1a>;
  1475. qcom,mdss-dsi-h-pulse-width = <0x1a>;
  1476. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1477. qcom,mdss-dsi-v-back-porch = <0x2>;
  1478. qcom,mdss-dsi-v-front-porch = <0x2>;
  1479. qcom,mdss-dsi-v-pulse-width = <0x2>;
  1480. qcom,mdss-dsi-h-left-border = <0x0>;
  1481. qcom,mdss-dsi-h-right-border = <0x0>;
  1482. qcom,mdss-dsi-v-top-border = <0x0>;
  1483. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1484. qcom,mdss-dsi-bpp = <0x18>;
  1485. qcom,mdss-dsi-underflow-color = <0xff>;
  1486. qcom,mdss-dsi-border-color = <0x0>;
  1487. qcom,mdss-dsi-on-command = [05 01 00 00 78 00 01 11 15 01 00 00 0a 00 02 36 00 05 01 00 00 0a 00 01 29 15 01 00 00 0a 00 02 53 24 15 01 00 00 0a 00 02 35 00];
  1488. qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 01 34 05 01 00 00 78 00 01 10 05 01 00 00 78 00 01 28 15 01 00 00 0a 00 02 53 00];
  1489. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1490. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1491. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  1492. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  1493. qcom,mdss-dsi-bllp-eof-power-mode;
  1494. qcom,mdss-dsi-bllp-power-mode;
  1495. qcom,mdss-dsi-lane-0-state;
  1496. qcom,mdss-dsi-lane-1-state;
  1497. qcom,mdss-dsi-lane-2-state;
  1498. qcom,mdss-dsi-lane-3-state;
  1499. qcom,mdss-dsi-te-pin-select = <0x1>;
  1500. qcom,mdss-dsi-wr-mem-start = <0x2c>;
  1501. qcom,mdss-dsi-wr-mem-continue = <0x3c>;
  1502. qcom,mdss-dsi-te-dcs-command = <0x1>;
  1503. qcom,mdss-dsi-te-check-enable;
  1504. qcom,mdss-dsi-te-using-te-pin;
  1505. qcom,mdss-dsi-panel-timings = <0x6e261b00 0x35342028 0x17030400>;
  1506. qcom,mdss-dsi-t-clk-post = <0x20>;
  1507. qcom,mdss-dsi-t-clk-pre = <0x2a>;
  1508. qcom,mdss-dsi-bl-min-level = <0x1>;
  1509. qcom,mdss-dsi-bl-max-level = <0xff>;
  1510. qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x64>;
  1511. qcom,mdss-dsi-bl-pmic-bank-select = <0x7>;
  1512. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1513. qcom,mdss-dsi-mdp-trigger = "none";
  1514. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
  1515. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>;
  1516. qcom,panel-roi-alignment = <0x2 0x2 0x2 0x2 0x0 0x0>;
  1517. qcom,partial-update-enabled;
  1518. qcom,cont-splash-enabled;
  1519. };
  1520.  
  1521. qcom,mdss_dsi_jdi_1080p_video {
  1522. qcom,mdss-dsi-panel-name = "jdi 1080p video mode dsi panel";
  1523. qcom,mdss-dsi-panel-controller = <0x26>;
  1524. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  1525. qcom,mdss-dsi-panel-destination = "display_1";
  1526. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1527. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1528. qcom,mdss-dsi-stream = <0x0>;
  1529. qcom,mdss-dsi-panel-width = <0x438>;
  1530. qcom,mdss-dsi-panel-height = <0x780>;
  1531. qcom,mdss-dsi-h-front-porch = <0x60>;
  1532. qcom,mdss-dsi-h-back-porch = <0x40>;
  1533. qcom,mdss-dsi-h-pulse-width = <0x10>;
  1534. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1535. qcom,mdss-dsi-v-back-porch = <0x10>;
  1536. qcom,mdss-dsi-v-front-porch = <0x4>;
  1537. qcom,mdss-dsi-v-pulse-width = <0x1>;
  1538. qcom,mdss-dsi-h-left-border = <0x0>;
  1539. qcom,mdss-dsi-h-right-border = <0x0>;
  1540. qcom,mdss-dsi-v-top-border = <0x0>;
  1541. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1542. qcom,mdss-dsi-bpp = <0x18>;
  1543. qcom,mdss-dsi-underflow-color = <0xff>;
  1544. qcom,mdss-dsi-border-color = <0x0>;
  1545. qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 55 00 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 29 00 05 01 00 00 78 00 02 11 00];
  1546. qcom,mdss-dsi-off-command = [05 01 00 00 02 00 02 28 00 05 01 00 00 79 00 02 10 00];
  1547. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1548. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1549. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  1550. qcom,mdss-dsi-traffic-mode = "burst_mode";
  1551. qcom,mdss-dsi-bllp-eof-power-mode;
  1552. qcom,mdss-dsi-bllp-power-mode;
  1553. qcom,mdss-dsi-lane-0-state;
  1554. qcom,mdss-dsi-lane-1-state;
  1555. qcom,mdss-dsi-lane-2-state;
  1556. qcom,mdss-dsi-lane-3-state;
  1557. qcom,mdss-dsi-panel-timings = <0xe7362400 0x666a2a3a 0x2d030400>;
  1558. qcom,mdss-dsi-t-clk-post = <0x4>;
  1559. qcom,mdss-dsi-t-clk-pre = <0x1b>;
  1560. qcom,mdss-dsi-bl-min-level = <0x1>;
  1561. qcom,mdss-dsi-bl-max-level = <0xfff>;
  1562. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1563. qcom,mdss-dsi-mdp-trigger = "none";
  1564. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  1565. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>;
  1566. qcom,mdss-pan-physical-width-dimension = <0x3d>;
  1567. qcom,mdss-pan-physical-height-dimension = <0x6e>;
  1568. qcom,cont-splash-enabled;
  1569. };
  1570.  
  1571. qcom,dsi_jdi_qhd_video_0 {
  1572. qcom,mdss-dsi-panel-name = "Dual 0 video mode dsi panel";
  1573. qcom,mdss-dsi-panel-controller = <0x26>;
  1574. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  1575. qcom,mdss-dsi-panel-destination = "display_1";
  1576. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1577. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1578. qcom,mdss-dsi-stream = <0x0>;
  1579. qcom,mdss-dsi-panel-width = <0x500>;
  1580. qcom,mdss-dsi-panel-height = <0x5a0>;
  1581. qcom,mdss-dsi-h-front-porch = <0x78>;
  1582. qcom,mdss-dsi-h-back-porch = <0x2c>;
  1583. qcom,mdss-dsi-h-pulse-width = <0x10>;
  1584. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1585. qcom,mdss-dsi-v-back-porch = <0x4>;
  1586. qcom,mdss-dsi-v-front-porch = <0x8>;
  1587. qcom,mdss-dsi-v-pulse-width = <0x4>;
  1588. qcom,mdss-dsi-h-left-border = <0x0>;
  1589. qcom,mdss-dsi-h-right-border = <0x0>;
  1590. qcom,mdss-dsi-v-top-border = <0x0>;
  1591. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1592. qcom,mdss-dsi-bpp = <0x18>;
  1593. qcom,mdss-dsi-underflow-color = <0xff>;
  1594. qcom,mdss-dsi-border-color = <0x0>;
  1595. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  1596. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  1597. qcom,mdss-dsi-bllp-eof-power-mode;
  1598. qcom,mdss-dsi-bllp-power-mode;
  1599. qcom,mdss-dsi-panel-broadcast-mode;
  1600. qcom,mdss-dsi-lane-0-state;
  1601. qcom,mdss-dsi-lane-1-state;
  1602. qcom,mdss-dsi-lane-2-state;
  1603. qcom,mdss-dsi-lane-3-state;
  1604. qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>;
  1605. qcom,mdss-dsi-t-clk-post = <0x3>;
  1606. qcom,mdss-dsi-t-clk-pre = <0x27>;
  1607. qcom,mdss-dsi-bl-max-level = <0xfff>;
  1608. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1609. qcom,mdss-dsi-mdp-trigger = "none";
  1610. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
  1611. qcom,mdss-dsi-on-command = [05 01 00 00 0a 00 01 00 15 01 00 00 0a 00 02 3a 77 39 01 00 00 0a 00 05 2a 00 00 04 ff 39 01 00 00 0a 00 05 2b 00 00 05 9f 15 01 00 00 0a 00 02 35 00 39 01 00 00 0a 00 03 44 00 00 15 01 00 00 0a 00 02 51 ff 15 01 00 00 0a 00 02 53 24 15 01 00 00 0a 00 02 55 00 05 01 00 00 78 00 01 11 23 01 00 00 0a 00 02 b0 00 29 01 00 00 0a 00 02 b3 14 29 01 00 00 0a 00 14 ce 7d 40 48 56 67 78 88 98 a7 b5 c3 d1 de e9 f2 fa ff 04 00 23 01 00 00 0a 00 02 b0 03 05 01 00 00 10 00 01 29];
  1612. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1613. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  1614. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1615. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>;
  1616. };
  1617.  
  1618. qcom,dsi_jdi_qhd_video_1 {
  1619. qcom,mdss-dsi-panel-name = "Dual 1 video mode dsi panel";
  1620. qcom,mdss-dsi-panel-controller = <0x25>;
  1621. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  1622. qcom,mdss-dsi-panel-destination = "display_2";
  1623. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1624. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1625. qcom,mdss-dsi-stream = <0x0>;
  1626. qcom,mdss-dsi-panel-width = <0x500>;
  1627. qcom,mdss-dsi-panel-height = <0x5a0>;
  1628. qcom,mdss-dsi-h-front-porch = <0x78>;
  1629. qcom,mdss-dsi-h-back-porch = <0x2c>;
  1630. qcom,mdss-dsi-h-pulse-width = <0x10>;
  1631. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1632. qcom,mdss-dsi-v-back-porch = <0x4>;
  1633. qcom,mdss-dsi-v-front-porch = <0x8>;
  1634. qcom,mdss-dsi-v-pulse-width = <0x4>;
  1635. qcom,mdss-dsi-h-left-border = <0x0>;
  1636. qcom,mdss-dsi-h-right-border = <0x0>;
  1637. qcom,mdss-dsi-v-top-border = <0x0>;
  1638. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1639. qcom,mdss-dsi-bpp = <0x18>;
  1640. qcom,mdss-dsi-underflow-color = <0xff>;
  1641. qcom,mdss-dsi-border-color = <0x0>;
  1642. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  1643. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  1644. qcom,mdss-dsi-bllp-eof-power-mode;
  1645. qcom,mdss-dsi-bllp-power-mode;
  1646. qcom,mdss-dsi-lane-0-state;
  1647. qcom,mdss-dsi-lane-1-state;
  1648. qcom,mdss-dsi-lane-2-state;
  1649. qcom,mdss-dsi-lane-3-state;
  1650. qcom,mdss-dsi-panel-broadcast-mode;
  1651. qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>;
  1652. qcom,mdss-dsi-t-clk-post = <0x3>;
  1653. qcom,mdss-dsi-t-clk-pre = <0x27>;
  1654. qcom,mdss-dsi-bl-min-level = <0x1>;
  1655. qcom,mdss-dsi-bl-max-level = <0xfff>;
  1656. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1657. qcom,mdss-dsi-mdp-trigger = "none";
  1658. qcom,mdss-dsi-on-command = [05 01 00 00 0a 00 01 00 15 01 00 00 0a 00 02 3a 77 39 01 00 00 0a 00 05 2a 00 00 04 ff 39 01 00 00 0a 00 05 2b 00 00 05 9f 15 01 00 00 0a 00 02 35 00 39 01 00 00 0a 00 03 44 00 00 15 01 00 00 0a 00 02 51 ff 15 01 00 00 0a 00 02 53 24 15 01 00 00 0a 00 02 55 00 05 01 00 00 78 00 01 11 23 01 00 00 0a 00 02 b0 00 29 01 00 00 0a 00 02 b3 14 29 01 00 00 0a 00 14 ce 7d 40 48 56 67 78 88 98 a7 b5 c3 d1 de e9 f2 fa ff 04 00 23 01 00 00 0a 00 02 b0 03 05 01 00 00 10 00 01 29];
  1659. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1660. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  1661. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1662. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>;
  1663. };
  1664.  
  1665. qcom,mdss_dsi_jdi_qhd_dualmipi0_cmd {
  1666. qcom,mdss-dsi-panel-name = "Dual 0 cmd mode dsi panel";
  1667. qcom,mdss-dsi-panel-controller = <0x26>;
  1668. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  1669. qcom,mdss-dsi-panel-destination = "display_1";
  1670. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1671. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1672. qcom,mdss-dsi-stream = <0x0>;
  1673. qcom,mdss-dsi-panel-width = <0x500>;
  1674. qcom,mdss-dsi-panel-height = <0x5a0>;
  1675. qcom,mdss-dsi-h-front-porch = <0x78>;
  1676. qcom,mdss-dsi-h-back-porch = <0x2c>;
  1677. qcom,mdss-dsi-h-pulse-width = <0x10>;
  1678. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1679. qcom,mdss-dsi-v-back-porch = <0x4>;
  1680. qcom,mdss-dsi-v-front-porch = <0x8>;
  1681. qcom,mdss-dsi-v-pulse-width = <0x4>;
  1682. qcom,mdss-dsi-h-left-border = <0x0>;
  1683. qcom,mdss-dsi-h-right-border = <0x0>;
  1684. qcom,mdss-dsi-v-top-border = <0x0>;
  1685. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1686. qcom,mdss-dsi-bpp = <0x18>;
  1687. qcom,mdss-dsi-color-order = "rgb_swap_rgb";
  1688. qcom,mdss-dsi-underflow-color = <0xff>;
  1689. qcom,mdss-dsi-border-color = <0x0>;
  1690. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  1691. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  1692. qcom,mdss-dsi-lane-map = "lane_map_0123";
  1693. qcom,mdss-dsi-bllp-eof-power-mode;
  1694. qcom,mdss-dsi-bllp-power-mode;
  1695. qcom,mdss-dsi-panel-broadcast-mode;
  1696. qcom,mdss-dsi-lane-0-state;
  1697. qcom,mdss-dsi-lane-1-state;
  1698. qcom,mdss-dsi-lane-2-state;
  1699. qcom,mdss-dsi-lane-3-state;
  1700. qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>;
  1701. qcom,mdss-dsi-reset-sequence = <0x1 0xc8 0x0 0xc8 0x1 0x14>;
  1702. qcom,mdss-dsi-t-clk-post = <0x3>;
  1703. qcom,mdss-dsi-t-clk-pre = <0x27>;
  1704. qcom,mdss-dsi-bl-max-level = <0xfff>;
  1705. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1706. qcom,mdss-dsi-mdp-trigger = "none";
  1707. qcom,mdss-dsi-te-pin-select = <0x1>;
  1708. qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line = <0x2c>;
  1709. qcom,mdss-dsi-te-v-sync-continues-lines = <0x3c>;
  1710. qcom,mdss-dsi-te-dcs-command = <0x1>;
  1711. qcom,mdss-dsi-te-check-enable;
  1712. qcom,mdss-dsi-te-using-te-pin;
  1713. qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;
  1714. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1715. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  1716. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1717. };
  1718.  
  1719. qcom,mdss_dsi_jdi_qhd_dualmipi1_cmd {
  1720. qcom,mdss-dsi-panel-name = "Dual 1 cmd mode dsi panel";
  1721. qcom,mdss-dsi-panel-controller = <0x25>;
  1722. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  1723. qcom,mdss-dsi-panel-destination = "display_2";
  1724. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1725. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1726. qcom,mdss-dsi-stream = <0x0>;
  1727. qcom,mdss-dsi-panel-width = <0x500>;
  1728. qcom,mdss-dsi-panel-height = <0x5a0>;
  1729. qcom,mdss-dsi-h-front-porch = <0x78>;
  1730. qcom,mdss-dsi-h-back-porch = <0x2c>;
  1731. qcom,mdss-dsi-h-pulse-width = <0x10>;
  1732. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1733. qcom,mdss-dsi-v-back-porch = <0x4>;
  1734. qcom,mdss-dsi-v-front-porch = <0x8>;
  1735. qcom,mdss-dsi-v-pulse-width = <0x4>;
  1736. qcom,mdss-dsi-h-left-border = <0x0>;
  1737. qcom,mdss-dsi-h-right-border = <0x0>;
  1738. qcom,mdss-dsi-v-top-border = <0x0>;
  1739. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1740. qcom,mdss-dsi-bpp = <0x18>;
  1741. qcom,mdss-dsi-color-order = "rgb_swap_rgb";
  1742. qcom,mdss-dsi-underflow-color = <0xff>;
  1743. qcom,mdss-dsi-border-color = <0x0>;
  1744. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  1745. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  1746. qcom,mdss-dsi-lane-map = "lane_map_0123";
  1747. qcom,mdss-dsi-bllp-eof-power-mode;
  1748. qcom,mdss-dsi-bllp-power-mode;
  1749. qcom,mdss-dsi-panel-broadcast-mode;
  1750. qcom,mdss-dsi-lane-0-state;
  1751. qcom,mdss-dsi-lane-1-state;
  1752. qcom,mdss-dsi-lane-2-state;
  1753. qcom,mdss-dsi-lane-3-state;
  1754. qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>;
  1755. qcom,mdss-dsi-reset-sequence = <0x1 0xc8 0x0 0xc8 0x1 0x14>;
  1756. qcom,mdss-dsi-t-clk-post = <0x3>;
  1757. qcom,mdss-dsi-t-clk-pre = <0x27>;
  1758. qcom,mdss-dsi-bl-max-level = <0xfff>;
  1759. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  1760. qcom,mdss-dsi-mdp-trigger = "none";
  1761. qcom,mdss-dsi-te-pin-select = <0x1>;
  1762. qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line = <0x2c>;
  1763. qcom,mdss-dsi-te-v-sync-continues-lines = <0x3c>;
  1764. qcom,mdss-dsi-te-dcs-command = <0x1>;
  1765. qcom,mdss-dsi-te-check-enable;
  1766. qcom,mdss-dsi-te-using-te-pin;
  1767. qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;
  1768. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1769. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  1770. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1771. };
  1772.  
  1773. qcom,mdss_dsi_otm1902b_1080p_cmd {
  1774. qcom,mdss-dsi-panel-name = "otm1902b 1080p cmd mode dsi panel";
  1775. qcom,mdss-dsi-panel-controller = <0x26>;
  1776. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  1777. qcom,mdss-dsi-panel-destination = "display_1";
  1778. qcom,mdss-dsi-panel-framerate = <0x3c>;
  1779. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  1780. qcom,mdss-dsi-stream = <0x0>;
  1781. qcom,mdss-dsi-panel-width = <0x438>;
  1782. qcom,mdss-dsi-panel-height = <0x780>;
  1783. qcom,mdss-dsi-h-front-porch = <0x90>;
  1784. qcom,mdss-dsi-h-back-porch = <0x20>;
  1785. qcom,mdss-dsi-h-pulse-width = <0xc>;
  1786. qcom,mdss-dsi-h-sync-skew = <0x0>;
  1787. qcom,mdss-dsi-v-back-porch = <0x3>;
  1788. qcom,mdss-dsi-v-front-porch = <0x9>;
  1789. qcom,mdss-dsi-v-pulse-width = <0x4>;
  1790. qcom,mdss-dsi-h-left-border = <0x0>;
  1791. qcom,mdss-dsi-h-right-border = <0x0>;
  1792. qcom,mdss-dsi-v-top-border = <0x0>;
  1793. qcom,mdss-dsi-v-bottom-border = <0x0>;
  1794. qcom,mdss-dsi-bpp = <0x18>;
  1795. qcom,mdss-dsi-underflow-color = <0xff>;
  1796. qcom,mdss-dsi-border-color = <0x0>;
  1797. qcom,mdss-dsi-on-command = <0x29010000 0x200 0x290100 0x10005 0xff190201 0x290100 0x10002 0x802901 0x100 0x3ff1902 0x15010000 0x1000200 0xb0290100 0x10005 0xcaff025f 0x40150100 0x10002 0x532c0501 0x3200 0x2110005 0x1000060 0x22900>;
  1798. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 64 00 02 10 00];
  1799. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  1800. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  1801. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  1802. qcom,mdss-dsi-traffic-mode = "burst_mode";
  1803. qcom,mdss-dsi-lane-map;
  1804. qcom,mdss-dsi-bllp-eof-power-mode;
  1805. qcom,mdss-dsi-bllp-power-mode;
  1806. qcom,mdss-pan-dsi-bllp-power-stop;
  1807. qcom,mdss-pan-dsi-h-power-stop;
  1808. qcom,mdss-dsi-lane-0-state;
  1809. qcom,mdss-dsi-lane-1-state;
  1810. qcom,mdss-dsi-lane-2-state;
  1811. qcom,mdss-dsi-lane-3-state;
  1812. qcom,mdss-dsi-te-pin-select = <0x1>;
  1813. qcom,mdss-dsi-wr-mem-start = <0x2c>;
  1814. qcom,mdss-dsi-wr-mem-continue = <0x3c>;
  1815. qcom,mdss-dsi-te-dcs-command = <0x1>;
  1816. qcom,mdss-dsi-te-check-enable;
  1817. qcom,mdss-dsi-te-using-te-pin;
  1818. qcom,mdss-dsi-panel-timings = <0xd5322200 0x60642634 0x29030400>;
  1819. qcom,mdss-dsi-t-clk-post = <0x1e>;
  1820. qcom,mdss-dsi-t-clk-pre = <0x38>;
  1821. qcom,mdss-dsi-bl-min-level = <0x0>;
  1822. qcom,mdss-dsi-bl-max-level = <0xff>;
  1823. qcom,mdss-dsi-dma-trigger = <0x4>;
  1824. qcom,mdss-dsi-mdp-trigger = <0x0>;
  1825. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
  1826. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x2 0x1 0xa>;
  1827. qcom,mdss-pan-physical-width-dimension = <0x3e>;
  1828. qcom,mdss-pan-physical-height-dimension = <0x6e>;
  1829. qcom,cont-splash-enabled;
  1830. linux,phandle = <0x2b>;
  1831. phandle = <0x2b>;
  1832. };
  1833. };
  1834.  
  1835. qcom,mdss_dsi@fd922800 {
  1836. compatible = "qcom,mdss-dsi-ctrl";
  1837. label = "MDSS DSI CTRL->0";
  1838. cell-index = <0x0>;
  1839. reg = <0xfd922800 0x1f8 0xfd922b00 0x2b0 0xfdf30000 0x108>;
  1840. reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
  1841. vdd-supply = <0xd>;
  1842. vddio-supply = <0x2>;
  1843. vdda-supply = <0x27>;
  1844. qcom,mdss-fb-map = <0x28>;
  1845. qcom,mdss-mdp = <0x29>;
  1846. qcom,platform-reset-gpio = <0x2a 0x13 0x0>;
  1847. qcom,platform-enable-gpio = <0x5 0x19 0x0>;
  1848. qcom,platform-te-gpio = <0x5 0xc 0x0>;
  1849. qcom,platform-strength-ctrl = [ff 06];
  1850. qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
  1851. qcom,platform-regulator-settings = [07 09 03 00 20 00 01];
  1852. qcom,platform-lane-config = [00 00 00 00 00 00 00 01 97 00 00 00 00 05 00 00 01 97 00 00 00 00 0a 00 00 01 97 00 00 00 00 0f 00 00 01 97 00 c0 00 00 00 00 00 01 bb];
  1853. qcom,dsi-pref-prim-pan = <0x2b>;
  1854. linux,phandle = <0x26>;
  1855. phandle = <0x26>;
  1856.  
  1857. qcom,platform-supply-entry1 {
  1858. qcom,supply-name = "vdd";
  1859. qcom,supply-min-voltage = <0x2dc6c0>;
  1860. qcom,supply-max-voltage = <0x2dc6c0>;
  1861. qcom,supply-enable-load = <0x186a0>;
  1862. qcom,supply-disable-load = <0x64>;
  1863. qcom,supply-pre-on-sleep = <0x0>;
  1864. qcom,supply-post-on-sleep = <0x14>;
  1865. qcom,supply-pre-off-sleep = <0x0>;
  1866. qcom,supply-post-off-sleep = <0x0>;
  1867. };
  1868.  
  1869. qcom,platform-supply-entry2 {
  1870. qcom,supply-name = "vddio";
  1871. qcom,supply-min-voltage = <0x1b7740>;
  1872. qcom,supply-max-voltage = <0x1b7740>;
  1873. qcom,supply-enable-load = <0x186a0>;
  1874. qcom,supply-disable-load = <0x64>;
  1875. qcom,supply-pre-on-sleep = <0x0>;
  1876. qcom,supply-post-on-sleep = <0x14>;
  1877. qcom,supply-pre-off-sleep = <0x0>;
  1878. qcom,supply-post-off-sleep = <0x0>;
  1879. };
  1880.  
  1881. qcom,platform-supply-entry3 {
  1882. qcom,supply-name = "vdda";
  1883. qcom,supply-min-voltage = <0x124f80>;
  1884. qcom,supply-max-voltage = <0x124f80>;
  1885. qcom,supply-enable-load = <0x186a0>;
  1886. qcom,supply-disable-load = <0x64>;
  1887. qcom,supply-pre-on-sleep = <0x0>;
  1888. qcom,supply-post-on-sleep = <0x0>;
  1889. qcom,supply-pre-off-sleep = <0x0>;
  1890. qcom,supply-post-off-sleep = <0x0>;
  1891. };
  1892. };
  1893.  
  1894. qcom,mdss_dsi@fd922e00 {
  1895. compatible = "qcom,mdss-dsi-ctrl";
  1896. status = "disabled";
  1897. label = "MDSS DSI CTRL->1";
  1898. cell-index = <0x1>;
  1899. reg = <0xfd922e00 0x1f8 0xfd923100 0x2b0 0xfdf30000 0x108>;
  1900. reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
  1901. vdd-supply = <0xd>;
  1902. vddio-supply = <0x2>;
  1903. vdda-supply = <0x27>;
  1904. qcom,mdss-fb-map = <0x28>;
  1905. qcom,mdss-mdp = <0x29>;
  1906. qcom,platform-strength-ctrl = [ff 06];
  1907. qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
  1908. qcom,platform-regulator-settings = [07 09 03 00 20 00 01];
  1909. qcom,platform-lane-config = [00 00 00 00 00 00 00 01 97 00 00 00 00 05 00 00 01 97 00 00 00 00 0a 00 00 01 97 00 00 00 00 0f 00 00 01 97 00 c0 00 00 00 00 00 01 bb];
  1910. linux,phandle = <0x25>;
  1911. phandle = <0x25>;
  1912.  
  1913. qcom,platform-supply-entry1 {
  1914. qcom,supply-name = "vdd";
  1915. qcom,supply-min-voltage = <0x2dc6c0>;
  1916. qcom,supply-max-voltage = <0x2dc6c0>;
  1917. qcom,supply-enable-load = <0x186a0>;
  1918. qcom,supply-disable-load = <0x64>;
  1919. qcom,supply-pre-on-sleep = <0x0>;
  1920. qcom,supply-post-on-sleep = <0x14>;
  1921. qcom,supply-pre-off-sleep = <0x0>;
  1922. qcom,supply-post-off-sleep = <0x0>;
  1923. };
  1924.  
  1925. qcom,platform-supply-entry2 {
  1926. qcom,supply-name = "vddio";
  1927. qcom,supply-min-voltage = <0x1b7740>;
  1928. qcom,supply-max-voltage = <0x1b7740>;
  1929. qcom,supply-enable-load = <0x186a0>;
  1930. qcom,supply-disable-load = <0x64>;
  1931. qcom,supply-pre-on-sleep = <0x0>;
  1932. qcom,supply-post-on-sleep = <0x14>;
  1933. qcom,supply-pre-off-sleep = <0x0>;
  1934. qcom,supply-post-off-sleep = <0x0>;
  1935. };
  1936.  
  1937. qcom,platform-supply-entry3 {
  1938. qcom,supply-name = "vdda";
  1939. qcom,supply-min-voltage = <0x124f80>;
  1940. qcom,supply-max-voltage = <0x124f80>;
  1941. qcom,supply-enable-load = <0x186a0>;
  1942. qcom,supply-disable-load = <0x64>;
  1943. qcom,supply-pre-on-sleep = <0x0>;
  1944. qcom,supply-post-on-sleep = <0x0>;
  1945. qcom,supply-pre-off-sleep = <0x0>;
  1946. qcom,supply-post-off-sleep = <0x0>;
  1947. };
  1948. };
  1949.  
  1950. qcom,hdmi_tx@fd922100 {
  1951. cell-index = <0x0>;
  1952. compatible = "qcom,hdmi-tx";
  1953. reg = <0xfd922100 0x370 0xfd922500 0x7c 0xfc4b8000 0x60f0>;
  1954. reg-names = "core_physical", "phy_physical", "qfprom_physical";
  1955. hpd-gdsc-supply = <0x22>;
  1956. hpd-5v-supply = <0x2c>;
  1957. core-vdda-supply = <0x2>;
  1958. core-vcc-supply = <0x2d>;
  1959. qcom,hdmi-tx-supply-names = "hpd-gdsc", "hpd-5v", "core-vdda", "core-vcc";
  1960. qcom,hdmi-tx-min-voltage-level = <0x0 0x0 0x1b7740 0x1b7740>;
  1961. qcom,hdmi-tx-max-voltage-level = <0x0 0x0 0x1b7740 0x1b7740>;
  1962. qcom,hdmi-tx-peak-current = <0x0 0x0 0x493e0 0x0>;
  1963. qcom,hdmi-tx-cec = <0x5 0x1f 0x0>;
  1964. qcom,hdmi-tx-ddc-clk = <0x5 0x20 0x0>;
  1965. qcom,hdmi-tx-ddc-data = <0x5 0x21 0x0>;
  1966. qcom,hdmi-tx-hpd = <0x5 0x22 0x0>;
  1967. qcom,mdss-fb-map = <0x2e>;
  1968. status = "disabled";
  1969.  
  1970. qcom,msm-hdmi-audio-rx {
  1971. compatible = "qcom,msm-hdmi-audio-codec-rx";
  1972. };
  1973. };
  1974.  
  1975. qcom,mdss_wb_panel {
  1976. compatible = "qcom,mdss_wb";
  1977. qcom,mdss_pan_res = <0x780 0x438>;
  1978. qcom,mdss_pan_bpp = <0x18>;
  1979. qcom,mdss-fb-map = <0x2f>;
  1980. };
  1981.  
  1982. qcom,mdss_edp@fd923400 {
  1983. compatible = "qcom,mdss-edp";
  1984. reg = <0xfd923400 0x700 0xfd8c2000 0x1000>;
  1985. reg-names = "edp_base", "mmss_cc_base";
  1986. vdda-supply = <0x2>;
  1987. gpio-panel-en = <0x5 0x3a 0x0>;
  1988. qcom,mdss-fb-map = <0x28>;
  1989. gpio-panel-hpd = <0x5 0x66 0x0>;
  1990. };
  1991.  
  1992. qcom,smp2p-modem {
  1993. compatible = "qcom,smp2p";
  1994. reg = <0xf9011008 0x4>;
  1995. qcom,remote-pid = <0x1>;
  1996. qcom,irq-bitmask = <0x4000>;
  1997. interrupts = <0x0 0x1b 0x1>;
  1998. };
  1999.  
  2000. qcom,smp2p-adsp {
  2001. compatible = "qcom,smp2p";
  2002. reg = <0xf9011008 0x4>;
  2003. qcom,remote-pid = <0x2>;
  2004. qcom,irq-bitmask = <0x400>;
  2005. interrupts = <0x0 0x9e 0x1>;
  2006. };
  2007.  
  2008. qcom,smp2p-wcnss {
  2009. compatible = "qcom,smp2p";
  2010. reg = <0xf9011008 0x4>;
  2011. qcom,remote-pid = <0x4>;
  2012. qcom,irq-bitmask = <0x40000>;
  2013. interrupts = <0x0 0x8f 0x1>;
  2014. };
  2015.  
  2016. qcom,smp2pgpio-smp2p-7-in {
  2017. compatible = "qcom,smp2pgpio";
  2018. qcom,entry-name = "smp2p";
  2019. qcom,remote-pid = <0x7>;
  2020. qcom,is-inbound;
  2021. gpio-controller;
  2022. #gpio-cells = <0x2>;
  2023. interrupt-controller;
  2024. #interrupt-cells = <0x2>;
  2025. linux,phandle = <0x30>;
  2026. phandle = <0x30>;
  2027. };
  2028.  
  2029. qcom,smp2pgpio_test_smp2p_7_in {
  2030. compatible = "qcom,smp2pgpio_test_smp2p_7_in";
  2031. gpios = <0x30 0x0 0x0>;
  2032. };
  2033.  
  2034. qcom,smp2pgpio-smp2p-7-out {
  2035. compatible = "qcom,smp2pgpio";
  2036. qcom,entry-name = "smp2p";
  2037. qcom,remote-pid = <0x7>;
  2038. gpio-controller;
  2039. #gpio-cells = <0x2>;
  2040. interrupt-controller;
  2041. #interrupt-cells = <0x2>;
  2042. linux,phandle = <0x31>;
  2043. phandle = <0x31>;
  2044. };
  2045.  
  2046. qcom,smp2pgpio_test_smp2p_7_out {
  2047. compatible = "qcom,smp2pgpio_test_smp2p_7_out";
  2048. gpios = <0x31 0x0 0x0>;
  2049. };
  2050.  
  2051. qcom,smp2pgpio-smp2p-1-in {
  2052. compatible = "qcom,smp2pgpio";
  2053. qcom,entry-name = "smp2p";
  2054. qcom,remote-pid = <0x1>;
  2055. qcom,is-inbound;
  2056. gpio-controller;
  2057. #gpio-cells = <0x2>;
  2058. interrupt-controller;
  2059. #interrupt-cells = <0x2>;
  2060. linux,phandle = <0x32>;
  2061. phandle = <0x32>;
  2062. };
  2063.  
  2064. qcom,smp2pgpio_test_smp2p_1_in {
  2065. compatible = "qcom,smp2pgpio_test_smp2p_1_in";
  2066. gpios = <0x32 0x0 0x0>;
  2067. };
  2068.  
  2069. qcom,smp2pgpio-smp2p-1-out {
  2070. compatible = "qcom,smp2pgpio";
  2071. qcom,entry-name = "smp2p";
  2072. qcom,remote-pid = <0x1>;
  2073. gpio-controller;
  2074. #gpio-cells = <0x2>;
  2075. interrupt-controller;
  2076. #interrupt-cells = <0x2>;
  2077. linux,phandle = <0x33>;
  2078. phandle = <0x33>;
  2079. };
  2080.  
  2081. qcom,smp2pgpio_test_smp2p_1_out {
  2082. compatible = "qcom,smp2pgpio_test_smp2p_1_out";
  2083. gpios = <0x33 0x0 0x0>;
  2084. };
  2085.  
  2086. qcom,smp2pgpio-ssr-smp2p-1-in {
  2087. compatible = "qcom,smp2pgpio";
  2088. qcom,entry-name = "slave-kernel";
  2089. qcom,remote-pid = <0x1>;
  2090. qcom,is-inbound;
  2091. gpio-controller;
  2092. #gpio-cells = <0x2>;
  2093. interrupt-controller;
  2094. #interrupt-cells = <0x2>;
  2095. linux,phandle = <0x69>;
  2096. phandle = <0x69>;
  2097. };
  2098.  
  2099. qcom,smp2pgpio-ssr-smp2p-1-out {
  2100. compatible = "qcom,smp2pgpio";
  2101. qcom,entry-name = "master-kernel";
  2102. qcom,remote-pid = <0x1>;
  2103. gpio-controller;
  2104. #gpio-cells = <0x2>;
  2105. interrupt-controller;
  2106. #interrupt-cells = <0x2>;
  2107. linux,phandle = <0x6a>;
  2108. phandle = <0x6a>;
  2109. };
  2110.  
  2111. qcom,smp2pgpio-smp2p-2-in {
  2112. compatible = "qcom,smp2pgpio";
  2113. qcom,entry-name = "smp2p";
  2114. qcom,remote-pid = <0x2>;
  2115. qcom,is-inbound;
  2116. gpio-controller;
  2117. #gpio-cells = <0x2>;
  2118. interrupt-controller;
  2119. #interrupt-cells = <0x2>;
  2120. linux,phandle = <0x34>;
  2121. phandle = <0x34>;
  2122. };
  2123.  
  2124. qcom,smp2pgpio_test_smp2p_2_in {
  2125. compatible = "qcom,smp2pgpio_test_smp2p_2_in";
  2126. gpios = <0x34 0x0 0x0>;
  2127. };
  2128.  
  2129. qcom,smp2pgpio-smp2p-2-out {
  2130. compatible = "qcom,smp2pgpio";
  2131. qcom,entry-name = "smp2p";
  2132. qcom,remote-pid = <0x2>;
  2133. gpio-controller;
  2134. #gpio-cells = <0x2>;
  2135. interrupt-controller;
  2136. #interrupt-cells = <0x2>;
  2137. linux,phandle = <0x35>;
  2138. phandle = <0x35>;
  2139. };
  2140.  
  2141. qcom,smp2pgpio_test_smp2p_2_out {
  2142. compatible = "qcom,smp2pgpio_test_smp2p_2_out";
  2143. gpios = <0x35 0x0 0x0>;
  2144. };
  2145.  
  2146. qcom,smp2pgpio-ssr-smp2p-2-in {
  2147. compatible = "qcom,smp2pgpio";
  2148. qcom,entry-name = "slave-kernel";
  2149. qcom,remote-pid = <0x2>;
  2150. qcom,is-inbound;
  2151. gpio-controller;
  2152. #gpio-cells = <0x2>;
  2153. interrupt-controller;
  2154. #interrupt-cells = <0x2>;
  2155. linux,phandle = <0x65>;
  2156. phandle = <0x65>;
  2157. };
  2158.  
  2159. qcom,smp2pgpio-ssr-smp2p-2-out {
  2160. compatible = "qcom,smp2pgpio";
  2161. qcom,entry-name = "master-kernel";
  2162. qcom,remote-pid = <0x2>;
  2163. gpio-controller;
  2164. #gpio-cells = <0x2>;
  2165. interrupt-controller;
  2166. #interrupt-cells = <0x2>;
  2167. linux,phandle = <0x66>;
  2168. phandle = <0x66>;
  2169. };
  2170.  
  2171. qcom,smp2pgpio-smp2p-4-in {
  2172. compatible = "qcom,smp2pgpio";
  2173. qcom,entry-name = "smp2p";
  2174. qcom,remote-pid = <0x4>;
  2175. qcom,is-inbound;
  2176. gpio-controller;
  2177. #gpio-cells = <0x2>;
  2178. interrupt-controller;
  2179. #interrupt-cells = <0x2>;
  2180. linux,phandle = <0x36>;
  2181. phandle = <0x36>;
  2182. };
  2183.  
  2184. qcom,smp2pgpio_test_smp2p_4_in {
  2185. compatible = "qcom,smp2pgpio_test_smp2p_4_in";
  2186. gpios = <0x36 0x0 0x0>;
  2187. };
  2188.  
  2189. qcom,smp2pgpio-smp2p-4-out {
  2190. compatible = "qcom,smp2pgpio";
  2191. qcom,entry-name = "smp2p";
  2192. qcom,remote-pid = <0x4>;
  2193. gpio-controller;
  2194. #gpio-cells = <0x2>;
  2195. interrupt-controller;
  2196. #interrupt-cells = <0x2>;
  2197. linux,phandle = <0x37>;
  2198. phandle = <0x37>;
  2199. };
  2200.  
  2201. qcom,smp2pgpio-ssr-smp2p-4-in {
  2202. compatible = "qcom,smp2pgpio";
  2203. qcom,entry-name = "slave-kernel";
  2204. qcom,remote-pid = <0x4>;
  2205. qcom,is-inbound;
  2206. gpio-controller;
  2207. #gpio-cells = <0x2>;
  2208. interrupt-controller;
  2209. #interrupt-cells = <0x2>;
  2210. linux,phandle = <0x6b>;
  2211. phandle = <0x6b>;
  2212. };
  2213.  
  2214. qcom,smp2pgpio-ssr-smp2p-4-out {
  2215. compatible = "qcom,smp2pgpio";
  2216. qcom,entry-name = "master-kernel";
  2217. qcom,remote-pid = <0x4>;
  2218. gpio-controller;
  2219. #gpio-cells = <0x2>;
  2220. interrupt-controller;
  2221. #interrupt-cells = <0x2>;
  2222. linux,phandle = <0x6c>;
  2223. phandle = <0x6c>;
  2224. };
  2225.  
  2226. qcom,smp2pgpio_test_smp2p_4_out {
  2227. compatible = "qcom,smp2pgpio_test_smp2p_4_out";
  2228. gpios = <0x37 0x0 0x0>;
  2229. };
  2230.  
  2231. msm-mmss-noc@fc478000 {
  2232. compatible = "msm-bus-fabric";
  2233. reg = <0xfc478000 0x4000>;
  2234. cell-id = <0x800>;
  2235. label = "msm_mmss_noc";
  2236. qcom,fabclk-dual = "bus_clk";
  2237. qcom,fabclk-active = "bus_a_clk";
  2238. qcom,ntieredslaves = <0x0>;
  2239. qcom,qos-freq = <0x12c0>;
  2240. qcom,hw-sel = "NoC";
  2241. qcom,rpm-en;
  2242. coresight-id = <0x34>;
  2243. coresight-name = "coresight-mnoc";
  2244. coresight-nr-inports = <0x0>;
  2245. coresight-outports = <0x0>;
  2246. coresight-child-list = <0x19>;
  2247. coresight-child-ports = <0x5>;
  2248.  
  2249. mas-gfx3d {
  2250. cell-id = <0x1a>;
  2251. label = "mas-gfx3d";
  2252. qcom,masterp = <0x2 0x3>;
  2253. qcom,tier = <0x2>;
  2254. qcom,hw-sel = "NoC";
  2255. qcom,perm-mode = "Bypass";
  2256. qcom,mode = "Bypass";
  2257. qcom,ws = <0x2710>;
  2258. qcom,qport = <0x2 0x3>;
  2259. qcom,mas-hw-id = <0x6>;
  2260. };
  2261.  
  2262. mas-jpeg {
  2263. cell-id = <0x3e>;
  2264. label = "mas-jpeg";
  2265. qcom,masterp = <0x4>;
  2266. qcom,tier = <0x2>;
  2267. qcom,hw-sel = "NoC";
  2268. qcom,perm-mode = "Bypass";
  2269. qcom,mode = "Bypass";
  2270. qcom,qport = <0x0>;
  2271. qcom,ws = <0x2710>;
  2272. qcom,mas-hw-id = <0x7>;
  2273. };
  2274.  
  2275. mas-mdp-port0 {
  2276. cell-id = <0x16>;
  2277. label = "mas-mdp-port0";
  2278. qcom,masterp = <0x5>;
  2279. qcom,tier = <0x2>;
  2280. qcom,hw-sel = "NoC";
  2281. qcom,perm-mode = "Bypass";
  2282. qcom,mode = "Bypass";
  2283. qcom,qport = <0x1>;
  2284. qcom,ws = <0x2710>;
  2285. qcom,mas-hw-id = <0x8>;
  2286. };
  2287.  
  2288. mas-video-p0 {
  2289. cell-id = <0x3f>;
  2290. label = "mas-video-p0";
  2291. qcom,masterp = <0x6 0x7>;
  2292. qcom,tier = <0x2>;
  2293. qcom,hw-sel = "NoC";
  2294. qcom,perm-mode = "Bypass";
  2295. qcom,mode = "Bypass";
  2296. qcom,ws = <0x2710>;
  2297. qcom,qport = <0x4 0x5>;
  2298. qcom,mas-hw-id = <0x9>;
  2299. };
  2300.  
  2301. mas-vfe {
  2302. cell-id = <0x1d>;
  2303. label = "mas-vfe";
  2304. qcom,masterp = <0x10>;
  2305. qcom,tier = <0x2>;
  2306. qcom,hw-sel = "NoC";
  2307. qcom,perm-mode = "Bypass";
  2308. qcom,mode = "Bypass";
  2309. qcom,ws = <0x2710>;
  2310. qcom,qport = <0x6>;
  2311. qcom,mas-hw-id = <0xb>;
  2312. };
  2313.  
  2314. fab-cnoc {
  2315. cell-id = <0x1400>;
  2316. label = "fab-cnoc";
  2317. qcom,gateway;
  2318. qcom,masterp = <0x0 0x1>;
  2319. qcom,buswidth = <0x10>;
  2320. qcom,hw-sel = "RPM";
  2321. qcom,mas-hw-id = <0x4>;
  2322. };
  2323.  
  2324. fab-bimc {
  2325. cell-id = <0x0>;
  2326. label = "fab-bimc";
  2327. qcom,gateway;
  2328. qcom,slavep = <0x10 0x11>;
  2329. qcom,buswidth = <0x10>;
  2330. qcom,hw-sel = "NoC";
  2331. qcom,slv-hw-id = <0x10>;
  2332. };
  2333.  
  2334. slv-camera-cfg {
  2335. cell-id = <0x24d>;
  2336. label = "slv-camera-cfg";
  2337. qcom,slavep = <0x0>;
  2338. qcom,tier = <0x2>;
  2339. qcom,buswidth = <0x10>;
  2340. qcom,hw-sel = "NoC";
  2341. qcom,slv-hw-id = <0x3>;
  2342. };
  2343.  
  2344. slv-display-cfg {
  2345. cell-id = <0x24e>;
  2346. label = "slv-display-cfg";
  2347. qcom,slavep = <0x1>;
  2348. qcom,tier = <0x2>;
  2349. qcom,buswidth = <0x10>;
  2350. qcom,hw-sel = "NoC";
  2351. qcom,slv-hw-id = <0x4>;
  2352. };
  2353.  
  2354. slv-ocmem-cfg {
  2355. cell-id = <0x24f>;
  2356. label = "slv-ocmem-cfg";
  2357. qcom,slavep = <0x2>;
  2358. qcom,tier = <0x2>;
  2359. qcom,buswidth = <0x10>;
  2360. qcom,hw-sel = "NoC";
  2361. qcom,slv-hw-id = <0x5>;
  2362. };
  2363.  
  2364. slv-cpr-cfg {
  2365. cell-id = <0x250>;
  2366. label = "slv-cpr-cfg";
  2367. qcom,slavep = <0x3>;
  2368. qcom,tier = <0x2>;
  2369. qcom,buswidth = <0x10>;
  2370. qcom,hw-sel = "NoC";
  2371. qcom,slv-hw-id = <0x6>;
  2372. };
  2373.  
  2374. slv-cpr-xpu-cfg {
  2375. cell-id = <0x251>;
  2376. label = "slv-cpr-xpu-cfg";
  2377. qcom,slavep = <0x4>;
  2378. qcom,tier = <0x2>;
  2379. qcom,buswidth = <0x10>;
  2380. qcom,hw-sel = "NoC";
  2381. qcom,slv-hw-id = <0x7>;
  2382. };
  2383.  
  2384. slv-misc-cfg {
  2385. cell-id = <0x252>;
  2386. label = "slv-misc-cfg";
  2387. qcom,slavep = <0x6>;
  2388. qcom,tier = <0x2>;
  2389. qcom,buswidth = <0x10>;
  2390. qcom,hw-sel = "NoC";
  2391. qcom,slv-hw-id = <0x8>;
  2392. };
  2393.  
  2394. slv-misc-xpu-cfg {
  2395. cell-id = <0x253>;
  2396. label = "slv-misc-xpu-cfg";
  2397. qcom,slavep = <0x7>;
  2398. qcom,tier = <0x2>;
  2399. qcom,buswidth = <0x10>;
  2400. qcom,hw-sel = "NoC";
  2401. qcom,slv-hw-id = <0x9>;
  2402. };
  2403.  
  2404. slv-venus-cfg {
  2405. cell-id = <0x254>;
  2406. label = "slv-venus-cfg";
  2407. qcom,slavep = <0x8>;
  2408. qcom,tier = <0x2>;
  2409. qcom,buswidth = <0x10>;
  2410. qcom,hw-sel = "NoC";
  2411. qcom,slv-hw-id = <0xa>;
  2412. };
  2413.  
  2414. slv-gfx3d-cfg {
  2415. cell-id = <0x256>;
  2416. label = "slv-gfx3d-cfg";
  2417. qcom,slavep = <0x9>;
  2418. qcom,tier = <0x2>;
  2419. qcom,buswidth = <0x10>;
  2420. qcom,hw-sel = "NoC";
  2421. qcom,slv-hw-id = <0xb>;
  2422. };
  2423.  
  2424. slv-mmss-clk-cfg {
  2425. cell-id = <0x257>;
  2426. label = "slv-mmss-clk-cfg";
  2427. qcom,slavep = <0xb>;
  2428. qcom,tier = <0x2>;
  2429. qcom,buswidth = <0x10>;
  2430. qcom,hw-sel = "NoC";
  2431. qcom,slv-hw-id = <0xc>;
  2432. };
  2433.  
  2434. slv-mmss-clk-xpu-cfg {
  2435. cell-id = <0x258>;
  2436. label = "slv-mmss-clk-xpu-cfg";
  2437. qcom,slavep = <0xc>;
  2438. qcom,tier = <0x2>;
  2439. qcom,buswidth = <0x10>;
  2440. qcom,hw-sel = "NoC";
  2441. qcom,slv-hw-id = <0xd>;
  2442. };
  2443.  
  2444. slv-mnoc-mpu-cfg {
  2445. cell-id = <0x259>;
  2446. label = "slv-mnoc-mpu-cfg";
  2447. qcom,slavep = <0xd>;
  2448. qcom,tier = <0x2>;
  2449. qcom,buswidth = <0x10>;
  2450. qcom,hw-sel = "NoC";
  2451. qcom,slv-hw-id = <0xe>;
  2452. };
  2453.  
  2454. slv-onoc-mpu-cfg {
  2455. cell-id = <0x25a>;
  2456. label = "slv-onoc-mpu-cfg";
  2457. qcom,slavep = <0xe>;
  2458. qcom,tier = <0x2>;
  2459. qcom,buswidth = <0x10>;
  2460. qcom,hw-sel = "NoC";
  2461. qcom,slv-hw-id = <0xf>;
  2462. };
  2463.  
  2464. slv-service-mnoc {
  2465. cell-id = <0x25b>;
  2466. label = "slv-service-mnoc";
  2467. qcom,slavep = <0x12>;
  2468. qcom,tier = <0x2>;
  2469. qcom,buswidth = <0x10>;
  2470. qcom,hw-sel = "NoC";
  2471. qcom,slv-hw-id = <0x11>;
  2472. };
  2473. };
  2474.  
  2475. msm-sys-noc@fc460000 {
  2476. compatible = "msm-bus-fabric";
  2477. reg = <0xfc460000 0x4000>;
  2478. cell-id = <0x400>;
  2479. label = "msm_sys_noc";
  2480. qcom,fabclk-dual = "bus_clk";
  2481. qcom,fabclk-active = "bus_a_clk";
  2482. qcom,ntieredslaves = <0x0>;
  2483. qcom,qos-freq = <0x12c0>;
  2484. qcom,hw-sel = "NoC";
  2485. qcom,rpm-en;
  2486. coresight-id = <0x32>;
  2487. coresight-name = "coresight-snoc";
  2488. coresight-nr-inports = <0x0>;
  2489. coresight-outports = <0x0>;
  2490. coresight-child-list = <0x19>;
  2491. coresight-child-ports = <0x3>;
  2492.  
  2493. msm-lpass-ahb {
  2494. cell-id = <0x34>;
  2495. label = "mas-lpass-ahb";
  2496. qcom,masterp = <0x0>;
  2497. qcom,tier = <0x2>;
  2498. qcom,qport = <0x0>;
  2499. qcom,mas-hw-id = <0x12>;
  2500. qcom,mode = "Fixed";
  2501. qcom,prio1 = <0x2>;
  2502. qcom,prio0 = <0x2>;
  2503. };
  2504.  
  2505. mas-qdss-bam {
  2506. cell-id = <0x35>;
  2507. label = "mas-qdss-bam";
  2508. qcom,masterp = <0x1>;
  2509. qcom,tier = <0x2>;
  2510. qcom,mode = "Fixed";
  2511. qcom,qport = <0x1>;
  2512. qcom,mas-hw-id = <0x13>;
  2513. qcom,prio1 = <0x1>;
  2514. qcom,prio0 = <0x1>;
  2515. qcom,hw-sel = "NoC";
  2516. };
  2517.  
  2518. mas-snoc-cfg {
  2519. cell-id = <0x36>;
  2520. label = "mas-snoc-cfg";
  2521. qcom,masterp = <0x2>;
  2522. qcom,tier = <0x2>;
  2523. qcom,mas-hw-id = <0x14>;
  2524. };
  2525.  
  2526. fab-bimc {
  2527. cell-id = <0x0>;
  2528. label = "fab-bimc";
  2529. qcom,gateway;
  2530. qcom,slavep = <0x7 0x8>;
  2531. qcom,masterp = <0x3>;
  2532. qcom,buswidth = <0x8>;
  2533. qcom,mas-hw-id = <0x15>;
  2534. qcom,slv-hw-id = <0x18>;
  2535. };
  2536.  
  2537. fab-cnoc {
  2538. cell-id = <0x1400>;
  2539. label = "fab-cnoc";
  2540. qcom,gateway;
  2541. qcom,slavep = <0x9>;
  2542. qcom,masterp = <0x4>;
  2543. qcom,buswidth = <0x8>;
  2544. qcom,mas-hw-id = <0x16>;
  2545. qcom,slv-hw-id = <0x19>;
  2546. };
  2547.  
  2548. fab-pnoc {
  2549. cell-id = <0x1000>;
  2550. label = "fab-pnoc";
  2551. qcom,gateway;
  2552. qcom,slavep = <0xc>;
  2553. qcom,masterp = <0xb>;
  2554. qcom,buswidth = <0x8>;
  2555. qcom,qport = <0x8>;
  2556. qcom,mas-hw-id = <0x1d>;
  2557. qcom,slv-hw-id = <0x1c>;
  2558. qcom,mode = "Fixed";
  2559. qcom,prio1 = <0x2>;
  2560. qcom,prio0 = <0x2>;
  2561. };
  2562.  
  2563. fab-ovnoc {
  2564. cell-id = <0x1800>;
  2565. label = "fab-ovnoc";
  2566. qcom,gateway;
  2567. qcom,buswidth = <0x8>;
  2568. qcom,mas-hw-id = <0x35>;
  2569. qcom,slv-hw-id = <0x4d>;
  2570. };
  2571.  
  2572. mas-crypto-core0 {
  2573. cell-id = <0x37>;
  2574. label = "mas-crypto-core0";
  2575. qcom,masterp = <0x5>;
  2576. qcom,tier = <0x2>;
  2577. qcom,mode = "Fixed";
  2578. qcom,qport = <0x2>;
  2579. qcom,mas-hw-id = <0x17>;
  2580. qcom,hw-sel = "NoC";
  2581. qcom,prio1 = <0x1>;
  2582. qcom,prio0 = <0x1>;
  2583. };
  2584.  
  2585. mas-crypto-core1 {
  2586. cell-id = <0x38>;
  2587. label = "mas-crypto-core1";
  2588. qcom,masterp = <0x6>;
  2589. qcom,tier = <0x2>;
  2590. qcom,mode = "Fixed";
  2591. qcom,qport = <0x3>;
  2592. qcom,mas-hw-id = <0x18>;
  2593. qcom,hw-sel = "NoC";
  2594. qcom,prio1 = <0x1>;
  2595. qcom,prio0 = <0x1>;
  2596. };
  2597.  
  2598. mas-lpass-proc {
  2599. cell-id = <0xb>;
  2600. label = "mas-lpass-proc";
  2601. qcom,masterp = <0x7>;
  2602. qcom,tier = <0x2>;
  2603. qcom,qport = <0x4>;
  2604. qcom,mas-hw-id = <0x19>;
  2605. qcom,mode = "Fixed";
  2606. qcom,prio1 = <0x2>;
  2607. qcom,prio0 = <0x2>;
  2608. };
  2609.  
  2610. mas-mss {
  2611. cell-id = <0x26>;
  2612. label = "mas-mss";
  2613. qcom,masterp = <0x8>;
  2614. qcom,tier = <0x2>;
  2615. qcom,mas-hw-id = <0x1a>;
  2616. };
  2617.  
  2618. mas-mss-nav {
  2619. cell-id = <0x39>;
  2620. label = "mas-mss-nav";
  2621. qcom,masterp = <0x9>;
  2622. qcom,tier = <0x2>;
  2623. qcom,mas-hw-id = <0x1b>;
  2624. };
  2625.  
  2626. mas-ocmem-dma {
  2627. cell-id = <0x3a>;
  2628. label = "mas-ocmem-dma";
  2629. qcom,masterp = <0xa>;
  2630. qcom,tier = <0x2>;
  2631. qcom,mode = "Fixed";
  2632. qcom,qport = <0x7>;
  2633. qcom,mas-hw-id = <0x1c>;
  2634. };
  2635.  
  2636. mas-wcss {
  2637. cell-id = <0x3b>;
  2638. label = "mas-wcss";
  2639. qcom,masterp = <0xc>;
  2640. qcom,tier = <0x2>;
  2641. qcom,mas-hw-id = <0x1e>;
  2642. };
  2643.  
  2644. mas-qdss-etr {
  2645. cell-id = <0x3c>;
  2646. label = "mas-qdss-etr";
  2647. qcom,masterp = <0xd>;
  2648. qcom,tier = <0x2>;
  2649. qcom,qport = <0xa>;
  2650. qcom,mode = "Fixed";
  2651. qcom,mas-hw-id = <0x1f>;
  2652. qcom,prio1 = <0x1>;
  2653. qcom,prio0 = <0x1>;
  2654. qcom,hw-sel = "NoC";
  2655. };
  2656.  
  2657. mas-usb3 {
  2658. cell-id = <0x3d>;
  2659. label = "mas-usb3";
  2660. qcom,masterp = <0xe>;
  2661. qcom,tier = <0x2>;
  2662. qcom,mode = "Fixed";
  2663. qcom,qport = <0xb>;
  2664. qcom,mas-hw-id = <0x20>;
  2665. qcom,prio1 = <0x1>;
  2666. qcom,prio0 = <0x1>;
  2667. qcom,hw-sel = "NoC";
  2668. qcom,iface-clk-node = "msm_usb3";
  2669. };
  2670.  
  2671. slv-ampss {
  2672. cell-id = <0x208>;
  2673. label = "slv-ampss";
  2674. qcom,slavep = <0x1>;
  2675. qcom,tier = <0x2>;
  2676. qcom,buswidth = <0x8>;
  2677. qcom,slv-hw-id = <0x14>;
  2678. };
  2679.  
  2680. slv-lpass {
  2681. cell-id = <0x20a>;
  2682. label = "slv-lpass";
  2683. qcom,slavep = <0x2>;
  2684. qcom,tier = <0x2>;
  2685. qcom,buswidth = <0x8>;
  2686. qcom,slv-hw-id = <0x15>;
  2687. };
  2688.  
  2689. slv-usb3 {
  2690. cell-id = <0x247>;
  2691. label = "slv-usb3";
  2692. qcom,slavep = <0x4>;
  2693. qcom,tier = <0x2>;
  2694. qcom,buswidth = <0x8>;
  2695. qcom,slv-hw-id = <0x16>;
  2696. };
  2697.  
  2698. slv-wcss {
  2699. cell-id = <0x248>;
  2700. label = "slv-wcss";
  2701. qcom,slavep = <0x6>;
  2702. qcom,tier = <0x2>;
  2703. qcom,buswidth = <0x8>;
  2704. qcom,slv-hw-id = <0x17>;
  2705. };
  2706.  
  2707. slv-ocimem {
  2708. cell-id = <0x249>;
  2709. label = "slv-ocimem";
  2710. qcom,slavep = <0xa>;
  2711. qcom,tier = <0x2>;
  2712. qcom,buswidth = <0x8>;
  2713. qcom,slv-hw-id = <0x1a>;
  2714. };
  2715.  
  2716. slv-snoc-ocmem {
  2717. cell-id = <0x24a>;
  2718. label = "slv-snoc-ocmem";
  2719. qcom,slavep = <0xb>;
  2720. qcom,tier = <0x2>;
  2721. qcom,buswidth = <0x8>;
  2722. qcom,slv-hw-id = <0x1b>;
  2723. };
  2724.  
  2725. slv-service-snoc {
  2726. cell-id = <0x24b>;
  2727. label = "slv-service-snoc";
  2728. qcom,slavep = <0xd>;
  2729. qcom,tier = <0x2>;
  2730. qcom,buswidth = <0x8>;
  2731. qcom,slv-hw-id = <0x1d>;
  2732. };
  2733.  
  2734. slv-qdss-stm {
  2735. cell-id = <0x24c>;
  2736. label = "slv-qdss-stm";
  2737. qcom,slavep = <0xe>;
  2738. qcom,tier = <0x2>;
  2739. qcom,buswidth = <0x8>;
  2740. qcom,slv-hw-id = <0x1e>;
  2741. };
  2742. };
  2743.  
  2744. msm-periph-noc@fc468000 {
  2745. compatible = "msm-bus-fabric";
  2746. reg = <0xfc468000 0x4000>;
  2747. cell-id = <0x1000>;
  2748. label = "msm_periph_noc";
  2749. qcom,fabclk-dual = "bus_clk";
  2750. qcom,fabclk-active = "bus_a_clk";
  2751. qcom,ntieredslaves = <0x0>;
  2752. qcom,hw-sel = "NoC";
  2753. qcom,rpm-en;
  2754. coresight-id = <0x36>;
  2755. coresight-name = "coresight-pnoc";
  2756. coresight-nr-inports = <0x0>;
  2757. coresight-outports = <0x0>;
  2758. coresight-child-list = <0x19>;
  2759. coresight-child-ports = <0x6>;
  2760.  
  2761. mas-pnoc-cfg {
  2762. cell-id = <0x58>;
  2763. label = "mas-pnoc-cfg";
  2764. qcom,masterp = <0xa>;
  2765. qcom,tier = <0x2>;
  2766. qcom,buswidth = <0x8>;
  2767. qcom,mas-hw-id = <0x2b>;
  2768. };
  2769.  
  2770. mas-sdcc-1 {
  2771. cell-id = <0x4e>;
  2772. label = "mas-sdcc-1";
  2773. qcom,masterp = <0x0>;
  2774. qcom,tier = <0x2>;
  2775. qcom,buswidth = <0x8>;
  2776. qcom,mas-hw-id = <0x21>;
  2777. };
  2778.  
  2779. mas-sdcc-3 {
  2780. cell-id = <0x4f>;
  2781. label = "mas-sdcc-3";
  2782. qcom,masterp = <0x1>;
  2783. qcom,tier = <0x2>;
  2784. qcom,buswidth = <0x8>;
  2785. qcom,mas-hw-id = <0x22>;
  2786. };
  2787.  
  2788. mas-sdcc-4 {
  2789. cell-id = <0x50>;
  2790. label = "mas-sdcc-4";
  2791. qcom,masterp = <0x3>;
  2792. qcom,tier = <0x2>;
  2793. qcom,buswidth = <0x8>;
  2794. qcom,mas-hw-id = <0x24>;
  2795. };
  2796.  
  2797. mas-sdcc-2 {
  2798. cell-id = <0x51>;
  2799. label = "mas-sdcc-2";
  2800. qcom,masterp = <0x2>;
  2801. qcom,tier = <0x2>;
  2802. qcom,buswidth = <0x8>;
  2803. qcom,mas-hw-id = <0x23>;
  2804. };
  2805.  
  2806. mas-tsif {
  2807. cell-id = <0x52>;
  2808. label = "mas-tsif";
  2809. qcom,masterp = <0x4>;
  2810. qcom,tier = <0x2>;
  2811. qcom,buswidth = <0x8>;
  2812. qcom,mas-hw-id = <0x25>;
  2813. };
  2814.  
  2815. mas-bam-dma {
  2816. cell-id = <0x53>;
  2817. label = "mas-bam-dma";
  2818. qcom,masterp = <0x5>;
  2819. qcom,tier = <0x2>;
  2820. qcom,buswidth = <0x8>;
  2821. qcom,mas-hw-id = <0x26>;
  2822. };
  2823.  
  2824. mas-blsp-2 {
  2825. cell-id = <0x54>;
  2826. label = "mas-blsp-2";
  2827. qcom,masterp = <0x6>;
  2828. qcom,tier = <0x2>;
  2829. qcom,buswidth = <0x8>;
  2830. qcom,mas-hw-id = <0x27>;
  2831. };
  2832.  
  2833. mas-usb-hsic {
  2834. cell-id = <0x55>;
  2835. label = "mas-usb-hsic";
  2836. qcom,masterp = <0x7>;
  2837. qcom,tier = <0x2>;
  2838. qcom,buswidth = <0x8>;
  2839. qcom,mas-hw-id = <0x28>;
  2840. };
  2841.  
  2842. mas-blsp-1 {
  2843. cell-id = <0x56>;
  2844. label = "mas-blsp-1";
  2845. qcom,masterp = <0x8>;
  2846. qcom,tier = <0x2>;
  2847. qcom,buswidth = <0x8>;
  2848. qcom,mas-hw-id = <0x29>;
  2849. };
  2850.  
  2851. mas-usb-hs {
  2852. cell-id = <0x57>;
  2853. label = "mas-usb-hs";
  2854. qcom,masterp = <0x9>;
  2855. qcom,tier = <0x2>;
  2856. qcom,buswidth = <0x8>;
  2857. qcom,mas-hw-id = <0x2a>;
  2858. };
  2859.  
  2860. fab-snoc {
  2861. cell-id = <0x400>;
  2862. label = "fab-snoc";
  2863. qcom,gateway;
  2864. qcom,slavep = <0xe>;
  2865. qcom,masterp = <0xb>;
  2866. qcom,tier = <0x2>;
  2867. qcom,buswidth = <0x8>;
  2868. qcom,slv-hw-id = <0x2d>;
  2869. qcom,mas-hw-id = <0x2c>;
  2870. };
  2871.  
  2872. slv-sdcc-1 {
  2873. cell-id = <0x25e>;
  2874. label = "slv-sdcc-1";
  2875. qcom,slavep = <0x0>;
  2876. qcom,tier = <0x2>;
  2877. qcom,buswidth = <0x8>;
  2878. qcom,slv-hw-id = <0x1f>;
  2879. };
  2880.  
  2881. slv-sdcc-3 {
  2882. cell-id = <0x25f>;
  2883. label = "slv-sdcc-3";
  2884. qcom,slavep = <0x1>;
  2885. qcom,tier = <0x2>;
  2886. qcom,buswidth = <0x8>;
  2887. qcom,slv-hw-id = <0x20>;
  2888. };
  2889.  
  2890. slv-sdcc-2 {
  2891. cell-id = <0x260>;
  2892. label = "slv-sdcc-2";
  2893. qcom,slavep = <0x2>;
  2894. qcom,tier = <0x2>;
  2895. qcom,buswidth = <0x8>;
  2896. qcom,slv-hw-id = <0x21>;
  2897. };
  2898.  
  2899. slv-sdcc-4 {
  2900. cell-id = <0x261>;
  2901. label = "slv-sdcc-4";
  2902. qcom,slavep = <0x3>;
  2903. qcom,tier = <0x2>;
  2904. qcom,buswidth = <0x8>;
  2905. qcom,slv-hw-id = <0x22>;
  2906. };
  2907.  
  2908. slv-tsif {
  2909. cell-id = <0x23f>;
  2910. label = "slv-tsif";
  2911. qcom,slavep = <0x4>;
  2912. qcom,tier = <0x2>;
  2913. qcom,buswidth = <0x8>;
  2914. qcom,slv-hw-id = <0x23>;
  2915. };
  2916.  
  2917. slv-bam-dma {
  2918. cell-id = <0x262>;
  2919. label = "slv-bam-dma";
  2920. qcom,slavep = <0x5>;
  2921. qcom,tier = <0x2>;
  2922. qcom,buswidth = <0x8>;
  2923. qcom,slv-hw-id = <0x24>;
  2924. };
  2925.  
  2926. slv-blsp-2 {
  2927. cell-id = <0x263>;
  2928. label = "slv-blsp-2";
  2929. qcom,slavep = <0x6>;
  2930. qcom,tier = <0x2>;
  2931. qcom,buswidth = <0x8>;
  2932. qcom,slv-hw-id = <0x25>;
  2933. };
  2934.  
  2935. slv-usb-hsic {
  2936. cell-id = <0x264>;
  2937. label = "slv-usb-hsic";
  2938. qcom,slavep = <0x7>;
  2939. qcom,tier = <0x2>;
  2940. qcom,buswidth = <0x8>;
  2941. qcom,slv-hw-id = <0x26>;
  2942. };
  2943.  
  2944. slv-blsp-1 {
  2945. cell-id = <0x265>;
  2946. label = "slv-blsp-1";
  2947. qcom,slavep = <0x8>;
  2948. qcom,tier = <0x2>;
  2949. qcom,buswidth = <0x8>;
  2950. qcom,slv-hw-id = <0x27>;
  2951. };
  2952.  
  2953. slv-usb-hs {
  2954. cell-id = <0x266>;
  2955. label = "slv-usb-hs";
  2956. qcom,slavep = <0x9>;
  2957. qcom,tier = <0x2>;
  2958. qcom,buswidth = <0x8>;
  2959. qcom,slv-hw-id = <0x28>;
  2960. };
  2961.  
  2962. slv-pdm {
  2963. cell-id = <0x267>;
  2964. label = "slv-pdm";
  2965. qcom,slavep = <0xa>;
  2966. qcom,tier = <0x2>;
  2967. qcom,buswidth = <0x8>;
  2968. qcom,slv-hw-id = <0x29>;
  2969. };
  2970.  
  2971. slv-periph-apu-cfg {
  2972. cell-id = <0x268>;
  2973. label = "slv-periph-apu-cfg";
  2974. qcom,slavep = <0xb>;
  2975. qcom,tier = <0x2>;
  2976. qcom,buswidth = <0x8>;
  2977. qcom,slv-hw-id = <0x2a>;
  2978. };
  2979.  
  2980. slv-pnoc-mpu-cfg {
  2981. cell-id = <0x269>;
  2982. label = "slv-pnoc-mpu-cfg";
  2983. qcom,slavep = <0xc>;
  2984. qcom,tier = <0x2>;
  2985. qcom,buswidth = <0x8>;
  2986. qcom,slv-hw-id = <0x2b>;
  2987. };
  2988.  
  2989. slv-prng {
  2990. cell-id = <0x26a>;
  2991. label = "slv-prng";
  2992. qcom,slavep = <0xd>;
  2993. qcom,tier = <0x2>;
  2994. qcom,buswidth = <0x8>;
  2995. qcom,slv-hw-id = <0x2c>;
  2996. };
  2997.  
  2998. slv-service-pnoc {
  2999. cell-id = <0x26b>;
  3000. label = "slv-service-pnoc";
  3001. qcom,slavep = <0xf>;
  3002. qcom,tier = <0x2>;
  3003. qcom,buswidth = <0x8>;
  3004. qcom,slv-hw-id = <0x2e>;
  3005. };
  3006. };
  3007.  
  3008. msm-config-noc@fc480000 {
  3009. compatible = "msm-bus-fabric";
  3010. reg = <0xfc480000 0x4000>;
  3011. cell-id = <0x1400>;
  3012. label = "msm_config_noc";
  3013. qcom,fabclk-dual = "bus_clk";
  3014. qcom,fabclk-active = "bus_a_clk";
  3015. qcom,ntieredslaves = <0x0>;
  3016. qcom,hw-sel = "NoC";
  3017. qcom,rpm-en;
  3018.  
  3019. mas-rpm-inst {
  3020. cell-id = <0x48>;
  3021. label = "mas-rpm-inst";
  3022. qcom,masterp = <0x0>;
  3023. qcom,tier = <0x2>;
  3024. qcom,buswidth = <0x8>;
  3025. qcom,mas-hw-id = <0x2d>;
  3026. };
  3027.  
  3028. mas-rpm-data {
  3029. cell-id = <0x49>;
  3030. label = "mas-rpm-data";
  3031. qcom,masterp = <0x1>;
  3032. qcom,tier = <0x2>;
  3033. qcom,buswidth = <0x8>;
  3034. qcom,mas-hw-id = <0x2e>;
  3035. };
  3036.  
  3037. mas-rpm-sys {
  3038. cell-id = <0x4a>;
  3039. label = "mas-rpm-sys";
  3040. qcom,masterp = <0x2>;
  3041. qcom,tier = <0x2>;
  3042. qcom,buswidth = <0x8>;
  3043. qcom,mas-hw-id = <0x2f>;
  3044. };
  3045.  
  3046. mas-dehr {
  3047. cell-id = <0x4b>;
  3048. label = "mas-dehr";
  3049. qcom,masterp = <0x3>;
  3050. qcom,tier = <0x2>;
  3051. qcom,buswidth = <0x8>;
  3052. qcom,mas-hw-id = <0x30>;
  3053. };
  3054.  
  3055. mas-qdss-dsp {
  3056. cell-id = <0x4c>;
  3057. label = "mas-qdss-dap";
  3058. qcom,masterp = <0x4>;
  3059. qcom,tier = <0x2>;
  3060. qcom,buswidth = <0x8>;
  3061. qcom,mas-hw-id = <0x31>;
  3062. };
  3063.  
  3064. mas-spdm {
  3065. cell-id = <0x24>;
  3066. label = "mas-spdm";
  3067. qcom,masterp = <0x5>;
  3068. qcom,tier = <0x2>;
  3069. qcom,buswidth = <0x8>;
  3070. qcom,mas-hw-id = <0x32>;
  3071. };
  3072.  
  3073. mas-tic {
  3074. cell-id = <0x4d>;
  3075. label = "mas-tic";
  3076. qcom,masterp = <0x6>;
  3077. qcom,tier = <0x2>;
  3078. qcom,buswidth = <0x8>;
  3079. qcom,mas-hw-id = <0x33>;
  3080. };
  3081.  
  3082. slv-clk-ctl {
  3083. cell-id = <0x26c>;
  3084. label = "slv-clk-ctl";
  3085. qcom,slavep = <0x1>;
  3086. qcom,tier = <0x2>;
  3087. qcom,buswidth = <0x8>;
  3088. qcom,slv-hw-id = <0x2f>;
  3089. };
  3090.  
  3091. slv-cnoc-mss {
  3092. cell-id = <0x26d>;
  3093. label = "slv-cnoc-mss";
  3094. qcom,slavep = <0x2>;
  3095. qcom,tier = <0x2>;
  3096. qcom,buswidth = <0x8>;
  3097. qcom,slv-hw-id = <0x30>;
  3098. };
  3099.  
  3100. slv-security {
  3101. cell-id = <0x26e>;
  3102. label = "slv-security";
  3103. qcom,slavep = <0x3>;
  3104. qcom,tier = <0x2>;
  3105. qcom,buswidth = <0x8>;
  3106. qcom,slv-hw-id = <0x31>;
  3107. };
  3108.  
  3109. slv-tcsr {
  3110. cell-id = <0x26f>;
  3111. label = "slv-tcsr";
  3112. qcom,slavep = <0x4>;
  3113. qcom,tier = <0x2>;
  3114. qcom,buswidth = <0x8>;
  3115. qcom,slv-hw-id = <0x32>;
  3116. };
  3117.  
  3118. slv-tlmm {
  3119. cell-id = <0x270>;
  3120. label = "slv-tlmm";
  3121. qcom,slavep = <0x5>;
  3122. qcom,tier = <0x2>;
  3123. qcom,buswidth = <0x8>;
  3124. qcom,slv-hw-id = <0x33>;
  3125. };
  3126.  
  3127. slv-crypto-0-cfg {
  3128. cell-id = <0x271>;
  3129. label = "slv-crypto-0-cfg";
  3130. qcom,slavep = <0x6>;
  3131. qcom,tier = <0x2>;
  3132. qcom,buswidth = <0x8>;
  3133. qcom,slv-hw-id = <0x34>;
  3134. };
  3135.  
  3136. slv-crypto-1-cfg {
  3137. cell-id = <0x272>;
  3138. label = "slv-crypto-1-cfg";
  3139. qcom,slavep = <0x7>;
  3140. qcom,tier = <0x2>;
  3141. qcom,buswidth = <0x8>;
  3142. qcom,slv-hw-id = <0x35>;
  3143. };
  3144.  
  3145. slv-imem-cfg {
  3146. cell-id = <0x273>;
  3147. label = "slv-imem-cfg";
  3148. qcom,slavep = <0x8>;
  3149. qcom,tier = <0x2>;
  3150. qcom,buswidth = <0x8>;
  3151. qcom,slv-hw-id = <0x36>;
  3152. };
  3153.  
  3154. slv-message-ram {
  3155. cell-id = <0x274>;
  3156. label = "slv-message-ram";
  3157. qcom,slavep = <0x9>;
  3158. qcom,tier = <0x2>;
  3159. qcom,buswidth = <0x8>;
  3160. qcom,slv-hw-id = <0x37>;
  3161. };
  3162.  
  3163. slv-bimc-cfg {
  3164. cell-id = <0x275>;
  3165. label = "slv-bimc-cfg";
  3166. qcom,slavep = <0xa>;
  3167. qcom,tier = <0x2>;
  3168. qcom,buswidth = <0x8>;
  3169. qcom,slv-hw-id = <0x38>;
  3170. };
  3171.  
  3172. slv-boot-rom {
  3173. cell-id = <0x276>;
  3174. label = "slv-boot-rom";
  3175. qcom,slavep = <0xb>;
  3176. qcom,tier = <0x2>;
  3177. qcom,buswidth = <0x8>;
  3178. qcom,slv-hw-id = <0x39>;
  3179. };
  3180.  
  3181. slv-pmic-arb {
  3182. cell-id = <0x278>;
  3183. label = "slv-pmic-arb";
  3184. qcom,slavep = <0xd>;
  3185. qcom,tier = <0x2>;
  3186. qcom,buswidth = <0x8>;
  3187. qcom,slv-hw-id = <0x3b>;
  3188. };
  3189.  
  3190. slv-spdm-wrapper {
  3191. cell-id = <0x279>;
  3192. label = "slv-spdm-wrapper";
  3193. qcom,slavep = <0xe>;
  3194. qcom,tier = <0x2>;
  3195. qcom,buswidth = <0x8>;
  3196. qcom,slv-hw-id = <0x3c>;
  3197. };
  3198.  
  3199. slv-dehr-cfg {
  3200. cell-id = <0x27a>;
  3201. label = "slv-dehr-cfg";
  3202. qcom,slavep = <0xf>;
  3203. qcom,tier = <0x2>;
  3204. qcom,buswidth = <0x8>;
  3205. qcom,slv-hw-id = <0x3d>;
  3206. };
  3207.  
  3208. slv-mpm {
  3209. cell-id = <0x218>;
  3210. label = "slv-mpm";
  3211. qcom,slavep = <0x10>;
  3212. qcom,tier = <0x2>;
  3213. qcom,buswidth = <0x8>;
  3214. qcom,slv-hw-id = <0x3e>;
  3215. };
  3216.  
  3217. slv-qdss-cfg {
  3218. cell-id = <0x27b>;
  3219. label = "slv-qdss-cfg";
  3220. qcom,slavep = <0x11>;
  3221. qcom,tier = <0x2>;
  3222. qcom,buswidth = <0x8>;
  3223. qcom,slv-hw-id = <0x3f>;
  3224. };
  3225.  
  3226. slv-rbcpr-cfg {
  3227. cell-id = <0x27c>;
  3228. label = "slv-rbcpr-cfg";
  3229. qcom,slavep = <0x12>;
  3230. qcom,tier = <0x2>;
  3231. qcom,buswidth = <0x8>;
  3232. qcom,slv-hw-id = <0x40>;
  3233. };
  3234.  
  3235. slv-rbcpr-qdss-apu-cfg {
  3236. cell-id = <0x27d>;
  3237. label = "slv-rbcpr-qdss-apu-cfg";
  3238. qcom,slavep = <0x13>;
  3239. qcom,tier = <0x2>;
  3240. qcom,buswidth = <0x8>;
  3241. qcom,slv-hw-id = <0x41>;
  3242. };
  3243.  
  3244. fab-snoc {
  3245. cell-id = <0x400>;
  3246. label = "fab-snoc";
  3247. qcom,gateway;
  3248. qcom,slavep = <0x1d>;
  3249. qcom,masterp = <0x7>;
  3250. qcom,tier = <0x2>;
  3251. qcom,buswidth = <0x8>;
  3252. qcom,mas-hw-id = <0x34>;
  3253. qcom,slv-hw-id = <0x4b>;
  3254. };
  3255.  
  3256. slv-cnoc-onoc-cfg {
  3257. cell-id = <0x27f>;
  3258. label = "slv-cnoc-onoc-cfg";
  3259. qcom,slavep = <0x16>;
  3260. qcom,tier = <0x2>;
  3261. qcom,buswidth = <0x8>;
  3262. qcom,slv-hw-id = <0x44>;
  3263. };
  3264.  
  3265. slv-cnoc-mnoc-mmss-cfg {
  3266. cell-id = <0x277>;
  3267. label = "slv-cnoc-mnoc-mmss-cfg";
  3268. qcom,slavep = <0xc>;
  3269. qcom,tier = <0x2>;
  3270. qcom,buswidth = <0x8>;
  3271. qcom,slv-hw-id = <0x3a>;
  3272. };
  3273.  
  3274. slv-cnoc-mnoc-cfg {
  3275. cell-id = <0x280>;
  3276. label = "slv-cnoc-mnoc-cfg";
  3277. qcom,slavep = <0x14>;
  3278. qcom,tier = <0x2>;
  3279. qcom,buswidth = <0x8>;
  3280. qcom,slv-hw-id = <0x42>;
  3281. };
  3282.  
  3283. slv-pnoc-cfg {
  3284. cell-id = <0x281>;
  3285. label = "slv-pnoc-cfg";
  3286. qcom,slavep = <0x17>;
  3287. qcom,tier = <0x2>;
  3288. qcom,buswidth = <0x8>;
  3289. qcom,slv-hw-id = <0x45>;
  3290. };
  3291.  
  3292. slv-snoc-mpu-cfg {
  3293. cell-id = <0x27e>;
  3294. label = "slv-snoc-mpu-cfg";
  3295. qcom,slavep = <0x15>;
  3296. qcom,tier = <0x2>;
  3297. qcom,buswidth = <0x8>;
  3298. qcom,slv-hw-id = <0x43>;
  3299. };
  3300.  
  3301. slv-snoc-cfg {
  3302. cell-id = <0x282>;
  3303. label = "slv-snoc-cfg";
  3304. qcom,slavep = <0x18>;
  3305. qcom,tier = <0x2>;
  3306. qcom,buswidth = <0x8>;
  3307. qcom,slv-hw-id = <0x46>;
  3308. };
  3309.  
  3310. slv-ebi1-dll-cfg {
  3311. cell-id = <0x283>;
  3312. label = "slv-ebi1-dll-cfg";
  3313. qcom,slavep = <0x19>;
  3314. qcom,tier = <0x2>;
  3315. qcom,buswidth = <0x8>;
  3316. qcom,slv-hw-id = <0x47>;
  3317. };
  3318.  
  3319. slv-phy-apu-cfg {
  3320. cell-id = <0x284>;
  3321. label = "slv-phy-apu-cfg";
  3322. qcom,slavep = <0x1a>;
  3323. qcom,tier = <0x2>;
  3324. qcom,buswidth = <0x8>;
  3325. qcom,slv-hw-id = <0x48>;
  3326. };
  3327.  
  3328. slv-ebi1-phy-cfg {
  3329. cell-id = <0x285>;
  3330. label = "slv-ebi1-phy-cfg";
  3331. qcom,slavep = <0x1b>;
  3332. qcom,tier = <0x2>;
  3333. qcom,buswidth = <0x8>;
  3334. qcom,slv-hw-id = <0x49>;
  3335. };
  3336.  
  3337. slv-rpm {
  3338. cell-id = <0x216>;
  3339. label = "slv-rpm";
  3340. qcom,slavep = <0x1c>;
  3341. qcom,tier = <0x2>;
  3342. qcom,buswidth = <0x8>;
  3343. qcom,slv-hw-id = <0x4a>;
  3344. };
  3345.  
  3346. slv-service-cnoc {
  3347. cell-id = <0x286>;
  3348. label = "slv-service-cnoc";
  3349. qcom,slavep = <0x1e>;
  3350. qcom,tier = <0x2>;
  3351. qcom,buswidth = <0x8>;
  3352. qcom,slv-hw-id = <0x4c>;
  3353. };
  3354. };
  3355.  
  3356. msm-bimc@0xfc380000 {
  3357. compatible = "msm-bus-fabric";
  3358. reg = <0xfc380000 0x6a000>;
  3359. cell-id = <0x0>;
  3360. label = "msm_bimc";
  3361. qcom,fabclk-dual = "mem_clk";
  3362. qcom,fabclk-active = "mem_a_clk";
  3363. qcom,ntieredslaves = <0x0>;
  3364. qcom,qos-freq = <0x4b00>;
  3365. qcom,hw-sel = "BIMC";
  3366. qcom,rpm-en;
  3367. coresight-id = <0x37>;
  3368. coresight-name = "coresight-bimc";
  3369. coresight-nr-inports = <0x0>;
  3370. coresight-outports = <0x0>;
  3371. coresight-child-list = <0x17>;
  3372. coresight-child-ports = <0x3>;
  3373.  
  3374. mas-ampss-m0 {
  3375. cell-id = <0x1>;
  3376. label = "mas-ampss-m0";
  3377. qcom,masterp = <0x0>;
  3378. qcom,tier = <0x2>;
  3379. qcom,hw-sel = "BIMC";
  3380. qcom,mode = "Limiter";
  3381. qcom,qport = <0x0>;
  3382. qcom,ws = <0x2710>;
  3383. qcom,mas-hw-id = <0x0>;
  3384. qcom,prio-rd = <0x0>;
  3385. qcom,prio-wr = <0x0>;
  3386. qcom,mode-thresh = "Fixed";
  3387. qcom,thresh = <0x1e8480 0x2579c0>;
  3388. qcom,dual-conf;
  3389. qcom,bimc,bw = <0x493e0 0x6ddd0>;
  3390. qcom,bimc,gp = <0x1388>;
  3391. qcom,bimc,thmp = <0x32>;
  3392. };
  3393.  
  3394. mas-ampss-m1 {
  3395. cell-id = <0x2>;
  3396. label = "mas-ampss-m1";
  3397. qcom,masterp = <0x1>;
  3398. qcom,tier = <0x2>;
  3399. qcom,hw-sel = "BIMC";
  3400. qcom,mode = "Limiter";
  3401. qcom,qport = <0x1>;
  3402. qcom,ws = <0x2710>;
  3403. qcom,mas-hw-id = <0x0>;
  3404. qcom,prio-rd = <0x0>;
  3405. qcom,prio-wr = <0x0>;
  3406. qcom,mode-thresh = "Fixed";
  3407. qcom,thresh = <0x1e8480 0x2579c0>;
  3408. qcom,dual-conf;
  3409. qcom,bimc,bw = <0x493e0 0x6ddd0>;
  3410. qcom,bimc,gp = <0x1388>;
  3411. qcom,bimc,thmp = <0x32>;
  3412. };
  3413.  
  3414. mas-mss-proc {
  3415. cell-id = <0x41>;
  3416. label = "mas-mss-proc";
  3417. qcom,masterp = <0x2>;
  3418. qcom,tier = <0x2>;
  3419. qcom,hw-sel = "RPM";
  3420. qcom,mas-hw-id = <0x1>;
  3421. };
  3422.  
  3423. fab-mmss-noc {
  3424. cell-id = <0x800>;
  3425. label = "fab_mmss_noc";
  3426. qcom,gateway;
  3427. qcom,masterp = <0x3 0x4>;
  3428. qcom,qport = <0x3 0x4>;
  3429. qcom,buswidth = <0x8>;
  3430. qcom,ws = <0x2710>;
  3431. qcom,mas-hw-id = <0x2>;
  3432. qcom,hw-sel = "BIMC";
  3433. qcom,mode = "Bypass";
  3434. };
  3435.  
  3436. fab-snoc {
  3437. cell-id = <0x400>;
  3438. label = "fab-snoc";
  3439. qcom,gateway;
  3440. qcom,slavep = <0x3>;
  3441. qcom,masterp = <0x5 0x6>;
  3442. qcom,qport = <0x5 0x6>;
  3443. qcom,buswidth = <0x8>;
  3444. qcom,ws = <0x2710>;
  3445. qcom,mas-hw-id = <0x3>;
  3446. qcom,slv-hw-id = <0x2>;
  3447. qcom,mode = "Bypass";
  3448. qcom,hw-sel = "RPM";
  3449. };
  3450.  
  3451. slv-ebi-ch0 {
  3452. cell-id = <0x200>;
  3453. label = "slv-ebi-ch0";
  3454. qcom,slavep = <0x0 0x1>;
  3455. qcom,tier = <0x2>;
  3456. qcom,buswidth = <0x8>;
  3457. qcom,slv-hw-id = <0x0>;
  3458. qcom,mode = "Bypass";
  3459. };
  3460.  
  3461. slv-ampss-l2 {
  3462. cell-id = <0x202>;
  3463. label = "slv-ampss-l2";
  3464. qcom,slavep = <0x2>;
  3465. qcom,tier = <0x2>;
  3466. qcom,buswidth = <0x8>;
  3467. qcom,slv-hw-id = <0x1>;
  3468. };
  3469. };
  3470.  
  3471. msm-ocmem-vnoc@6144 {
  3472. compatible = "msm-bus-fabric";
  3473. reg = <0x6144 0x2>;
  3474. cell-id = <0x1800>;
  3475. label = "msm-ocmem-vnoc";
  3476. qcom,ntieredslaves = <0x0>;
  3477. qcom,hw-sel = "NoC";
  3478. qcom,rpm-en;
  3479. qcom,virt;
  3480.  
  3481. mas-v-ocmem-gfx3d {
  3482. cell-id = <0x59>;
  3483. label = "mas-v-ocmem-gfx3d";
  3484. qcom,tier = <0x2>;
  3485. qcom,buswidth = <0x8>;
  3486. qcom,mas-hw-id = <0x37>;
  3487. };
  3488.  
  3489. slv-ocmem {
  3490. cell-id = <0x25c>;
  3491. label = "slv-ocmem";
  3492. qcom,slavep = <0x0 0x1>;
  3493. qcom,tier = <0x2>;
  3494. qcom,buswidth = <0x10>;
  3495. qcom,slv-hw-id = <0x12>;
  3496. qcom,slaveclk-dual = "ocmem_clk";
  3497. qcom,slaveclk-active = "ocmem_a_clk";
  3498. };
  3499.  
  3500. fab-snoc {
  3501. cell-id = <0x400>;
  3502. label = "fab-snoc";
  3503. qcom,gateway;
  3504. qcom,buswidth = <0x8>;
  3505. qcom,ws = <0x2710>;
  3506. qcom,mas-hw-id = <0x39>;
  3507. qcom,slv-hw-id = <0x50>;
  3508. };
  3509.  
  3510. fab-onoc {
  3511. cell-id = <0xc00>;
  3512. label = "fab-onoc";
  3513. qcom,gateway;
  3514. qcom,buswidth = <0x10>;
  3515. qcom,ws = <0x2710>;
  3516. qcom,mas-hw-id = <0x38>;
  3517. qcom,slv-hw-id = <0x4f>;
  3518. };
  3519. };
  3520.  
  3521. msm-ocmem-noc@fc470000 {
  3522. compatible = "msm-bus-fabric";
  3523. reg = <0xfc470000 0x4000>;
  3524. cell-id = <0xc00>;
  3525. label = "msm_ocmem_noc";
  3526. qcom,fabclk-dual = "bus_clk";
  3527. qcom,fabclk-active = "bus_a_clk";
  3528. qcom,ntieredslaves = <0x0>;
  3529. qcom,qos-freq = <0x12c0>;
  3530. qcom,hw-sel = "NoC";
  3531. qcom,rpm-en;
  3532. coresight-id = <0x33>;
  3533. coresight-name = "coresight-onoc";
  3534. coresight-nr-inports = <0x0>;
  3535. coresight-outports = <0x0>;
  3536. coresight-child-list = <0x19>;
  3537. coresight-child-ports = <0x4>;
  3538.  
  3539. fab-ocmem-vnoc {
  3540. cell-id = <0x1800>;
  3541. label = "fab-ocmem-vnoc";
  3542. qcom,gateway;
  3543. qcom,buswidth = <0x10>;
  3544. qcom,mas-hw-id = <0x36>;
  3545. qcom,slv-hw-id = <0x4e>;
  3546. };
  3547.  
  3548. mas-jpeg-ocmem {
  3549. cell-id = <0x42>;
  3550. label = "mas-jpeg-ocmem";
  3551. qcom,masterp = <0x1>;
  3552. qcom,tier = <0x2>;
  3553. qcom,perm-mode = "Fixed";
  3554. qcom,mode = "Fixed";
  3555. qcom,qport = <0x0>;
  3556. qcom,mas-hw-id = <0xd>;
  3557. qcom,hw-sel = "NoC";
  3558. };
  3559.  
  3560. mas-mdp-ocmem {
  3561. cell-id = <0x43>;
  3562. label = "mas-mdp-ocmem";
  3563. qcom,masterp = <0x2>;
  3564. qcom,tier = <0x2>;
  3565. qcom,perm-mode = "Fixed";
  3566. qcom,mode = "Fixed";
  3567. qcom,mas-hw-id = <0xe>;
  3568. qcom,hw-sel = "NoC";
  3569. };
  3570.  
  3571. mas-video-ocmem {
  3572. cell-id = <0x44>;
  3573. label = "mas-video-ocmem";
  3574. qcom,masterp = <0x3 0x4>;
  3575. qcom,tier = <0x2>;
  3576. qcom,perm-mode = "Fixed";
  3577. qcom,mode = "Fixed";
  3578. qcom,qport = <0x2 0x3>;
  3579. qcom,mas-hw-id = <0xf>;
  3580. qcom,hw-sel = "NoC";
  3581. };
  3582.  
  3583. mas-vfe-ocmem {
  3584. cell-id = <0x46>;
  3585. label = "mas-vfe-ocmem";
  3586. qcom,masterp = <0x5>;
  3587. qcom,tier = <0x2>;
  3588. qcom,perm-mode = "Fixed";
  3589. qcom,mode = "Fixed";
  3590. qcom,qport = <0x4>;
  3591. qcom,mas-hw-id = <0x11>;
  3592. qcom,hw-sel = "NoC";
  3593. qcom,prio-rd = <0x1>;
  3594. qcom,prio-wr = <0x1>;
  3595. };
  3596.  
  3597. mas-cnoc-onoc-cfg {
  3598. cell-id = <0x47>;
  3599. label = "mas-cnoc-onoc-cfg";
  3600. qcom,masterp = <0x0>;
  3601. qcom,tier = <0x2>;
  3602. qcom,buswidth = <0x10>;
  3603. qcom,mas-hw-id = <0xc>;
  3604. qcom,hw-sel = "NoC";
  3605. };
  3606.  
  3607. slv-service-onoc {
  3608. cell-id = <0x25d>;
  3609. label = "slv-service-onoc";
  3610. qcom,slavep = <0x2>;
  3611. qcom,tier = <0x2>;
  3612. qcom,buswidth = <0x10>;
  3613. qcom,slv-hw-id = <0x13>;
  3614. };
  3615. };
  3616.  
  3617. qcom,smp2pgpio-rdbg-2-in {
  3618. compatible = "qcom,smp2pgpio";
  3619. qcom,entry-name = "rdbg";
  3620. qcom,remote-pid = <0x2>;
  3621. qcom,is-inbound;
  3622. gpio-controller;
  3623. #gpio-cells = <0x2>;
  3624. interrupt-controller;
  3625. #interrupt-cells = <0x2>;
  3626. linux,phandle = <0x38>;
  3627. phandle = <0x38>;
  3628. };
  3629.  
  3630. qcom,smp2pgpio_client_rdbg_2_in {
  3631. compatible = "qcom,smp2pgpio_client_rdbg_2_in";
  3632. gpios = <0x38 0x0 0x0>;
  3633. };
  3634.  
  3635. qcom,smp2pgpio-rdbg-2-out {
  3636. compatible = "qcom,smp2pgpio";
  3637. qcom,entry-name = "rdbg";
  3638. qcom,remote-pid = <0x2>;
  3639. gpio-controller;
  3640. #gpio-cells = <0x2>;
  3641. interrupt-controller;
  3642. #interrupt-cells = <0x2>;
  3643. linux,phandle = <0x39>;
  3644. phandle = <0x39>;
  3645. };
  3646.  
  3647. qcom,smp2pgpio_client_rdbg_2_out {
  3648. compatible = "qcom,smp2pgpio_client_rdbg_2_out";
  3649. gpios = <0x39 0x0 0x0>;
  3650. };
  3651.  
  3652. qcom,smp2pgpio-rdbg-1-in {
  3653. compatible = "qcom,smp2pgpio";
  3654. qcom,entry-name = "rdbg";
  3655. qcom,remote-pid = <0x1>;
  3656. qcom,is-inbound;
  3657. gpio-controller;
  3658. #gpio-cells = <0x2>;
  3659. interrupt-controller;
  3660. #interrupt-cells = <0x2>;
  3661. linux,phandle = <0x3a>;
  3662. phandle = <0x3a>;
  3663. };
  3664.  
  3665. qcom,smp2pgpio_client_rdbg_1_in {
  3666. compatible = "qcom,smp2pgpio_client_rdbg_1_in";
  3667. gpios = <0x3a 0x0 0x0>;
  3668. };
  3669.  
  3670. qcom,smp2pgpio-rdbg-1-out {
  3671. compatible = "qcom,smp2pgpio";
  3672. qcom,entry-name = "rdbg";
  3673. qcom,remote-pid = <0x1>;
  3674. gpio-controller;
  3675. #gpio-cells = <0x2>;
  3676. interrupt-controller;
  3677. #interrupt-cells = <0x2>;
  3678. linux,phandle = <0x3b>;
  3679. phandle = <0x3b>;
  3680. };
  3681.  
  3682. qcom,smp2pgpio_client_rdbg_1_out {
  3683. compatible = "qcom,smp2pgpio_client_rdbg_1_out";
  3684. gpios = <0x3b 0x0 0x0>;
  3685. };
  3686.  
  3687. interrupt-controller@F9000000 {
  3688. compatible = "qcom,msm-qgic2";
  3689. interrupt-controller;
  3690. #interrupt-cells = <0x3>;
  3691. reg = <0xf9000000 0x1000 0xf9002000 0x1000>;
  3692. linux,phandle = <0x1>;
  3693. phandle = <0x1>;
  3694. };
  3695.  
  3696. gpio@fd510000 {
  3697. compatible = "qcom,msm-gpio";
  3698. gpio-controller;
  3699. #gpio-cells = <0x2>;
  3700. interrupt-controller;
  3701. #interrupt-cells = <0x2>;
  3702. reg = <0xfd510000 0x4000>;
  3703. ngpio = <0x92>;
  3704. interrupts = <0x0 0xd0 0x0>;
  3705. qcom,direct-connect-irqs = <0x8>;
  3706. linux,phandle = <0x5>;
  3707. phandle = <0x5>;
  3708. };
  3709.  
  3710. wcd9xxx-irq {
  3711. compatible = "qcom,wcd9xxx-irq";
  3712. interrupt-controller;
  3713. #interrupt-cells = <0x1>;
  3714. interrupt-parent = <0x5>;
  3715. interrupts = <0x48 0x0>;
  3716. interrupt-names = "cdc-int";
  3717. linux,phandle = <0x4a>;
  3718. phandle = <0x4a>;
  3719. };
  3720.  
  3721. timer {
  3722. compatible = "arm,armv7-timer";
  3723. interrupts = <0x1 0x2 0x0 0x1 0x3 0x0>;
  3724. clock-frequency = <0x124f800>;
  3725. };
  3726.  
  3727. timer@f9020000 {
  3728. #address-cells = <0x1>;
  3729. #size-cells = <0x1>;
  3730. ranges;
  3731. compatible = "arm,armv7-timer-mem";
  3732. reg = <0xf9020000 0x1000>;
  3733. clock-frequency = <0x124f800>;
  3734.  
  3735. frame@f9021000 {
  3736. frame-number = <0x0>;
  3737. interrupts = <0x0 0x8 0x4 0x0 0x7 0x4>;
  3738. reg = <0xf9021000 0x1000 0xf9022000 0x1000>;
  3739. };
  3740.  
  3741. frame@f9023000 {
  3742. frame-number = <0x1>;
  3743. interrupts = <0x0 0x9 0x4>;
  3744. reg = <0xf9023000 0x1000>;
  3745. status = "disabled";
  3746. };
  3747.  
  3748. frame@f9024000 {
  3749. frame-number = <0x2>;
  3750. interrupts = <0x0 0xa 0x4>;
  3751. reg = <0xf9024000 0x1000>;
  3752. status = "disabled";
  3753. };
  3754.  
  3755. frame@f9025000 {
  3756. frame-number = <0x3>;
  3757. interrupts = <0x0 0xb 0x4>;
  3758. reg = <0xf9025000 0x1000>;
  3759. status = "disabled";
  3760. };
  3761.  
  3762. frame@f9026000 {
  3763. frame-number = <0x4>;
  3764. interrupts = <0x0 0xc 0x4>;
  3765. reg = <0xf9026000 0x1000>;
  3766. status = "disabled";
  3767. };
  3768.  
  3769. frame@f9027000 {
  3770. frame-number = <0x5>;
  3771. interrupts = <0x0 0xd 0x4>;
  3772. reg = <0xf9027000 0x1000>;
  3773. status = "disabled";
  3774. };
  3775.  
  3776. frame@f9028000 {
  3777. frame-number = <0x6>;
  3778. interrupts = <0x0 0xe 0x4>;
  3779. reg = <0xf9028000 0x1000>;
  3780. status = "disabled";
  3781. };
  3782. };
  3783.  
  3784. qcom,mpm2-sleep-counter@fc4a3000 {
  3785. compatible = "qcom,mpm2-sleep-counter";
  3786. reg = <0xfc4a3000 0x1000>;
  3787. clock-frequency = <0x8000>;
  3788. };
  3789.  
  3790. qcom,vidc@fdc00000 {
  3791. compatible = "qcom,msm-vidc";
  3792. reg = <0xfdc00000 0xff000>;
  3793. interrupts = <0x0 0x2c 0x0>;
  3794. vdd-supply = <0x3c>;
  3795. qcom,hfi = "venus";
  3796. qcom,ocmem-size = <0x80000>;
  3797. qcom,max-hw-load = <0x138e40>;
  3798. qcom,vidc-ns-map = <0x40000000 0x40000000>;
  3799. qcom,load-freq-tbl = <0xfd200 0x1bb75640 0xbf400 0x1bb75640 0x77880 0xfe50fb0 0x3bc40 0x7f27450>;
  3800. qcom,reg-presets = <0x80004 0x1 0x80070 0x11fff 0x80074 0xa4 0x800a8 0x1fff 0x80124 0x3 0xe0020 0x5555556 0xe0024 0x0>;
  3801. qcom,bus-ports = <0x1>;
  3802. qcom,enc-ocmem-ab-ib = <0x0 0x0 0x21b10 0xfc710 0x65130 0xfc710 0xe57e0 0xfc710 0x1cafc0 0x1f8e20 0x2de600 0x327dc8 0x395f80 0x3f1c40 0x442d20 0x257da8>;
  3803. qcom,dec-ocmem-ab-ib = <0x0 0x0 0x2af80 0x7eb58 0x6f540 0x7eb58 0xd2f00 0x99908 0x1a5e00 0xfd6b0 0x2a34b0 0x195848 0x34bc00 0x1fad60 0x37e0b0 0x2189f0>;
  3804. qcom,enc-ddr-ab-ib = <0x0 0x0 0x1d4c0 0x49bb0 0x58de0 0x49bb0 0xc44a0 0x49bb0 0x188940 0x93760 0x274e80 0xec158 0x476940 0x156c60 0x4c1c60 0x16d3c0>;
  3805. qcom,dec-ddr-ab-ib = <0x0 0x0 0x32c80 0x49f98 0x82dc0 0x186a00 0xf7120 0x186a00 0x1ee240 0x186a00 0x317040 0x186a00 0x3dc480 0x186a00 0x411040 0x186a00>;
  3806. qcom,buffer-type-tz-usage-table = <0x241 0x1 0x106 0x2 0x480 0x3>;
  3807.  
  3808. qcom,vidc-iommu-domains {
  3809.  
  3810. qcom,domain-ns {
  3811. qcom,vidc-domain-phandle = <0x3d>;
  3812. qcom,vidc-partition-buffer-types = <0x7ff 0x800>;
  3813. };
  3814.  
  3815. qcom,domain-sec-bs {
  3816. qcom,vidc-domain-phandle = <0x3e>;
  3817. qcom,vidc-partition-buffer-types = <0x241>;
  3818. };
  3819.  
  3820. qcom,domain-sec-px {
  3821. qcom,vidc-domain-phandle = <0x3f>;
  3822. qcom,vidc-partition-buffer-types = <0x106>;
  3823. };
  3824.  
  3825. qcom,domain-sec-np {
  3826. qcom,vidc-domain-phandle = <0x40>;
  3827. qcom,vidc-partition-buffer-types = <0x480>;
  3828. };
  3829. };
  3830. };
  3831.  
  3832. qcom,vidc {
  3833. compatible = "qcom,msm-vidc";
  3834. qcom,hfi = "q6";
  3835. qcom,max-hw-load = <0x3b538>;
  3836. };
  3837.  
  3838. qcom,wfd {
  3839. compatible = "qcom,msm-wfd";
  3840. };
  3841.  
  3842. qcom,ram-console {
  3843. compatible = "ram-console";
  3844. };
  3845.  
  3846. serial@f991f000 {
  3847. compatible = "qcom,msm-lsuart-v14";
  3848. reg = <0xf991f000 0x1000>;
  3849. interrupts = <0x0 0x6d 0x0>;
  3850. status = "disabled";
  3851. };
  3852.  
  3853. serial@f995e000 {
  3854. compatible = "qcom,msm-lsuart-v14";
  3855. reg = <0xf995e000 0x1000>;
  3856. interrupts = <0x0 0x72 0x0>;
  3857. status = "disabled";
  3858. };
  3859.  
  3860. serial@f991e000 {
  3861. compatible = "qcom,msm-lsuart-v14";
  3862. reg = <0xf991e000 0x1000>;
  3863. interrupts = <0x0 0x6c 0x0>;
  3864. status = "ok";
  3865. qcom,msm-bus,name = "serial_uart2";
  3866. qcom,msm-bus,num-cases = <0x2>;
  3867. qcom,msm-bus,num-paths = <0x1>;
  3868. qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
  3869. };
  3870.  
  3871. usb@f9a55000 {
  3872. compatible = "qcom,hsusb-otg";
  3873. status = "disabled";
  3874. reg = <0xf9a55000 0x400>;
  3875. interrupts = <0x0 0x86 0x0 0x0 0x8c 0x0>;
  3876. interrupt-names = "core_irq", "async_irq";
  3877. HSUSB_VDDCX-supply = <0x23>;
  3878. HSUSB_1p8-supply = <0x41>;
  3879. HSUSB_3p3-supply = <0x42>;
  3880. qcom,vdd-voltage-level = <0x1 0x5 0x7>;
  3881. qcom,hsusb-otg-phy-type = <0x2>;
  3882. qcom,hsusb-otg-phy-init-seq = <0x63 0x81 0xffffffff>;
  3883. qcom,hsusb-otg-mode = <0x1>;
  3884. qcom,hsusb-otg-otg-control = <0x2>;
  3885. qcom,hsusb-otg-disable-reset;
  3886. qcom,hsusb-otg-mpm-dpsehv-int = <0x31>;
  3887. qcom,hsusb-otg-mpm-dmsehv-int = <0x3a>;
  3888. qcom,msm-bus,name = "usb2";
  3889. qcom,msm-bus,num-cases = <0x2>;
  3890. qcom,msm-bus,num-paths = <0x1>;
  3891. qcom,msm-bus,vectors-KBps = <0x57 0x200 0x0 0x0 0x57 0x200 0xea60 0xea600>;
  3892. };
  3893.  
  3894. rmtfs_sharedmem {
  3895. compatible = "qcom,sharedmem-uio";
  3896. reg = <0xfd80000 0x180000>;
  3897. reg-names = "rmtfs";
  3898. };
  3899.  
  3900. dsp_sharedmem {
  3901. compatible = "qcom,sharedmem-uio";
  3902. reg = <0xfd60000 0x20000>;
  3903. reg-names = "rfsa_dsp";
  3904. };
  3905.  
  3906. mdm_sharedmem {
  3907. compatible = "qcom,sharedmem-uio";
  3908. reg = <0xfd60000 0x20000>;
  3909. reg-names = "rfsa_mdm";
  3910. };
  3911.  
  3912. qcom,sdcc@f9824000 {
  3913. cell-index = <0x1>;
  3914. compatible = "qcom,msm-sdcc";
  3915. reg = <0xf9824000 0x800 0xf9824800 0x100 0xf9804000 0x7000>;
  3916. reg-names = "core_mem", "dml_mem", "bam_mem";
  3917. interrupts = <0x0 0x7b 0x0 0x0 0x89 0x0>;
  3918. interrupt-names = "core_irq", "bam_irq";
  3919. vdd-supply = <0x43>;
  3920. vdd-io-supply = <0x2d>;
  3921. qcom,vdd-always-on;
  3922. qcom,vdd-lpm-sup;
  3923. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  3924. qcom,vdd-current-level = <0x320 0x7a120>;
  3925. qcom,vdd-io-always-on;
  3926. qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>;
  3927. qcom,vdd-io-current-level = <0xfa 0x25990>;
  3928. qcom,pad-pull-on = <0x0 0x3 0x3>;
  3929. qcom,pad-pull-off = <0x0 0x3 0x3>;
  3930. qcom,pad-drv-on = <0x7 0x4 0x4>;
  3931. qcom,pad-drv-off = <0x0 0x0 0x0>;
  3932. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>;
  3933. qcom,sup-voltages = <0xb86 0xb86>;
  3934. qcom,bus-width = <0x8>;
  3935. qcom,nonremovable;
  3936. qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
  3937. qcom,msm-bus,name = "sdcc1";
  3938. qcom,msm-bus,num-cases = <0x9>;
  3939. qcom,msm-bus,num-paths = <0x1>;
  3940. qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x0 0x0 0x4e 0x200 0x640 0xc80 0x4e 0x200 0x13880 0x27100 0x4e 0x200 0x186a0 0x30d40 0x4e 0x200 0x30d40 0x61a80 0x4e 0x200 0x61a80 0xc3500 0x4e 0x200 0xc3500 0x186a00 0x4e 0x200 0xc3500 0x186a00 0x4e 0x200 0x1f4000 0x3e8000>;
  3941. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0x17d78400 0xffffffff>;
  3942. qcom,dat1-mpm-int = <0x2a>;
  3943. status = "disabled";
  3944. };
  3945.  
  3946. qcom,sdcc@f98a4000 {
  3947. cell-index = <0x2>;
  3948. compatible = "qcom,msm-sdcc";
  3949. reg = <0xf98a4000 0x800 0xf98a4800 0x100 0xf9884000 0x7000>;
  3950. reg-names = "core_mem", "dml_mem", "bam_mem";
  3951. interrupts = <0x0 0x1 0x2>;
  3952. interrupt-names = "core_irq", "bam_irq", "status_irq";
  3953. vdd-supply = <0x10>;
  3954. vdd-io-supply = <0x11>;
  3955. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  3956. qcom,vdd-current-level = <0x2328 0xc3500>;
  3957. qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>;
  3958. qcom,vdd-io-current-level = <0x6 0x55f0>;
  3959. qcom,pad-pull-on = <0x0 0x3 0x3>;
  3960. qcom,pad-pull-off = <0x0 0x3 0x3>;
  3961. qcom,pad-drv-on = <0x7 0x4 0x4>;
  3962. qcom,pad-drv-off = <0x0 0x0 0x0>;
  3963. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>;
  3964. qcom,sup-voltages = <0xb86 0xb86>;
  3965. qcom,bus-width = <0x4>;
  3966. qcom,xpc;
  3967. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
  3968. qcom,current-limit = <0x320>;
  3969. qcom,msm-bus,name = "sdcc2";
  3970. qcom,msm-bus,num-cases = <0x8>;
  3971. qcom,msm-bus,num-paths = <0x1>;
  3972. qcom,msm-bus,vectors-KBps = <0x51 0x200 0x0 0x0 0x51 0x200 0x640 0xc80 0x51 0x200 0x13880 0x27100 0x51 0x200 0x186a0 0x30d40 0x51 0x200 0x30d40 0x61a80 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0xc3500 0x186a00 0x51 0x200 0x1f4000 0x3e8000>;
  3973. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
  3974. qcom,dat1-mpm-int = <0x2c>;
  3975. status = "disabled";
  3976. #address-cells = <0x0>;
  3977. interrupt-parent = <0x44>;
  3978. #interrupt-cells = <0x1>;
  3979. interrupt-map-mask = <0xffffffff>;
  3980. interrupt-map = <0x0 0x1 0x0 0x7d 0x0 0x1 0x1 0x0 0xdc 0x0 0x2 0x5 0x3e 0x3>;
  3981. cd-gpios = <0x5 0x3e 0x1>;
  3982. linux,phandle = <0x44>;
  3983. phandle = <0x44>;
  3984. };
  3985.  
  3986. qcom,sdcc@f9864000 {
  3987. cell-index = <0x3>;
  3988. compatible = "qcom,msm-sdcc";
  3989. reg = <0xf9864000 0x800 0xf9864800 0x100 0xf9844000 0x7000>;
  3990. reg-names = "core_mem", "dml_mem", "bam_mem";
  3991. #address-cells = <0x0>;
  3992. interrupt-parent = <0x45>;
  3993. interrupts = <0x0 0x1 0x2>;
  3994. #interrupt-cells = <0x1>;
  3995. interrupt-map-mask = <0xffffffff>;
  3996. interrupt-map = <0x0 0x1 0x0 0x7f 0x0 0x1 0x1 0x0 0xdf 0x0 0x2 0x5 0x25 0x8>;
  3997. interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq";
  3998. gpios = <0x5 0x28 0x0 0x5 0x27 0x0 0x5 0x26 0x0 0x5 0x25 0x0 0x5 0x24 0x0 0x5 0x23 0x0>;
  3999. qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
  4000. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100>;
  4001. qcom,sup-voltages = <0x708 0x708>;
  4002. qcom,bus-width = <0x4>;
  4003. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
  4004. qcom,msm-bus,name = "sdcc3";
  4005. qcom,msm-bus,num-cases = <0x8>;
  4006. qcom,msm-bus,num-paths = <0x1>;
  4007. qcom,msm-bus,vectors-KBps = <0x4f 0x200 0x0 0x0 0x4f 0x200 0x640 0xc80 0x4f 0x200 0x13880 0x27100 0x4f 0x200 0x186a0 0x30d40 0x4f 0x200 0x30d40 0x61a80 0x4f 0x200 0x61a80 0xc3500 0x4f 0x200 0xc3500 0x186a00 0x4f 0x200 0x1f4000 0x3e8000>;
  4008. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
  4009. status = "disable";
  4010. linux,phandle = <0x45>;
  4011. phandle = <0x45>;
  4012. };
  4013.  
  4014. qcom,sdcc@f98e4000 {
  4015. cell-index = <0x4>;
  4016. compatible = "qcom,msm-sdcc";
  4017. reg = <0xf98e4000 0x800 0xf98e4800 0x100 0xf98c4000 0x7000>;
  4018. reg-names = "core_mem", "dml_mem", "bam_mem";
  4019. #address-cells = <0x0>;
  4020. interrupt-parent = <0x46>;
  4021. interrupts = <0x0 0x1 0x2>;
  4022. #interrupt-cells = <0x1>;
  4023. interrupt-map-mask = <0xffffffff>;
  4024. interrupt-map = <0x0 0x1 0x0 0x81 0x0 0x1 0x1 0x0 0xe2 0x0 0x2 0x5 0x5f 0x8>;
  4025. interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq";
  4026. gpios = <0x5 0x5d 0x0 0x5 0x5b 0x0 0x5 0x60 0x0 0x5 0x5f 0x0 0x5 0x5e 0x0 0x5 0x5c 0x0>;
  4027. qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
  4028. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100>;
  4029. qcom,sup-voltages = <0x708 0x708>;
  4030. qcom,bus-width = <0x4>;
  4031. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
  4032. qcom,msm-bus,name = "sdcc4";
  4033. qcom,msm-bus,num-cases = <0x8>;
  4034. qcom,msm-bus,num-paths = <0x1>;
  4035. qcom,msm-bus,vectors-KBps = <0x50 0x200 0x0 0x0 0x50 0x200 0x640 0xc80 0x50 0x200 0x13880 0x27100 0x50 0x200 0x186a0 0x30d40 0x50 0x200 0x30d40 0x61a80 0x50 0x200 0x61a80 0xc3500 0x50 0x200 0xc3500 0x186a00 0x50 0x200 0x1f4000 0x3e8000>;
  4036. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
  4037. status = "disable";
  4038. linux,phandle = <0x46>;
  4039. phandle = <0x46>;
  4040. };
  4041.  
  4042. sdhci@f9824900 {
  4043. qcom,bus-width = <0x8>;
  4044. compatible = "qcom,sdhci-msm";
  4045. reg = <0xf9824900 0x1a0 0xf9824000 0x800>;
  4046. reg-names = "hc_mem", "core_mem";
  4047. interrupts = <0x0 0x7b 0x0 0x0 0x8a 0x0>;
  4048. interrupt-names = "hc_irq", "pwr_irq";
  4049. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000>;
  4050. qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
  4051. qcom,cpu-dma-latency-us = <0xc8>;
  4052. qcom,msm-bus,name = "sdhc1";
  4053. qcom,msm-bus,num-cases = <0x9>;
  4054. qcom,msm-bus,num-paths = <0x1>;
  4055. qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x0 0x0 0x4e 0x200 0x640 0xc80 0x4e 0x200 0x13880 0x27100 0x4e 0x200 0x186a0 0x30d40 0x4e 0x200 0x30d40 0x61a80 0x4e 0x200 0x61a80 0xc3500 0x4e 0x200 0xc3500 0x186a00 0x4e 0x200 0xc3500 0x186a00 0x4e 0x200 0x1f4000 0x3e8000>;
  4056. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0x17d78400 0xffffffff>;
  4057. qcom,dat1-mpm-int = <0x2a>;
  4058. status = "ok";
  4059. vdd-supply = <0x43>;
  4060. vdd-io-supply = <0x2d>;
  4061. qcom,vdd-always-on;
  4062. qcom,vdd-lpm-sup;
  4063. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  4064. qcom,vdd-current-level = <0x320 0x7a120>;
  4065. qcom,vdd-io-always-on;
  4066. qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>;
  4067. qcom,vdd-io-current-level = <0xfa 0x25990>;
  4068. qcom,pad-pull-on = <0x0 0x3 0x3 0x1>;
  4069. qcom,pad-pull-off = <0x0 0x3 0x3 0x1>;
  4070. qcom,pad-drv-on = <0x4 0x4 0x4>;
  4071. qcom,pad-drv-off = <0x0 0x0 0x0>;
  4072. qcom,nonremovable;
  4073. };
  4074.  
  4075. sdhci@f98a4900 {
  4076. compatible = "qcom,sdhci-msm";
  4077. reg = <0xf98a4900 0x11c 0xf98a4000 0x800>;
  4078. reg-names = "hc_mem", "core_mem";
  4079. interrupts = <0x0 0x1 0x2>;
  4080. interrupt-names = "hc_irq", "pwr_irq", "status_irq";
  4081. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>;
  4082. qcom,bus-width = <0x4>;
  4083. qcom,cpu-dma-latency-us = <0xc8>;
  4084. qcom,msm-bus,name = "sdhc2";
  4085. qcom,msm-bus,num-cases = <0x8>;
  4086. qcom,msm-bus,num-paths = <0x1>;
  4087. qcom,msm-bus,vectors-KBps = <0x51 0x200 0x0 0x0 0x51 0x200 0x640 0xc80 0x51 0x200 0x13880 0x27100 0x51 0x200 0x186a0 0x30d40 0x51 0x200 0x30d40 0x61a80 0x51 0x200 0x61a80 0xc3500 0x51 0x200 0xc3500 0x186a00 0x51 0x200 0x1f4000 0x3e8000>;
  4088. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
  4089. qcom,dat1-mpm-int = <0x2c>;
  4090. status = "ok";
  4091. #address-cells = <0x0>;
  4092. interrupt-parent = <0x47>;
  4093. #interrupt-cells = <0x1>;
  4094. interrupt-map-mask = <0xffffffff>;
  4095. interrupt-map = <0x0 0x1 0x0 0x7d 0x0 0x1 0x1 0x0 0xdd 0x0 0x2 0x5 0x3e 0x3>;
  4096. vdd-supply = <0x10>;
  4097. vdd-io-supply = <0x11>;
  4098. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  4099. qcom,vdd-current-level = <0x2328 0xc3500>;
  4100. qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>;
  4101. qcom,vdd-io-current-level = <0x6 0x55f0>;
  4102. qcom,pad-pull-on = <0x0 0x3 0x3>;
  4103. qcom,pad-pull-off = <0x0 0x3 0x3>;
  4104. qcom,pad-drv-on = <0x7 0x4 0x4>;
  4105. qcom,pad-drv-off = <0x0 0x0 0x0>;
  4106. linux,phandle = <0x47>;
  4107. phandle = <0x47>;
  4108. };
  4109.  
  4110. sdhci@f9864900 {
  4111. compatible = "qcom,sdhci-msm";
  4112. reg = <0xf9864900 0x11c 0xf9864000 0x800>;
  4113. reg-names = "hc_mem", "core_mem";
  4114. #address-cells = <0x0>;
  4115. interrupt-parent = <0x48>;
  4116. interrupts = <0x0 0x1 0x2>;
  4117. #interrupt-cells = <0x1>;
  4118. interrupt-map-mask = <0xffffffff>;
  4119. interrupt-map = <0x0 0x1 0x0 0x7f 0x0 0x1 0x1 0x0 0xe0 0x0 0x2 0x5 0x25 0x8>;
  4120. interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq";
  4121. gpios = <0x5 0x28 0x0 0x5 0x27 0x0 0x5 0x26 0x0 0x5 0x25 0x0 0x5 0x24 0x0 0x5 0x23 0x0>;
  4122. qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
  4123. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100>;
  4124. qcom,bus-width = <0x4>;
  4125. qcom,cpu-dma-latency-us = <0xc8>;
  4126. qcom,msm-bus,name = "sdhc3";
  4127. qcom,msm-bus,num-cases = <0x8>;
  4128. qcom,msm-bus,num-paths = <0x1>;
  4129. qcom,msm-bus,vectors-KBps = <0x4f 0x200 0x0 0x0 0x4f 0x200 0x640 0xc80 0x4f 0x200 0x13880 0x27100 0x4f 0x200 0x186a0 0x30d40 0x4f 0x200 0x30d40 0x61a80 0x4f 0x200 0x61a80 0xc3500 0x4f 0x200 0xc3500 0x186a00 0x4f 0x200 0x1f4000 0x3e8000>;
  4130. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
  4131. status = "disable";
  4132. linux,phandle = <0x48>;
  4133. phandle = <0x48>;
  4134. };
  4135.  
  4136. sdhci@f98e4900 {
  4137. compatible = "qcom,sdhci-msm";
  4138. reg = <0xf98e4900 0x11c 0xf98e4000 0x800>;
  4139. reg-names = "hc_mem", "core_mem";
  4140. #address-cells = <0x0>;
  4141. interrupt-parent = <0x49>;
  4142. interrupts = <0x0 0x1 0x2>;
  4143. #interrupt-cells = <0x1>;
  4144. interrupt-map-mask = <0xffffffff>;
  4145. interrupt-map = <0x0 0x1 0x0 0x81 0x0 0x1 0x1 0x0 0xe3 0x0 0x2 0x5 0x5f 0x8>;
  4146. interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq";
  4147. gpios = <0x5 0x5d 0x0 0x5 0x5b 0x0 0x5 0x60 0x0 0x5 0x5f 0x0 0x5 0x5e 0x0 0x5 0x5c 0x0>;
  4148. qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
  4149. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100>;
  4150. qcom,bus-width = <0x4>;
  4151. qcom,cpu-dma-latency-us = <0xc8>;
  4152. qcom,msm-bus,name = "sdhc4";
  4153. qcom,msm-bus,num-cases = <0x8>;
  4154. qcom,msm-bus,num-paths = <0x1>;
  4155. qcom,msm-bus,vectors-KBps = <0x50 0x200 0x0 0x0 0x50 0x200 0x640 0xc80 0x50 0x200 0x13880 0x27100 0x50 0x200 0x186a0 0x30d40 0x50 0x200 0x30d40 0x61a80 0x50 0x200 0x61a80 0xc3500 0x50 0x200 0xc3500 0x186a00 0x50 0x200 0x1f4000 0x3e8000>;
  4156. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
  4157. status = "disable";
  4158. linux,phandle = <0x49>;
  4159. phandle = <0x49>;
  4160. };
  4161.  
  4162. qcom,sps@f9980000 {
  4163. compatible = "qcom,msm_sps";
  4164. reg = <0xf9984000 0x15000 0xf9999000 0xb000>;
  4165. interrupts = <0x0 0x5e 0x0>;
  4166. qcom,bam-dma-res-pipes = <0x6>;
  4167. };
  4168.  
  4169. spi@f9966000 {
  4170. compatible = "qcom,spi-qup-v2";
  4171. #address-cells = <0x1>;
  4172. #size-cells = <0x0>;
  4173. reg-names = "spi_physical", "spi_bam_physical";
  4174. reg = <0xf9966000 0x1000 0xf9944000 0x19000>;
  4175. interrupt-names = "spi_irq", "spi_bam_irq";
  4176. interrupts = <0x0 0x68 0x0 0x0 0xef 0x0>;
  4177. spi-max-frequency = <0x124f800>;
  4178. qcom,gpio-mosi = <0x5 0x35 0x0>;
  4179. qcom,gpio-miso = <0x5 0x36 0x0>;
  4180. qcom,gpio-clk = <0x5 0x38 0x0>;
  4181. qcom,gpio-cs0 = <0x5 0x37 0x0>;
  4182. qcom,infinite-mode = <0x0>;
  4183. qcom,use-bam;
  4184. qcom,ver-reg-exists;
  4185. qcom,bam-consumer-pipe-index = <0x12>;
  4186. qcom,bam-producer-pipe-index = <0x13>;
  4187. qcom,master-id = <0x54>;
  4188.  
  4189. epm-adc@0 {
  4190. compatible = "cy,epm-adc-cy8c5568lti-114";
  4191. reg = <0x0>;
  4192. interrupt-parent = <0x5>;
  4193. spi-max-frequency = <0xea600>;
  4194. qcom,channels = <0x1f>;
  4195. qcom,gain = <0x64 0x64 0x64 0x32 0x64 0x64 0x1 0x64 0x1 0x32 0x1 0x64 0x1 0x64 0x32 0x32 0x32 0x32 0x32 0x32 0x64 0x32 0x64 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32>;
  4196. qcom,rsense = <0x2 0x2 0x2 0xc8 0x14 0x2 0x1 0x2 0x1 0x1e 0x1 0xa 0x1 0x1e 0x32 0x1e 0x1f4 0x1e 0x64 0x1e 0x64 0x1f4 0x14 0xc8 0x3e8 0x14 0x3e8 0x3e8 0x46 0xc8 0x32>;
  4197. qcom,channel-type = <0x1540>;
  4198. };
  4199. };
  4200.  
  4201. msm_tspp@f99d8000 {
  4202. compatible = "qcom,msm_tspp";
  4203. cell-index = <0x0>;
  4204. reg = <0xf99d8000 0x1000 0xf99d9000 0x1000 0xf99da000 0x1000 0xf99c4000 0x14000>;
  4205. reg-names = "MSM_TSIF0_PHYS", "MSM_TSIF1_PHYS", "MSM_TSPP_PHYS", "MSM_TSPP_BAM_PHYS";
  4206. interrupts = <0x0 0x79 0x0 0x0 0x77 0x0 0x0 0x78 0x0 0x0 0x7a 0x0>;
  4207. interrupt-names = "TSIF_TSPP_IRQ", "TSIF0_IRQ", "TSIF1_IRQ", "TSIF_BAM_IRQ";
  4208. qcom,tsif-pclk = "iface_clk";
  4209. qcom,tsif-ref-clk = "ref_clk";
  4210. gpios = <0x5 0x59 0x0 0x5 0x5a 0x0 0x5 0x5b 0x0 0x5 0x5c 0x0 0x5 0x5d 0x0 0x5 0x5e 0x0 0x5 0x5f 0x0 0x5 0x60 0x0>;
  4211. qcom,gpio-names = "tsif_clk", "tsif_en", "tsif_data", "tsif_sync", "tsif_clk", "tsif_en", "tsif_data", "tsif_sync";
  4212. qcom,gpios-func = <0x1>;
  4213. qcom,msm-bus,name = "tsif";
  4214. qcom,msm-bus,num-cases = <0x2>;
  4215. qcom,msm-bus,num-paths = <0x1>;
  4216. qcom,msm-bus,vectors-KBps = <0x52 0x200 0x0 0x0 0x52 0x200 0x3000 0x6000>;
  4217. vdd_cx-supply = <0x23>;
  4218. };
  4219.  
  4220. slim@fe12f000 {
  4221. cell-index = <0x1>;
  4222. compatible = "qcom,slim-ngd";
  4223. reg = <0xfe12f000 0x35000 0xfe104000 0x20000>;
  4224. reg-names = "slimbus_physical", "slimbus_bam_physical";
  4225. interrupts = <0x0 0xa3 0x0 0x0 0xa4 0x0>;
  4226. interrupt-names = "slimbus_irq", "slimbus_bam_irq";
  4227. qcom,apps-ch-pipes = <0x60000000>;
  4228. qcom,ea-pc = <0x30>;
  4229.  
  4230. taiko_codec {
  4231. compatible = "qcom,taiko-slim-pgd";
  4232. elemental-addr = [00 01 a0 00 17 02];
  4233. interrupt-parent = <0x4a>;
  4234. interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>;
  4235. qcom,cdc-reset-gpio = <0x5 0x3f 0x0>;
  4236. cdc-vdd-buck-supply = <0x4b>;
  4237. qcom,cdc-vdd-buck-voltage = <0x20ce70 0x20ce70>;
  4238. qcom,cdc-vdd-buck-current = <0x9eb10>;
  4239. cdc-vdd-tx-h-supply = <0x2d>;
  4240. qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>;
  4241. qcom,cdc-vdd-tx-h-current = <0x61a8>;
  4242. cdc-vdd-rx-h-supply = <0x2d>;
  4243. qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>;
  4244. qcom,cdc-vdd-rx-h-current = <0x61a8>;
  4245. cdc-vddpx-1-supply = <0x2d>;
  4246. qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>;
  4247. qcom,cdc-vddpx-1-current = <0x2710>;
  4248. cdc-vdd-a-1p2v-supply = <0x4c>;
  4249. qcom,cdc-vdd-a-1p2v-voltage = <0x12b128 0x12b128>;
  4250. qcom,cdc-vdd-a-1p2v-current = <0x2710>;
  4251. cdc-vddcx-1-supply = <0x4c>;
  4252. qcom,cdc-vddcx-1-voltage = <0x12b128 0x12b128>;
  4253. qcom,cdc-vddcx-1-current = <0x2710>;
  4254. cdc-vddcx-2-supply = <0x4c>;
  4255. qcom,cdc-vddcx-2-voltage = <0x12b128 0x12b128>;
  4256. qcom,cdc-vddcx-2-current = <0x2710>;
  4257. cdc-vdd-spkdrv-supply = <0x4d>;
  4258. qcom,cdc-vdd-spkdrv-voltage = <0x4c4b40 0x4c4b40>;
  4259. qcom,cdc-vdd-spkdrv-current = <0x1312d0>;
  4260. qcom,cdc-on-demand-supplies = "cdc-vdd-spkdrv";
  4261. qcom,cdc-static-supplies = "cdc-vdd-buck", "cdc-vdd-tx-h", "cdc-vdd-rx-h", "cdc-vddpx-1", "cdc-vdd-a-1p2v", "cdc-vddcx-1", "cdc-vddcx-2";
  4262. qcom,cdc-micbias-ldoh-v = <0x3>;
  4263. qcom,cdc-micbias-cfilt1-mv = <0x708>;
  4264. qcom,cdc-micbias-cfilt2-mv = <0x866>;
  4265. qcom,cdc-micbias-cfilt3-mv = <0xa8c>;
  4266. qcom,cdc-micbias1-cfilt-sel = <0x0>;
  4267. qcom,cdc-micbias2-cfilt-sel = <0x1>;
  4268. qcom,cdc-micbias3-cfilt-sel = <0x2>;
  4269. qcom,cdc-micbias4-cfilt-sel = <0x2>;
  4270. qcom,cdc-mclk-clk-rate = <0x927c00>;
  4271. qcom,cdc-slim-ifd = "taiko-slim-ifd";
  4272. qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 00 17 02];
  4273. qcom,cdc-dmic-sample-rate = <0x493e00>;
  4274. qcom,cdc-micbias1-ext-cap;
  4275. qcom,cdc-micbias2-ext-cap;
  4276. qcom,cdc-micbias3-ext-cap;
  4277. qcom,cdc-micbias4-ext-cap;
  4278. };
  4279. };
  4280.  
  4281. ti2603 {
  4282. compatible = "drv2603";
  4283. vdd-drv2603-supply = <0x4e>;
  4284. };
  4285.  
  4286. sound {
  4287. compatible = "qcom,msm8974-audio-taiko";
  4288. qcom,model = "msm8974-taiko-mtp-snd-card";
  4289. reg = <0xfe02c000 0x4 0xfe02d000 0x4 0xfe02e000 0x4 0xfe02f000 0x4>;
  4290. reg-names = "lpaif_pri_mode_muxsel", "lpaif_sec_mode_muxsel", "lpaif_tert_mode_muxsel", "lpaif_quat_mode_muxsel";
  4291. qcom,audio-routing = "RX_BIAS", "MCLK", "LDO_H", "MCLK", "AIF4 MAD", "MCLK", "AMIC1", "MIC BIAS1 External", "MIC BIAS1 External", "Handset Mic", "AMIC2", "MIC BIAS2 External", "MIC BIAS2 External", "Headset Mic", "AMIC3", "MIC BIAS1 External", "MIC BIAS1 External", "Handset Mic", "AMIC4", "MIC BIAS2 External", "MIC BIAS2 External", "ANCLeft Headset Mic", "DMIC1", "MIC BIAS1 External", "MIC BIAS1 External", "Digital Mic1", "DMIC2", "MIC BIAS1 External", "MIC BIAS1 External", "Digital Mic2", "DMIC3", "MIC BIAS3 External", "MIC BIAS3 External", "Digital Mic3", "DMIC4", "MIC BIAS3 External", "MIC BIAS3 External", "Digital Mic4", "DMIC5", "MIC BIAS4 External", "MIC BIAS4 External", "Digital Mic5", "DMIC6", "MIC BIAS4 External", "MIC BIAS4 External", "Digital Mic6";
  4292. qcom,cdc-mclk-gpios = <0x2a 0xf 0x0>;
  4293. qcom,taiko-mclk-clk-freq = <0x927c00>;
  4294. qcom,prim-auxpcm-gpio-clk = <0x5 0x41 0x0>;
  4295. qcom,prim-auxpcm-gpio-sync = <0x5 0x42 0x0>;
  4296. qcom,prim-auxpcm-gpio-din = <0x5 0x43 0x0>;
  4297. qcom,prim-auxpcm-gpio-dout = <0x5 0x44 0x0>;
  4298. qcom,prim-auxpcm-gpio-set = "prim-gpio-prim";
  4299. qcom,sec-auxpcm-gpio-clk = <0x5 0x4f 0x0>;
  4300. qcom,sec-auxpcm-gpio-sync = <0x5 0x50 0x0>;
  4301. qcom,sec-auxpcm-gpio-din = <0x5 0x51 0x0>;
  4302. qcom,sec-auxpcm-gpio-dout = <0x5 0x52 0x0>;
  4303. qcom,cdc-micbias2-headset-only;
  4304. qcom,mbhc-audio-jack-type = "6-pole-jack";
  4305. };
  4306.  
  4307. qcom,spmi@fc4c0000 {
  4308. cell-index = <0x0>;
  4309. compatible = "qcom,spmi-pmic-arb";
  4310. reg-names = "core", "intr", "cnfg";
  4311. reg = <0xfc4cf000 0x1000 0xfc4cb000 0x1000 0xfc4ca000 0x1000>;
  4312. interrupts = <0x0 0xbe 0x0 0x0 0xbb 0x0>;
  4313. qcom,pmic-arb-ee = <0x0>;
  4314. qcom,pmic-arb-channel = <0x0>;
  4315. #address-cells = <0x1>;
  4316. #size-cells = <0x0>;
  4317. interrupt-controller;
  4318. #interrupt-cells = <0x3>;
  4319. linux,phandle = <0x61>;
  4320. phandle = <0x61>;
  4321.  
  4322. qcom,pm8841@4 {
  4323. spmi-slave-container;
  4324. reg = <0x4>;
  4325. #address-cells = <0x1>;
  4326. #size-cells = <0x1>;
  4327.  
  4328. qcom,qpnp-revid@100 {
  4329. compatible = "qcom,qpnp-revid";
  4330. reg = <0x100 0x100>;
  4331. };
  4332.  
  4333. qcom,temp-alarm@2400 {
  4334. compatible = "qcom,qpnp-temp-alarm";
  4335. reg = <0x2400 0x100>;
  4336. interrupts = <0x4 0x24 0x0>;
  4337. label = "pm8841_tz";
  4338. qcom,threshold-set = <0x0>;
  4339. qcom,default-temp = <0x9088>;
  4340. };
  4341.  
  4342. mpps {
  4343. spmi-dev-container;
  4344. compatible = "qcom,qpnp-pin";
  4345. gpio-controller;
  4346. #gpio-cells = <0x2>;
  4347. #address-cells = <0x1>;
  4348. #size-cells = <0x1>;
  4349. label = "pm8841-mpp";
  4350.  
  4351. mpp@a000 {
  4352. reg = <0xa000 0x100>;
  4353. qcom,pin-num = <0x1>;
  4354. };
  4355.  
  4356. mpp@a100 {
  4357. reg = <0xa100 0x100>;
  4358. qcom,pin-num = <0x2>;
  4359. };
  4360.  
  4361. mpp@a200 {
  4362. reg = <0xa200 0x100>;
  4363. qcom,pin-num = <0x3>;
  4364. };
  4365.  
  4366. mpp@a300 {
  4367. reg = <0xa300 0x100>;
  4368. qcom,pin-num = <0x4>;
  4369. };
  4370. };
  4371. };
  4372.  
  4373. qcom,pm8841@5 {
  4374. spmi-slave-container;
  4375. reg = <0x5>;
  4376. #address-cells = <0x1>;
  4377. #size-cells = <0x1>;
  4378.  
  4379. regulator@1400 {
  4380. regulator-name = "8841_s1";
  4381. spmi-dev-container;
  4382. #address-cells = <0x1>;
  4383. #size-cells = <0x1>;
  4384. compatible = "qcom,qpnp-regulator";
  4385. reg = <0x1400 0x300>;
  4386. status = "disabled";
  4387.  
  4388. qcom,ctl@1400 {
  4389. reg = <0x1400 0x100>;
  4390. };
  4391.  
  4392. qcom,ps@1500 {
  4393. reg = <0x1500 0x100>;
  4394. };
  4395.  
  4396. qcom,freq@1600 {
  4397. reg = <0x1600 0x100>;
  4398. };
  4399. };
  4400.  
  4401. regulator@1700 {
  4402. regulator-name = "8841_s2";
  4403. spmi-dev-container;
  4404. #address-cells = <0x1>;
  4405. #size-cells = <0x1>;
  4406. compatible = "qcom,qpnp-regulator";
  4407. reg = <0x1700 0x300>;
  4408. status = "disabled";
  4409. qcom,force-type = <0x1c 0x8>;
  4410.  
  4411. qcom,ctl@1700 {
  4412. reg = <0x1700 0x100>;
  4413. };
  4414.  
  4415. qcom,ps@1800 {
  4416. reg = <0x1800 0x100>;
  4417. };
  4418.  
  4419. qcom,freq@1900 {
  4420. reg = <0x1900 0x100>;
  4421. };
  4422. };
  4423.  
  4424. regulator@1a00 {
  4425. regulator-name = "8841_s3";
  4426. spmi-dev-container;
  4427. #address-cells = <0x1>;
  4428. #size-cells = <0x1>;
  4429. compatible = "qcom,qpnp-regulator";
  4430. reg = <0x1a00 0x300>;
  4431. status = "disabled";
  4432.  
  4433. qcom,ctl@1a00 {
  4434. reg = <0x1a00 0x100>;
  4435. };
  4436.  
  4437. qcom,ps@1b00 {
  4438. reg = <0x1b00 0x100>;
  4439. };
  4440.  
  4441. qcom,freq@1c00 {
  4442. reg = <0x1c00 0x100>;
  4443. };
  4444. };
  4445.  
  4446. regulator@1d00 {
  4447. regulator-name = "8841_s4";
  4448. spmi-dev-container;
  4449. #address-cells = <0x1>;
  4450. #size-cells = <0x1>;
  4451. compatible = "qcom,qpnp-regulator";
  4452. reg = <0x1d00 0x300>;
  4453. status = "disabled";
  4454. qcom,force-type = <0x1c 0x8>;
  4455.  
  4456. qcom,ctl@1d00 {
  4457. reg = <0x1d00 0x100>;
  4458. };
  4459.  
  4460. qcom,ps@1e00 {
  4461. reg = <0x1e00 0x100>;
  4462. };
  4463.  
  4464. qcom,freq@1f00 {
  4465. reg = <0x1f00 0x100>;
  4466. };
  4467. };
  4468.  
  4469. regulator@2000 {
  4470. regulator-name = "8841_s5";
  4471. spmi-dev-container;
  4472. #address-cells = <0x1>;
  4473. #size-cells = <0x1>;
  4474. compatible = "qcom,qpnp-regulator";
  4475. reg = <0x2000 0x300>;
  4476. status = "disabled";
  4477. qcom,force-type = <0x1c 0x8>;
  4478.  
  4479. qcom,ctl@0 {
  4480. reg = <0x2000 0x100>;
  4481. };
  4482.  
  4483. qcom,ps@100 {
  4484. reg = <0x2100 0x100>;
  4485. };
  4486.  
  4487. qcom,freq@200 {
  4488. reg = <0x2200 0x100>;
  4489. };
  4490. };
  4491.  
  4492. regulator@2300 {
  4493. regulator-name = "8841_s6";
  4494. spmi-dev-container;
  4495. #address-cells = <0x1>;
  4496. #size-cells = <0x1>;
  4497. compatible = "qcom,qpnp-regulator";
  4498. reg = <0x2300 0x300>;
  4499. status = "disabled";
  4500. qcom,force-type = <0x1c 0x8>;
  4501.  
  4502. qcom,ctl@2300 {
  4503. reg = <0x2300 0x100>;
  4504. };
  4505.  
  4506. qcom,ps@2400 {
  4507. reg = <0x2400 0x100>;
  4508. };
  4509.  
  4510. qcom,freq@2500 {
  4511. reg = <0x2500 0x100>;
  4512. };
  4513. };
  4514.  
  4515. regulator@2600 {
  4516. regulator-name = "8841_s7";
  4517. spmi-dev-container;
  4518. #address-cells = <0x1>;
  4519. #size-cells = <0x1>;
  4520. compatible = "qcom,qpnp-regulator";
  4521. reg = <0x2600 0x300>;
  4522. status = "disabled";
  4523. qcom,force-type = <0x1c 0x8>;
  4524.  
  4525. qcom,ctl@2600 {
  4526. reg = <0x2600 0x100>;
  4527. };
  4528.  
  4529. qcom,ps@2700 {
  4530. reg = <0x2700 0x100>;
  4531. };
  4532.  
  4533. qcom,freq@2800 {
  4534. reg = <0x2800 0x100>;
  4535. };
  4536. };
  4537.  
  4538. regulator@2900 {
  4539. regulator-name = "8841_s8";
  4540. spmi-dev-container;
  4541. #address-cells = <0x1>;
  4542. #size-cells = <0x1>;
  4543. compatible = "qcom,qpnp-regulator";
  4544. reg = <0x2900 0x300>;
  4545. status = "disabled";
  4546. qcom,force-type = <0x1c 0x8>;
  4547.  
  4548. qcom,ctl@2900 {
  4549. reg = <0x2900 0x100>;
  4550. };
  4551.  
  4552. qcom,ps@2a000 {
  4553. reg = <0x2a00 0x100>;
  4554. };
  4555.  
  4556. qcom,freq@2b00 {
  4557. reg = <0x2b00 0x100>;
  4558. };
  4559. };
  4560.  
  4561. qcom,krait-regulator-pmic@2000 {
  4562. spmi-dev-container;
  4563. compatible = "qcom,krait-regulator-pmic";
  4564. #address-cells = <0x1>;
  4565. #size-cells = <0x1>;
  4566. status = "ok";
  4567.  
  4568. qcom,ctl@2000 {
  4569. status = "ok";
  4570. reg = <0x2000 0x100>;
  4571. };
  4572.  
  4573. qcom,ps@2100 {
  4574. status = "ok";
  4575. reg = <0x2100 0x100>;
  4576. };
  4577.  
  4578. qcom,freq@2200 {
  4579. status = "ok";
  4580. reg = <0x2200 0x100>;
  4581. };
  4582. };
  4583. };
  4584.  
  4585. qcom,pm8941@0 {
  4586. reg = <0x0>;
  4587. spmi-slave-container;
  4588. #address-cells = <0x1>;
  4589. #size-cells = <0x1>;
  4590.  
  4591. qcom,misc@900 {
  4592. compatible = "qcom,qpnp-misc";
  4593. reg = <0x900 0x100>;
  4594. linux,phandle = <0x63>;
  4595. phandle = <0x63>;
  4596. };
  4597.  
  4598. qcom,revid@100 {
  4599. compatible = "qcom,qpnp-revid";
  4600. reg = <0x100 0x100>;
  4601. linux,phandle = <0x53>;
  4602. phandle = <0x53>;
  4603. };
  4604.  
  4605. qcom,temp-alarm@2400 {
  4606. compatible = "qcom,qpnp-temp-alarm";
  4607. reg = <0x2400 0x100>;
  4608. interrupts = <0x0 0x24 0x0>;
  4609. label = "pm8941_tz";
  4610. qcom,channel-num = <0x8>;
  4611. qcom,threshold-set = <0x0>;
  4612. qcom,temp_alarm-vadc = <0x4f>;
  4613. };
  4614.  
  4615. qcom,power-on@800 {
  4616. compatible = "qcom,qpnp-power-on";
  4617. reg = <0x800 0x100>;
  4618. interrupts = <0x0 0x8 0x0 0x0 0x8 0x1 0x0 0x8 0x4 0x0 0x8 0x5>;
  4619. interrupt-names = "kpdpwr", "resin", "resin-bark", "kpdpwr-resin-bark";
  4620. qcom,pon-dbc-delay = <0x3d09>;
  4621. qcom,system-reset;
  4622. qcom,s3-debounce = <0x20>;
  4623.  
  4624. qcom,pon_1 {
  4625. qcom,pon-type = <0x0>;
  4626. qcom,support-reset = <0x1>;
  4627. qcom,pull-up = <0x1>;
  4628. qcom,s1-timer = <0x2810>;
  4629. qcom,s2-timer = <0x7d0>;
  4630. qcom,s2-type = <0x7>;
  4631. linux,code = <0x74>;
  4632. };
  4633.  
  4634. qcom,pon_2 {
  4635. qcom,pon-type = <0x1>;
  4636. qcom,support-reset = <0x1>;
  4637. qcom,pull-up = <0x1>;
  4638. qcom,s1-timer = <0x0>;
  4639. qcom,s2-timer = <0x7d0>;
  4640. qcom,s2-type = <0x1>;
  4641. linux,code = <0x72>;
  4642. qcom,use-bark;
  4643. };
  4644.  
  4645. qcom,pon_3 {
  4646. qcom,pon-type = <0x3>;
  4647. qcom,support-reset = <0x1>;
  4648. qcom,s1-timer = <0x1a40>;
  4649. qcom,s2-timer = <0x7d0>;
  4650. qcom,s2-type = <0x7>;
  4651. qcom,pull-up = <0x1>;
  4652. qcom,use-bark;
  4653. };
  4654. };
  4655.  
  4656. qcom,bsi@1b00 {
  4657. compatible = "qcom,qpnp-bsi";
  4658. reg = <0x1b00 0x100 0x1208 0x1>;
  4659. reg-names = "bsi-base", "batt-id-status";
  4660. label = "pm8941-bsi";
  4661. interrupts = <0x0 0x1b 0x0 0x0 0x1b 0x1 0x0 0x1b 0x2 0x0 0x12 0x0>;
  4662. interrupt-names = "err", "rx", "tx", "batt-present";
  4663. qcom,channel-num = <0x31>;
  4664. qcom,pullup-ohms = <0x186a0>;
  4665. qcom,vref-microvolts = <0x1b7740>;
  4666. qcom,min-clock-period = <0x3e8>;
  4667. qcom,max-clock-period = <0x27100>;
  4668. qcom,sample-rate = <0x4>;
  4669. qcom,bsi-vadc = <0x4f>;
  4670. };
  4671.  
  4672. qcom,coincell@2800 {
  4673. compatible = "qcom,qpnp-coincell";
  4674. reg = <0x2800 0x100>;
  4675. };
  4676.  
  4677. qcom,bms {
  4678. spmi-dev-container;
  4679. compatible = "qcom,qpnp-bms";
  4680. #address-cells = <0x1>;
  4681. #size-cells = <0x1>;
  4682. status = "ok";
  4683. qcom,r-sense-uohm = <0x2710>;
  4684. qcom,v-cutoff-uv = <0x33e140>;
  4685. qcom,max-voltage-uv = <0x426030>;
  4686. qcom,r-conn-mohm = <0x0>;
  4687. qcom,shutdown-soc-valid-limit = <0x64>;
  4688. qcom,adjust-soc-low-threshold = <0xf>;
  4689. qcom,ocv-voltage-high-threshold-uv = <0x393870>;
  4690. qcom,ocv-voltage-low-threshold-uv = <0x37b1d0>;
  4691. qcom,low-soc-calculate-soc-threshold = <0xf>;
  4692. qcom,low-voltage-calculate-soc-ms = <0x3e8>;
  4693. qcom,low-soc-calculate-soc-ms = <0x1388>;
  4694. qcom,calculate-soc-ms = <0x4e20>;
  4695. qcom,chg-term-ua = <0x186a0>;
  4696. qcom,batt-type = <0x0>;
  4697. qcom,low-voltage-threshold = <0x342f60>;
  4698. qcom,tm-temp-margin = <0x1388>;
  4699. qcom,low-ocv-correction-limit-uv = <0x64>;
  4700. qcom,high-ocv-correction-limit-uv = <0xfa>;
  4701. qcom,hold-soc-est = <0x3>;
  4702. qcom,bms-vadc = <0x4f>;
  4703. qcom,bms-iadc = <0x50>;
  4704. qcom,bms-adc_tm = <0x51>;
  4705. qcom,enable-fcc-learning;
  4706. qcom,min-fcc-learning-soc = <0x14>;
  4707. qcom,min-fcc-ocv-pc = <0x1e>;
  4708. qcom,min-fcc-learning-samples = <0x5>;
  4709. qcom,fcc-resolution = <0xa>;
  4710. qcom,battery-data = <0x52>;
  4711.  
  4712. qcom,batt-pres-status@1208 {
  4713. reg = <0x1208 0x1>;
  4714. };
  4715.  
  4716. qcom,bms-iadc@3800 {
  4717. reg = <0x3800 0x100>;
  4718. };
  4719.  
  4720. qcom,bms-bms@4000 {
  4721. reg = <0x4000 0x100>;
  4722. interrupts = <0x0 0x40 0x0 0x0 0x40 0x1 0x0 0x40 0x2 0x0 0x40 0x3 0x0 0x40 0x4 0x0 0x40 0x5 0x0 0x40 0x6 0x0 0x40 0x7>;
  4723. interrupt-names = "cc_thr", "ocv_for_r", "good_ocv", "charge_begin", "ocv_thr", "sw_cc_thr", "vsense_avg", "vsense_for_r";
  4724. };
  4725. };
  4726.  
  4727. clkdiv@5b00 {
  4728. reg = <0x5b00 0x100>;
  4729. compatible = "qcom,qpnp-clkdiv";
  4730. qcom,cxo-freq = <0x124f800>;
  4731. qcom,cxo-div = <0x2>;
  4732. };
  4733.  
  4734. clkdiv@5c00 {
  4735. reg = <0x5c00 0x100>;
  4736. compatible = "qcom,qpnp-clkdiv";
  4737. qcom,cxo-freq = <0x124f800>;
  4738. };
  4739.  
  4740. clkdiv@5d00 {
  4741. reg = <0x5d00 0x1000>;
  4742. compatible = "qcom,qpnp-clkdiv";
  4743. qcom,cxo-freq = <0x124f800>;
  4744. };
  4745.  
  4746. qcom,charger {
  4747. spmi-dev-container;
  4748. compatible = "qcom,qpnp-charger";
  4749. #address-cells = <0x1>;
  4750. #size-cells = <0x1>;
  4751. status = "ok";
  4752. qcom,vddmax-mv = <0x10fe>;
  4753. qcom,vddsafe-mv = <0x111c>;
  4754. qcom,vinmin-mv = <0x1162>;
  4755. qcom,ibatmax-ma = <0x5dc>;
  4756. qcom,ibatterm-ma = <0x64>;
  4757. qcom,ibatsafe-ma = <0x5dc>;
  4758. qcom,thermal-mitigation = <0x5dc 0x2bc 0x258 0x145>;
  4759. qcom,cool-bat-decidegc = <0x64>;
  4760. qcom,cool-bat-mv = <0x1004>;
  4761. qcom,ibatmax-warm-ma = <0x15e>;
  4762. qcom,warm-bat-decidegc = <0x1c2>;
  4763. qcom,warm-bat-mv = <0x1004>;
  4764. qcom,ibatmax-cool-ma = <0x15e>;
  4765. qcom,vbatdet-delta-mv = <0x64>;
  4766. qcom,resume-soc = <0x63>;
  4767. qcom,tchg-mins = <0x96>;
  4768. qcom,chg-vadc = <0x4f>;
  4769. qcom,chg-iadc = <0x50>;
  4770. qcom,chg-adc_tm = <0x51>;
  4771. qcom,ibat-calibration-enabled;
  4772. otg-parent-supply = <0x4d>;
  4773. qcom,battery-data = <0x52>;
  4774.  
  4775. qcom,chgr@1000 {
  4776. status = "ok";
  4777. reg = <0x1000 0x100>;
  4778. interrupts = <0x0 0x10 0x0 0x0 0x10 0x1 0x0 0x10 0x2 0x0 0x10 0x3 0x0 0x10 0x4 0x0 0x10 0x5 0x0 0x10 0x6 0x0 0x10 0x7>;
  4779. interrupt-names = "vbat-det-lo", "vbat-det-hi", "chgwdog", "state-change", "trkl-chg-on", "fast-chg-on", "chg-failed", "chg-done";
  4780. regulator-name = "flash_wa";
  4781. linux,phandle = <0x56>;
  4782. phandle = <0x56>;
  4783. };
  4784.  
  4785. qcom,buck@1100 {
  4786. status = "ok";
  4787. reg = <0x1100 0x100>;
  4788. interrupts = <0x0 0x11 0x0 0x0 0x11 0x1 0x0 0x11 0x2 0x0 0x11 0x3 0x0 0x11 0x4 0x0 0x11 0x5 0x0 0x11 0x6>;
  4789. interrupt-names = "vbat-ov", "vreg-ov", "overtemp", "vchg-loop", "ichg-loop", "ibat-loop", "vdd-loop";
  4790. };
  4791.  
  4792. qcom,bat-if@1200 {
  4793. status = "ok";
  4794. reg = <0x1200 0x100>;
  4795. interrupts = <0x0 0x12 0x0 0x0 0x12 0x1 0x0 0x12 0x2 0x0 0x12 0x3 0x0 0x12 0x4>;
  4796. interrupt-names = "batt-pres", "bat-temp-ok", "bat-fet-on", "vcp-on", "psi";
  4797. regulator-name = "batfet";
  4798. linux,phandle = <0x24>;
  4799. phandle = <0x24>;
  4800. };
  4801.  
  4802. qcom,usb-chgpth@1300 {
  4803. status = "ok";
  4804. reg = <0x1300 0x100>;
  4805. interrupts = <0x0 0x13 0x0 0x0 0x13 0x1 0x0 0x13 0x2>;
  4806. interrupt-names = "coarse-det-usb", "usbin-valid", "chg-gone";
  4807. regulator-name = "8941_smbb_otg";
  4808. linux,phandle = <0x54>;
  4809. phandle = <0x54>;
  4810. };
  4811.  
  4812. qcom,dc-chgpth@1400 {
  4813. status = "ok";
  4814. reg = <0x1400 0x100>;
  4815. interrupts = <0x0 0x14 0x0 0x0 0x14 0x1>;
  4816. interrupt-names = "coarse-det-dc", "dcin-valid";
  4817. };
  4818.  
  4819. qcom,boost@1500 {
  4820. status = "ok";
  4821. reg = <0x1500 0x100>;
  4822. interrupts = <0x0 0x15 0x0 0x0 0x15 0x1>;
  4823. interrupt-names = "boost-pwr-ok", "limit-error";
  4824. regulator-min-microvolt = <0x4c4b40>;
  4825. regulator-max-microvolt = <0x4c4b40>;
  4826. regulator-name = "8941_smbb_boost";
  4827. linux,phandle = <0x55>;
  4828. phandle = <0x55>;
  4829. };
  4830.  
  4831. qcom,chg-misc@1600 {
  4832. status = "ok";
  4833. reg = <0x1600 0x100>;
  4834. };
  4835. };
  4836.  
  4837. gpios {
  4838. spmi-dev-container;
  4839. compatible = "qcom,qpnp-pin";
  4840. gpio-controller;
  4841. #gpio-cells = <0x2>;
  4842. #address-cells = <0x1>;
  4843. #size-cells = <0x1>;
  4844. label = "pm8941-gpio";
  4845. linux,phandle = <0x2a>;
  4846. phandle = <0x2a>;
  4847.  
  4848. gpio@c000 {
  4849. reg = <0xc000 0x100>;
  4850. qcom,pin-num = <0x1>;
  4851. qcom,mode = <0x0>;
  4852. qcom,pull = <0x0>;
  4853. qcom,master-en = <0x1>;
  4854. };
  4855.  
  4856. gpio@c100 {
  4857. reg = <0xc100 0x100>;
  4858. qcom,pin-num = <0x2>;
  4859. qcom,mode = <0x0>;
  4860. qcom,pull = <0x0>;
  4861. qcom,master-en = <0x1>;
  4862. };
  4863.  
  4864. gpio@c200 {
  4865. reg = <0xc200 0x100>;
  4866. qcom,pin-num = <0x3>;
  4867. qcom,mode = <0x0>;
  4868. qcom,pull = <0x0>;
  4869. qcom,vin-sel = <0x2>;
  4870. qcom,src-sel = <0x0>;
  4871. qcom,master-en = <0x1>;
  4872. };
  4873.  
  4874. gpio@c300 {
  4875. reg = <0xc300 0x100>;
  4876. qcom,pin-num = <0x4>;
  4877. qcom,mode = <0x0>;
  4878. qcom,pull = <0x0>;
  4879. qcom,vin-sel = <0x2>;
  4880. qcom,src-sel = <0x0>;
  4881. qcom,master-en = <0x1>;
  4882. };
  4883.  
  4884. gpio@c400 {
  4885. reg = <0xc400 0x100>;
  4886. qcom,pin-num = <0x5>;
  4887. qcom,mode = <0x0>;
  4888. qcom,pull = <0x0>;
  4889. qcom,vin-sel = <0x2>;
  4890. qcom,src-sel = <0x0>;
  4891. qcom,master-en = <0x1>;
  4892. };
  4893.  
  4894. gpio@c500 {
  4895. reg = <0xc500 0x100>;
  4896. qcom,pin-num = <0x6>;
  4897. qcom,mode = <0x0>;
  4898. qcom,pull = <0x0>;
  4899. qcom,master-en = <0x1>;
  4900. };
  4901.  
  4902. gpio@c600 {
  4903. reg = <0xc600 0x100>;
  4904. qcom,pin-num = <0x7>;
  4905. qcom,mode = <0x0>;
  4906. qcom,pull = <0x0>;
  4907. qcom,master-en = <0x1>;
  4908. };
  4909.  
  4910. gpio@c700 {
  4911. reg = <0xc700 0x100>;
  4912. qcom,pin-num = <0x8>;
  4913. qcom,mode = <0x0>;
  4914. qcom,pull = <0x0>;
  4915. qcom,master-en = <0x1>;
  4916. };
  4917.  
  4918. gpio@c800 {
  4919. reg = <0xc800 0x100>;
  4920. qcom,pin-num = <0x9>;
  4921. qcom,mode = <0x1>;
  4922. qcom,out-strength = <0x1>;
  4923. qcom,src-sel = <0x2>;
  4924. qcom,master-en = <0x1>;
  4925. };
  4926.  
  4927. gpio@c900 {
  4928. reg = <0xc900 0x100>;
  4929. qcom,pin-num = <0xa>;
  4930. qcom,mode = <0x1>;
  4931. qcom,out-strength = <0x1>;
  4932. qcom,src-sel = <0x2>;
  4933. qcom,master-en = <0x1>;
  4934. };
  4935.  
  4936. gpio@ca00 {
  4937. reg = <0xca00 0x100>;
  4938. qcom,pin-num = <0xb>;
  4939. qcom,mode = <0x1>;
  4940. qcom,out-strength = <0x1>;
  4941. qcom,src-sel = <0x2>;
  4942. qcom,master-en = <0x1>;
  4943. };
  4944.  
  4945. gpio@cb00 {
  4946. reg = <0xcb00 0x100>;
  4947. qcom,pin-num = <0xc>;
  4948. qcom,mode = <0x1>;
  4949. qcom,out-strength = <0x1>;
  4950. qcom,src-sel = <0x2>;
  4951. qcom,master-en = <0x1>;
  4952. };
  4953.  
  4954. gpio@cc00 {
  4955. reg = <0xcc00 0x100>;
  4956. qcom,pin-num = <0xd>;
  4957. qcom,mode = <0x1>;
  4958. qcom,out-strength = <0x1>;
  4959. qcom,src-sel = <0x2>;
  4960. qcom,master-en = <0x1>;
  4961. };
  4962.  
  4963. gpio@cd00 {
  4964. reg = <0xcd00 0x100>;
  4965. qcom,pin-num = <0xe>;
  4966. qcom,mode = <0x1>;
  4967. qcom,out-strength = <0x1>;
  4968. qcom,src-sel = <0x2>;
  4969. qcom,master-en = <0x1>;
  4970. };
  4971.  
  4972. gpio@ce00 {
  4973. reg = <0xce00 0x100>;
  4974. qcom,pin-num = <0xf>;
  4975. qcom,mode = <0x1>;
  4976. qcom,output-type = <0x0>;
  4977. qcom,pull = <0x5>;
  4978. qcom,vin-sel = <0x2>;
  4979. qcom,out-strength = <0x1>;
  4980. qcom,src-sel = <0x2>;
  4981. qcom,master-en = <0x1>;
  4982. };
  4983.  
  4984. gpio@cf00 {
  4985. reg = <0xcf00 0x100>;
  4986. qcom,pin-num = <0x10>;
  4987. qcom,mode = <0x1>;
  4988. qcom,output-type = <0x0>;
  4989. qcom,pull = <0x5>;
  4990. qcom,vin-sel = <0x2>;
  4991. qcom,out-strength = <0x3>;
  4992. qcom,src-sel = <0x3>;
  4993. qcom,master-en = <0x1>;
  4994. };
  4995.  
  4996. gpio@d000 {
  4997. reg = <0xd000 0x100>;
  4998. qcom,pin-num = <0x11>;
  4999. };
  5000.  
  5001. gpio@d100 {
  5002. reg = <0xd100 0x100>;
  5003. qcom,pin-num = <0x12>;
  5004. };
  5005.  
  5006. gpio@d200 {
  5007. reg = <0xd200 0x100>;
  5008. qcom,pin-num = <0x13>;
  5009. qcom,mode = <0x1>;
  5010. qcom,output-type = <0x0>;
  5011. qcom,pull = <0x5>;
  5012. qcom,vin-sel = <0x2>;
  5013. qcom,out-strength = <0x1>;
  5014. qcom,src-sel = <0x0>;
  5015. qcom,master-en = <0x1>;
  5016. };
  5017.  
  5018. gpio@d300 {
  5019. reg = <0xd300 0x100>;
  5020. qcom,pin-num = <0x14>;
  5021. qcom,mode = <0x1>;
  5022. qcom,out-strength = <0x1>;
  5023. qcom,src-sel = <0x2>;
  5024. qcom,master-en = <0x1>;
  5025. };
  5026.  
  5027. gpio@d400 {
  5028. reg = <0xd400 0x100>;
  5029. qcom,pin-num = <0x15>;
  5030. };
  5031.  
  5032. gpio@d500 {
  5033. reg = <0xd500 0x100>;
  5034. qcom,pin-num = <0x16>;
  5035. qcom,mode = <0x0>;
  5036. qcom,pull = <0x4>;
  5037. qcom,master-en = <0x1>;
  5038. };
  5039.  
  5040. gpio@d600 {
  5041. reg = <0xd600 0x100>;
  5042. qcom,pin-num = <0x17>;
  5043. qcom,mode = <0x1>;
  5044. qcom,out-strength = <0x1>;
  5045. qcom,src-sel = <0x2>;
  5046. qcom,master-en = <0x1>;
  5047. };
  5048.  
  5049. gpio@d700 {
  5050. reg = <0xd700 0x100>;
  5051. qcom,pin-num = <0x18>;
  5052. qcom,mode = <0x1>;
  5053. qcom,out-strength = <0x1>;
  5054. qcom,src-sel = <0x2>;
  5055. qcom,master-en = <0x1>;
  5056. };
  5057.  
  5058. gpio@d800 {
  5059. reg = <0xd800 0x100>;
  5060. qcom,pin-num = <0x19>;
  5061. qcom,mode = <0x1>;
  5062. qcom,out-strength = <0x1>;
  5063. qcom,src-sel = <0x2>;
  5064. qcom,master-en = <0x1>;
  5065. };
  5066.  
  5067. gpio@d900 {
  5068. reg = <0xd900 0x100>;
  5069. qcom,pin-num = <0x1a>;
  5070. qcom,mode = <0x1>;
  5071. qcom,out-strength = <0x1>;
  5072. qcom,src-sel = <0x2>;
  5073. qcom,master-en = <0x1>;
  5074. };
  5075.  
  5076. gpio@da00 {
  5077. reg = <0xda00 0x100>;
  5078. qcom,pin-num = <0x1b>;
  5079. qcom,mode = <0x0>;
  5080. qcom,pull = <0x4>;
  5081. qcom,master-en = <0x1>;
  5082. };
  5083.  
  5084. gpio@db00 {
  5085. reg = <0xdb00 0x100>;
  5086. qcom,pin-num = <0x1c>;
  5087. };
  5088.  
  5089. gpio@dc00 {
  5090. reg = <0xdc00 0x100>;
  5091. qcom,pin-num = <0x1d>;
  5092. qcom,mode = <0x1>;
  5093. qcom,out-strength = <0x1>;
  5094. qcom,src-sel = <0x2>;
  5095. qcom,master-en = <0x1>;
  5096. };
  5097.  
  5098. gpio@dd00 {
  5099. reg = <0xdd00 0x100>;
  5100. qcom,pin-num = <0x1e>;
  5101. qcom,mode = <0x0>;
  5102. qcom,pull = <0x4>;
  5103. qcom,master-en = <0x1>;
  5104. };
  5105.  
  5106. gpio@de00 {
  5107. reg = <0xde00 0x100>;
  5108. qcom,pin-num = <0x1f>;
  5109. };
  5110.  
  5111. gpio@df00 {
  5112. reg = <0xdf00 0x100>;
  5113. qcom,pin-num = <0x20>;
  5114. qcom,mode = <0x0>;
  5115. qcom,pull = <0x4>;
  5116. qcom,vin-sel = <0x2>;
  5117. qcom,src-sel = <0x2>;
  5118. qcom,master-en = <0x1>;
  5119. };
  5120.  
  5121. gpio@e000 {
  5122. reg = <0xe000 0x100>;
  5123. qcom,pin-num = <0x21>;
  5124. qcom,mode = <0x0>;
  5125. qcom,pull = <0x4>;
  5126. qcom,master-en = <0x1>;
  5127. };
  5128.  
  5129. gpio@e100 {
  5130. reg = <0xe100 0x100>;
  5131. qcom,pin-num = <0x22>;
  5132. qcom,mode = <0x0>;
  5133. qcom,pull = <0x4>;
  5134. qcom,master-en = <0x1>;
  5135. };
  5136.  
  5137. gpio@e200 {
  5138. reg = <0xe200 0x100>;
  5139. qcom,pin-num = <0x23>;
  5140. qcom,mode = <0x0>;
  5141. qcom,pull = <0x4>;
  5142. qcom,master-en = <0x1>;
  5143. };
  5144.  
  5145. gpio@e300 {
  5146. reg = <0xe300 0x100>;
  5147. qcom,pin-num = <0x24>;
  5148. };
  5149. };
  5150.  
  5151. mpps {
  5152. spmi-dev-container;
  5153. compatible = "qcom,qpnp-pin";
  5154. gpio-controller;
  5155. #gpio-cells = <0x2>;
  5156. #address-cells = <0x1>;
  5157. #size-cells = <0x1>;
  5158. label = "pm8941-mpp";
  5159. linux,phandle = <0x58>;
  5160. phandle = <0x58>;
  5161.  
  5162. mpp@a000 {
  5163. reg = <0xa000 0x100>;
  5164. qcom,pin-num = <0x1>;
  5165. status = "disabled";
  5166. };
  5167.  
  5168. mpp@a100 {
  5169. reg = <0xa100 0x100>;
  5170. qcom,pin-num = <0x2>;
  5171. qcom,mode = <0x1>;
  5172. qcom,out-strength = <0x1>;
  5173. qcom,master-en = <0x1>;
  5174. };
  5175.  
  5176. mpp@a200 {
  5177. reg = <0xa200 0x100>;
  5178. qcom,pin-num = <0x3>;
  5179. };
  5180.  
  5181. mpp@a300 {
  5182. reg = <0xa300 0x100>;
  5183. qcom,pin-num = <0x4>;
  5184. };
  5185.  
  5186. mpp@a400 {
  5187. reg = <0xa400 0x100>;
  5188. qcom,pin-num = <0x5>;
  5189. };
  5190.  
  5191. mpp@a500 {
  5192. reg = <0xa500 0x100>;
  5193. qcom,pin-num = <0x6>;
  5194. qcom,mode = <0x1>;
  5195. qcom,output-type = <0x0>;
  5196. qcom,vin-sel = <0x2>;
  5197. qcom,src-sel = <0x0>;
  5198. qcom,out-strength = <0x1>;
  5199. qcom,master-en = <0x1>;
  5200. };
  5201.  
  5202. mpp@a600 {
  5203. reg = <0xa600 0x100>;
  5204. qcom,pin-num = <0x7>;
  5205. qcom,mode = <0x1>;
  5206. qcom,out-strength = <0x1>;
  5207. qcom,master-en = <0x1>;
  5208. };
  5209.  
  5210. mpp@a700 {
  5211. reg = <0xa700 0x100>;
  5212. qcom,pin-num = <0x8>;
  5213. qcom,mode = <0x1>;
  5214. qcom,out-strength = <0x1>;
  5215. qcom,master-en = <0x1>;
  5216. };
  5217. };
  5218.  
  5219. qcom,pm8941_rtc {
  5220. spmi-dev-container;
  5221. compatible = "qcom,qpnp-rtc";
  5222. #address-cells = <0x1>;
  5223. #size-cells = <0x1>;
  5224. qcom,qpnp-rtc-write = <0x0>;
  5225. qcom,qpnp-rtc-alarm-pwrup = <0x0>;
  5226.  
  5227. qcom,pm8941_rtc_rw@6000 {
  5228. reg = <0x6000 0x100>;
  5229. };
  5230.  
  5231. qcom,pm8941_rtc_alarm@6100 {
  5232. reg = <0x6100 0x100>;
  5233. interrupts = <0x0 0x61 0x1>;
  5234. };
  5235. };
  5236.  
  5237. vadc@3100 {
  5238. compatible = "qcom,qpnp-vadc";
  5239. reg = <0x3100 0x100>;
  5240. #address-cells = <0x1>;
  5241. #size-cells = <0x0>;
  5242. interrupts = <0x0 0x31 0x0>;
  5243. interrupt-names = "eoc-int-en-set";
  5244. qcom,adc-bit-resolution = <0xf>;
  5245. qcom,adc-vdd-reference = <0x708>;
  5246. qcom,vadc-poll-eoc;
  5247. qcom,pmic-revid = <0x53>;
  5248. linux,phandle = <0x4f>;
  5249. phandle = <0x4f>;
  5250.  
  5251. chan@0 {
  5252. label = "usb_in";
  5253. reg = <0x0>;
  5254. qcom,decimation = <0x0>;
  5255. qcom,pre-div-channel-scaling = <0x4>;
  5256. qcom,calibration-type = "absolute";
  5257. qcom,scale-function = <0x0>;
  5258. qcom,hw-settle-time = <0x0>;
  5259. qcom,fast-avg-setup = <0x0>;
  5260. };
  5261.  
  5262. chan@1 {
  5263. label = "dc_in";
  5264. reg = <0x1>;
  5265. qcom,decimation = <0x0>;
  5266. qcom,pre-div-channel-scaling = <0x4>;
  5267. qcom,calibration-type = "absolute";
  5268. qcom,scale-function = <0x0>;
  5269. qcom,hw-settle-time = <0x0>;
  5270. qcom,fast-avg-setup = <0x0>;
  5271. };
  5272.  
  5273. chan@2 {
  5274. label = "vchg_sns";
  5275. reg = <0x2>;
  5276. qcom,decimation = <0x0>;
  5277. qcom,pre-div-channel-scaling = <0x3>;
  5278. qcom,calibration-type = "absolute";
  5279. qcom,scale-function = <0x0>;
  5280. qcom,hw-settle-time = <0x0>;
  5281. qcom,fast-avg-setup = <0x0>;
  5282. };
  5283.  
  5284. chan@3 {
  5285. label = "spare1_div3";
  5286. reg = <0x3>;
  5287. qcom,decimation = <0x0>;
  5288. qcom,pre-div-channel-scaling = <0x1>;
  5289. qcom,calibration-type = "absolute";
  5290. qcom,scale-function = <0x0>;
  5291. qcom,hw-settle-time = <0x0>;
  5292. qcom,fast-avg-setup = <0x0>;
  5293. };
  5294.  
  5295. chan@4 {
  5296. label = "usb_id_mv";
  5297. reg = <0x4>;
  5298. qcom,decimation = <0x0>;
  5299. qcom,pre-div-channel-scaling = <0x1>;
  5300. qcom,calibration-type = "absolute";
  5301. qcom,scale-function = <0x0>;
  5302. qcom,hw-settle-time = <0x0>;
  5303. qcom,fast-avg-setup = <0x0>;
  5304. };
  5305.  
  5306. chan@5 {
  5307. label = "vcoin";
  5308. reg = <0x5>;
  5309. qcom,decimation = <0x0>;
  5310. qcom,pre-div-channel-scaling = <0x1>;
  5311. qcom,calibration-type = "absolute";
  5312. qcom,scale-function = <0x0>;
  5313. qcom,hw-settle-time = <0x0>;
  5314. qcom,fast-avg-setup = <0x0>;
  5315. };
  5316.  
  5317. chan@6 {
  5318. label = "vbat_sns";
  5319. reg = <0x6>;
  5320. qcom,decimation = <0x0>;
  5321. qcom,pre-div-channel-scaling = <0x1>;
  5322. qcom,calibration-type = "absolute";
  5323. qcom,scale-function = <0x0>;
  5324. qcom,hw-settle-time = <0x0>;
  5325. qcom,fast-avg-setup = <0x0>;
  5326. };
  5327.  
  5328. chan@7 {
  5329. label = "vph_pwr";
  5330. reg = <0x7>;
  5331. qcom,decimation = <0x0>;
  5332. qcom,pre-div-channel-scaling = <0x1>;
  5333. qcom,calibration-type = "absolute";
  5334. qcom,scale-function = <0x0>;
  5335. qcom,hw-settle-time = <0x0>;
  5336. qcom,fast-avg-setup = <0x0>;
  5337. };
  5338.  
  5339. chan@8 {
  5340. label = "die_temp";
  5341. reg = <0x8>;
  5342. qcom,decimation = <0x0>;
  5343. qcom,pre-div-channel-scaling = <0x0>;
  5344. qcom,calibration-type = "absolute";
  5345. qcom,scale-function = <0x3>;
  5346. qcom,hw-settle-time = <0x0>;
  5347. qcom,fast-avg-setup = <0x0>;
  5348. };
  5349.  
  5350. chan@9 {
  5351. label = "ref_625mv";
  5352. reg = <0x9>;
  5353. qcom,decimation = <0x0>;
  5354. qcom,pre-div-channel-scaling = <0x0>;
  5355. qcom,calibration-type = "absolute";
  5356. qcom,scale-function = <0x0>;
  5357. qcom,hw-settle-time = <0x0>;
  5358. qcom,fast-avg-setup = <0x0>;
  5359. };
  5360.  
  5361. chan@a {
  5362. label = "ref_1250v";
  5363. reg = <0xa>;
  5364. qcom,decimation = <0x0>;
  5365. qcom,pre-div-channel-scaling = <0x0>;
  5366. qcom,calibration-type = "absolute";
  5367. qcom,scale-function = <0x0>;
  5368. qcom,hw-settle-time = <0x0>;
  5369. qcom,fast-avg-setup = <0x0>;
  5370. };
  5371.  
  5372. chan@30 {
  5373. label = "batt_therm";
  5374. reg = <0x30>;
  5375. qcom,decimation = <0x0>;
  5376. qcom,pre-div-channel-scaling = <0x0>;
  5377. qcom,calibration-type = "ratiometric";
  5378. qcom,scale-function = <0x1>;
  5379. qcom,hw-settle-time = <0x2>;
  5380. qcom,fast-avg-setup = <0x0>;
  5381. };
  5382.  
  5383. chan@31 {
  5384. label = "batt_id";
  5385. reg = <0x31>;
  5386. qcom,decimation = <0x0>;
  5387. qcom,pre-div-channel-scaling = <0x0>;
  5388. qcom,calibration-type = "ratiometric";
  5389. qcom,scale-function = <0x0>;
  5390. qcom,hw-settle-time = <0x2>;
  5391. qcom,fast-avg-setup = <0x0>;
  5392. };
  5393.  
  5394. chan@b2 {
  5395. label = "xo_therm_pu2";
  5396. reg = <0xb2>;
  5397. qcom,decimation = <0x0>;
  5398. qcom,pre-div-channel-scaling = <0x0>;
  5399. qcom,calibration-type = "ratiometric";
  5400. qcom,scale-function = <0x4>;
  5401. qcom,hw-settle-time = <0x2>;
  5402. qcom,fast-avg-setup = <0x0>;
  5403. };
  5404.  
  5405. chan@b3 {
  5406. label = "msm_therm";
  5407. reg = <0xb3>;
  5408. qcom,decimation = <0x0>;
  5409. qcom,pre-div-channel-scaling = <0x0>;
  5410. qcom,calibration-type = "ratiometric";
  5411. qcom,scale-function = <0x2>;
  5412. qcom,hw-settle-time = <0x2>;
  5413. qcom,fast-avg-setup = <0x0>;
  5414. };
  5415.  
  5416. chan@b4 {
  5417. label = "emmc_therm";
  5418. reg = <0xb4>;
  5419. qcom,decimation = <0x0>;
  5420. qcom,pre-div-channel-scaling = <0x0>;
  5421. qcom,calibration-type = "ratiometric";
  5422. qcom,scale-function = <0x2>;
  5423. qcom,hw-settle-time = <0x2>;
  5424. qcom,fast-avg-setup = <0x0>;
  5425. };
  5426.  
  5427. chan@b5 {
  5428. label = "pa_therm0";
  5429. reg = <0xb5>;
  5430. qcom,decimation = <0x0>;
  5431. qcom,pre-div-channel-scaling = <0x0>;
  5432. qcom,calibration-type = "ratiometric";
  5433. qcom,scale-function = <0x2>;
  5434. qcom,hw-settle-time = <0x2>;
  5435. qcom,fast-avg-setup = <0x0>;
  5436. };
  5437.  
  5438. chan@b6 {
  5439. label = "amux_in";
  5440. reg = <0xb6>;
  5441. qcom,decimation = <0x0>;
  5442. qcom,pre-div-channel-scaling = <0x0>;
  5443. qcom,calibration-type = "ratiometric";
  5444. qcom,scale-function = <0x0>;
  5445. qcom,hw-settle-time = <0x2>;
  5446. qcom,fast-avg-setup = <0x0>;
  5447. };
  5448.  
  5449. chan@b7 {
  5450. label = "pa_therm1";
  5451. reg = <0xb7>;
  5452. qcom,decimation = <0x0>;
  5453. qcom,pre-div-channel-scaling = <0x0>;
  5454. qcom,calibration-type = "ratiometric";
  5455. qcom,scale-function = <0x2>;
  5456. qcom,hw-settle-time = <0x2>;
  5457. qcom,fast-avg-setup = <0x0>;
  5458. };
  5459.  
  5460. chan@b8 {
  5461. label = "quiet_therm";
  5462. reg = <0xb8>;
  5463. qcom,decimation = <0x0>;
  5464. qcom,pre-div-channel-scaling = <0x0>;
  5465. qcom,calibration-type = "ratiometric";
  5466. qcom,scale-function = <0x2>;
  5467. qcom,hw-settle-time = <0x2>;
  5468. qcom,fast-avg-setup = <0x0>;
  5469. };
  5470.  
  5471. chan@b9 {
  5472. label = "usb_id";
  5473. reg = <0xb9>;
  5474. qcom,decimation = <0x0>;
  5475. qcom,pre-div-channel-scaling = <0x0>;
  5476. qcom,calibration-type = "ratiometric";
  5477. qcom,scale-function = <0x0>;
  5478. qcom,hw-settle-time = <0x2>;
  5479. qcom,fast-avg-setup = <0x0>;
  5480. };
  5481.  
  5482. chan@39 {
  5483. label = "usb_id_nopull";
  5484. reg = <0x39>;
  5485. qcom,decimation = <0x0>;
  5486. qcom,pre-div-channel-scaling = <0x0>;
  5487. qcom,calibration-type = "ratiometric";
  5488. qcom,scale-function = <0x0>;
  5489. qcom,hw-settle-time = <0x2>;
  5490. qcom,fast-avg-setup = <0x0>;
  5491. };
  5492. };
  5493.  
  5494. iadc@3600 {
  5495. compatible = "qcom,qpnp-iadc";
  5496. reg = <0x3600 0x100 0x12f1 0x1>;
  5497. reg-names = "iadc-base", "batt-id-trim-cnst-rds";
  5498. #address-cells = <0x1>;
  5499. #size-cells = <0x0>;
  5500. interrupts = <0x0 0x36 0x0>;
  5501. interrupt-names = "eoc-int-en-set";
  5502. qcom,adc-bit-resolution = <0x10>;
  5503. qcom,adc-vdd-reference = <0x708>;
  5504. qcom,iadc-vadc = <0x4f>;
  5505. qcom,iadc-poll-eoc;
  5506. qcom,use-default-rds-trim = <0x0>;
  5507. qcom,pmic-revid = <0x53>;
  5508. linux,phandle = <0x50>;
  5509. phandle = <0x50>;
  5510.  
  5511. chan@0 {
  5512. label = "internal_rsense";
  5513. reg = <0x0>;
  5514. qcom,decimation = <0x0>;
  5515. qcom,fast-avg-setup = <0x0>;
  5516. };
  5517. };
  5518.  
  5519. qcom,vadc@3400 {
  5520. compatible = "qcom,qpnp-adc-tm";
  5521. reg = <0x3400 0x100>;
  5522. #address-cells = <0x1>;
  5523. #size-cells = <0x0>;
  5524. interrupts = <0x0 0x34 0x0 0x0 0x34 0x3 0x0 0x34 0x4>;
  5525. interrupt-names = "eoc-int-en-set", "high-thr-en-set", "low-thr-en-set";
  5526. qcom,adc-bit-resolution = <0xf>;
  5527. qcom,adc-vdd-reference = <0x708>;
  5528. qcom,adc_tm-vadc = <0x4f>;
  5529. linux,phandle = <0x51>;
  5530. phandle = <0x51>;
  5531.  
  5532. chan@b9 {
  5533. label = "usb_id";
  5534. reg = <0xb9>;
  5535. qcom,decimation = <0x0>;
  5536. qcom,pre-div-channel-scaling = <0x0>;
  5537. qcom,calibration-type = "ratiometric";
  5538. qcom,scale-function = <0x2>;
  5539. qcom,hw-settle-time = <0x2>;
  5540. qcom,fast-avg-setup = <0x3>;
  5541. qcom,btm-channel-number = <0x48>;
  5542. };
  5543.  
  5544. chan@30 {
  5545. label = "batt_therm";
  5546. reg = <0x30>;
  5547. qcom,decimation = <0x0>;
  5548. qcom,pre-div-channel-scaling = <0x0>;
  5549. qcom,calibration-type = "ratiometric";
  5550. qcom,scale-function = <0x1>;
  5551. qcom,hw-settle-time = <0x2>;
  5552. qcom,fast-avg-setup = <0x3>;
  5553. qcom,btm-channel-number = <0x68>;
  5554. qcom,meas-interval-timer-idx = <0x2>;
  5555. };
  5556.  
  5557. chan@8 {
  5558. label = "die_temp";
  5559. reg = <0x8>;
  5560. qcom,decimation = <0x0>;
  5561. qcom,pre-div-channel-scaling = <0x0>;
  5562. qcom,calibration-type = "absolute";
  5563. qcom,scale-function = <0x3>;
  5564. qcom,hw-settle-time = <0x0>;
  5565. qcom,fast-avg-setup = <0x3>;
  5566. qcom,btm-channel-number = <0x70>;
  5567. };
  5568.  
  5569. chan@6 {
  5570. label = "vbat_sns";
  5571. reg = <0x6>;
  5572. qcom,decimation = <0x0>;
  5573. qcom,pre-div-channel-scaling = <0x1>;
  5574. qcom,calibration-type = "absolute";
  5575. qcom,scale-function = <0x0>;
  5576. qcom,hw-settle-time = <0x0>;
  5577. qcom,fast-avg-setup = <0x3>;
  5578. qcom,btm-channel-number = <0x78>;
  5579. };
  5580.  
  5581. chan@b5 {
  5582. label = "pa_therm0";
  5583. reg = <0xb5>;
  5584. qcom,decimation = <0x0>;
  5585. qcom,pre-div-channel-scaling = <0x0>;
  5586. qcom,calibration-type = "ratiometric";
  5587. qcom,scale-function = <0x2>;
  5588. qcom,hw-settle-time = <0x2>;
  5589. qcom,fast-avg-setup = <0x3>;
  5590. qcom,btm-channel-number = <0x80>;
  5591. qcom,thermal-node;
  5592. };
  5593.  
  5594. chan@b7 {
  5595. label = "pa_therm1";
  5596. reg = <0xb7>;
  5597. qcom,decimation = <0x0>;
  5598. qcom,pre-div-channel-scaling = <0x0>;
  5599. qcom,calibration-type = "ratiometric";
  5600. qcom,scale-function = <0x2>;
  5601. qcom,hw-settle-time = <0x2>;
  5602. qcom,fast-avg-setup = <0x3>;
  5603. qcom,btm-channel-number = <0x88>;
  5604. qcom,thermal-node;
  5605. };
  5606.  
  5607. chan@b4 {
  5608. label = "emmc_therm";
  5609. reg = <0xb4>;
  5610. qcom,decimation = <0x0>;
  5611. qcom,pre-div-channel-scaling = <0x0>;
  5612. qcom,calibration-type = "ratiometric";
  5613. qcom,scale-function = <0x2>;
  5614. qcom,hw-settle-time = <0x2>;
  5615. qcom,fast-avg-setup = <0x3>;
  5616. qcom,btm-channel-number = <0x90>;
  5617. qcom,thermal-node;
  5618. };
  5619.  
  5620. chan@b3 {
  5621. label = "msm_therm";
  5622. reg = <0xb3>;
  5623. qcom,decimation = <0x0>;
  5624. qcom,pre-div-channel-scaling = <0x0>;
  5625. qcom,calibration-type = "ratiometric";
  5626. qcom,scale-function = <0x2>;
  5627. qcom,hw-settle-time = <0x2>;
  5628. qcom,fast-avg-setup = <0x3>;
  5629. qcom,btm-channel-number = <0x98>;
  5630. qcom,thermal-node;
  5631. };
  5632. };
  5633. };
  5634.  
  5635. qcom,pm8941@1 {
  5636. reg = <0x1>;
  5637. spmi-slave-container;
  5638. #address-cells = <0x1>;
  5639. #size-cells = <0x1>;
  5640.  
  5641. regulator@1400 {
  5642. regulator-name = "8941_s1";
  5643. spmi-dev-container;
  5644. #address-cells = <0x1>;
  5645. #size-cells = <0x1>;
  5646. compatible = "qcom,qpnp-regulator";
  5647. reg = <0x1400 0x300>;
  5648. status = "disabled";
  5649.  
  5650. qcom,ctl@1400 {
  5651. reg = <0x1400 0x100>;
  5652. };
  5653.  
  5654. qcom,ps@1500 {
  5655. reg = <0x1500 0x100>;
  5656. };
  5657.  
  5658. qcom,freq@1600 {
  5659. reg = <0x1600 0x100>;
  5660. };
  5661. };
  5662.  
  5663. regulator@1700 {
  5664. regulator-name = "8941_s2";
  5665. spmi-dev-container;
  5666. #address-cells = <0x1>;
  5667. #size-cells = <0x1>;
  5668. compatible = "qcom,qpnp-regulator";
  5669. reg = <0x1700 0x300>;
  5670. status = "disabled";
  5671.  
  5672. qcom,ctl@1700 {
  5673. reg = <0x1700 0x100>;
  5674. };
  5675.  
  5676. qcom,ps@1800 {
  5677. reg = <0x1800 0x100>;
  5678. };
  5679.  
  5680. qcom,freq@1900 {
  5681. reg = <0x1900 0x100>;
  5682. };
  5683. };
  5684.  
  5685. regulator@1a00 {
  5686. regulator-name = "8941_s3";
  5687. spmi-dev-container;
  5688. #address-cells = <0x1>;
  5689. #size-cells = <0x1>;
  5690. compatible = "qcom,qpnp-regulator";
  5691. reg = <0x1a00 0x300>;
  5692. status = "disabled";
  5693.  
  5694. qcom,ctl@1a00 {
  5695. reg = <0x1a00 0x100>;
  5696. };
  5697.  
  5698. qcom,ps@1b00 {
  5699. reg = <0x1b00 0x100>;
  5700. };
  5701.  
  5702. qcom,freq@1c00 {
  5703. reg = <0x1c00 0x100>;
  5704. };
  5705. };
  5706.  
  5707. regulator@a000 {
  5708. regulator-name = "8941_boost";
  5709. reg = <0xa000 0x100>;
  5710. compatible = "qcom,qpnp-regulator";
  5711. status = "okay";
  5712. regulator-min-microvolt = <0x4c4b40>;
  5713. regulator-max-microvolt = <0x4c4b40>;
  5714. qcom,enable-time = <0x1f4>;
  5715. linux,phandle = <0x4d>;
  5716. phandle = <0x4d>;
  5717. };
  5718.  
  5719. regulator@4000 {
  5720. regulator-name = "8941_l1";
  5721. reg = <0x4000 0x100>;
  5722. compatible = "qcom,qpnp-regulator";
  5723. status = "disabled";
  5724. };
  5725.  
  5726. regulator@4100 {
  5727. regulator-name = "8941_l2";
  5728. reg = <0x4100 0x100>;
  5729. compatible = "qcom,qpnp-regulator";
  5730. status = "disabled";
  5731. };
  5732.  
  5733. regulator@4200 {
  5734. regulator-name = "8941_l3";
  5735. reg = <0x4200 0x100>;
  5736. compatible = "qcom,qpnp-regulator";
  5737. status = "disabled";
  5738. };
  5739.  
  5740. regulator@4300 {
  5741. regulator-name = "8941_l4";
  5742. reg = <0x4300 0x100>;
  5743. compatible = "qcom,qpnp-regulator";
  5744. status = "disabled";
  5745. };
  5746.  
  5747. regulator@4400 {
  5748. regulator-name = "8941_l5";
  5749. reg = <0x4400 0x100>;
  5750. compatible = "qcom,qpnp-regulator";
  5751. qcom,force-type = <0x4 0x10>;
  5752. status = "disabled";
  5753. };
  5754.  
  5755. regulator@4500 {
  5756. regulator-name = "8941_l6";
  5757. reg = <0x4500 0x100>;
  5758. compatible = "qcom,qpnp-regulator";
  5759. status = "disabled";
  5760. };
  5761.  
  5762. regulator@4600 {
  5763. regulator-name = "8941_l7";
  5764. reg = <0x4600 0x100>;
  5765. compatible = "qcom,qpnp-regulator";
  5766. qcom,force-type = <0x4 0x10>;
  5767. status = "disabled";
  5768. };
  5769.  
  5770. regulator@4700 {
  5771. regulator-name = "8941_l8";
  5772. reg = <0x4700 0x100>;
  5773. compatible = "qcom,qpnp-regulator";
  5774. status = "disabled";
  5775. };
  5776.  
  5777. regulator@4800 {
  5778. regulator-name = "8941_l9";
  5779. reg = <0x4800 0x100>;
  5780. compatible = "qcom,qpnp-regulator";
  5781. status = "disabled";
  5782. };
  5783.  
  5784. regulator@4900 {
  5785. regulator-name = "8941_l10";
  5786. reg = <0x4900 0x100>;
  5787. compatible = "qcom,qpnp-regulator";
  5788. status = "disabled";
  5789. };
  5790.  
  5791. regulator@4a00 {
  5792. regulator-name = "8941_l11";
  5793. reg = <0x4a00 0x100>;
  5794. compatible = "qcom,qpnp-regulator";
  5795. status = "disabled";
  5796. };
  5797.  
  5798. regulator@4b00 {
  5799. regulator-name = "8941_l12";
  5800. reg = <0x4b00 0x100>;
  5801. compatible = "qcom,qpnp-regulator";
  5802. status = "disabled";
  5803. };
  5804.  
  5805. regulator@4c00 {
  5806. regulator-name = "8941_l13";
  5807. reg = <0x4c00 0x100>;
  5808. compatible = "qcom,qpnp-regulator";
  5809. status = "disabled";
  5810. };
  5811.  
  5812. regulator@4d00 {
  5813. regulator-name = "8941_l14";
  5814. reg = <0x4d00 0x100>;
  5815. compatible = "qcom,qpnp-regulator";
  5816. status = "disabled";
  5817. };
  5818.  
  5819. regulator@4e00 {
  5820. regulator-name = "8941_l15";
  5821. reg = <0x4e00 0x100>;
  5822. compatible = "qcom,qpnp-regulator";
  5823. status = "disabled";
  5824. };
  5825.  
  5826. regulator@4f00 {
  5827. regulator-name = "8941_l16";
  5828. reg = <0x4f00 0x100>;
  5829. compatible = "qcom,qpnp-regulator";
  5830. status = "disabled";
  5831. };
  5832.  
  5833. regulator@5000 {
  5834. regulator-name = "8941_l17";
  5835. reg = <0x5000 0x100>;
  5836. compatible = "qcom,qpnp-regulator";
  5837. status = "disabled";
  5838. };
  5839.  
  5840. regulator@5100 {
  5841. regulator-name = "8941_l18";
  5842. reg = <0x5100 0x100>;
  5843. compatible = "qcom,qpnp-regulator";
  5844. status = "disabled";
  5845. };
  5846.  
  5847. regulator@5200 {
  5848. regulator-name = "8941_l19";
  5849. reg = <0x5200 0x100>;
  5850. compatible = "qcom,qpnp-regulator";
  5851. status = "disabled";
  5852. };
  5853.  
  5854. regulator@5300 {
  5855. regulator-name = "8941_l20";
  5856. reg = <0x5300 0x100>;
  5857. compatible = "qcom,qpnp-regulator";
  5858. status = "disabled";
  5859. };
  5860.  
  5861. regulator@5400 {
  5862. regulator-name = "8941_l21";
  5863. reg = <0x5400 0x100>;
  5864. compatible = "qcom,qpnp-regulator";
  5865. status = "disabled";
  5866. };
  5867.  
  5868. regulator@5500 {
  5869. regulator-name = "8941_l22";
  5870. reg = <0x5500 0x100>;
  5871. compatible = "qcom,qpnp-regulator";
  5872. status = "disabled";
  5873. };
  5874.  
  5875. regulator@5600 {
  5876. regulator-name = "8941_l23";
  5877. reg = <0x5600 0x100>;
  5878. compatible = "qcom,qpnp-regulator";
  5879. status = "disabled";
  5880. };
  5881.  
  5882. regulator@5700 {
  5883. regulator-name = "8941_l24";
  5884. reg = <0x5700 0x100>;
  5885. compatible = "qcom,qpnp-regulator";
  5886. status = "disabled";
  5887. };
  5888.  
  5889. regulator@8000 {
  5890. regulator-name = "8941_lvs1";
  5891. reg = <0x8000 0x100>;
  5892. compatible = "qcom,qpnp-regulator";
  5893. status = "disabled";
  5894. };
  5895.  
  5896. regulator@8100 {
  5897. regulator-name = "8941_lvs2";
  5898. reg = <0x8100 0x100>;
  5899. compatible = "qcom,qpnp-regulator";
  5900. status = "disabled";
  5901. };
  5902.  
  5903. regulator@8200 {
  5904. regulator-name = "8941_lvs3";
  5905. reg = <0x8200 0x100>;
  5906. compatible = "qcom,qpnp-regulator";
  5907. status = "disabled";
  5908. };
  5909.  
  5910. regulator@8300 {
  5911. regulator-name = "8941_mvs1";
  5912. reg = <0x8300 0x100>;
  5913. compatible = "qcom,qpnp-regulator";
  5914. status = "okay";
  5915. parent-supply = <0x54>;
  5916. qcom,enable-time = <0x3e8>;
  5917. qcom,pull-down-enable = <0x1>;
  5918. interrupts = <0x1 0x83 0x2>;
  5919. interrupt-names = "ocp";
  5920. qcom,ocp-enable = <0x1>;
  5921. qcom,ocp-max-retries = <0xa>;
  5922. qcom,ocp-retry-delay = <0x1e>;
  5923. qcom,soft-start-enable = <0x1>;
  5924. qcom,vs-soft-start-strength = <0x0>;
  5925. qcom,hpm-enable = <0x1>;
  5926. qcom,auto-mode-enable = <0x0>;
  5927. linux,phandle = <0x62>;
  5928. phandle = <0x62>;
  5929. };
  5930.  
  5931. regulator@8400 {
  5932. regulator-name = "8941_mvs2";
  5933. reg = <0x8400 0x100>;
  5934. compatible = "qcom,qpnp-regulator";
  5935. status = "okay";
  5936. parent-supply = <0x4d>;
  5937. qcom,enable-time = <0x3e8>;
  5938. qcom,pull-down-enable = <0x1>;
  5939. interrupts = <0x1 0x84 0x2>;
  5940. interrupt-names = "ocp";
  5941. qcom,ocp-enable = <0x1>;
  5942. qcom,ocp-max-retries = <0xa>;
  5943. qcom,ocp-retry-delay = <0x1e>;
  5944. qcom,soft-start-enable = <0x1>;
  5945. qcom,vs-soft-start-strength = <0x0>;
  5946. qcom,hpm-enable = <0x1>;
  5947. qcom,auto-mode-enable = <0x0>;
  5948. linux,phandle = <0x2c>;
  5949. phandle = <0x2c>;
  5950. };
  5951.  
  5952. qcom,vibrator@c000 {
  5953. compatible = "qcom,qpnp-vibrator";
  5954. reg = <0xc000 0x100>;
  5955. label = "vibrator";
  5956. status = "disabled";
  5957. };
  5958.  
  5959. qcom,leds@d000 {
  5960. compatible = "qcom,leds-qpnp";
  5961. reg = <0xd000 0x100>;
  5962. label = "rgb";
  5963. status = "okay";
  5964.  
  5965. qcom,rgb_0 {
  5966. label = "rgb";
  5967. linux,name = "red";
  5968. qcom,mode = "pwm";
  5969. qcom,pwm-channel = <0x6>;
  5970. qcom,pwm-us = <0x3e8>;
  5971. qcom,max-current = <0xc>;
  5972. qcom,default-state = "off";
  5973. qcom,id = <0x3>;
  5974. linux,default-trigger = "none";
  5975. qcom,start-idx = <0x1>;
  5976. qcom,duty-pcts = [00 00 00 00 00 00 00 00 00 00 00 19 32 4b 64 64 32 19 00 00 00 00 00 00 00 00 00 00 00];
  5977. qcom,lut-flags = <0x3>;
  5978. qcom,pause-lo = <0x0>;
  5979. qcom,pause-hi = <0x0>;
  5980. qcom,ramp-step-ms = <0xff>;
  5981. qcom,use-blink;
  5982. };
  5983.  
  5984. qcom,rgb_1 {
  5985. label = "rgb";
  5986. linux,name = "green";
  5987. qcom,mode = "pwm";
  5988. qcom,pwm-channel = <0x5>;
  5989. qcom,pwm-us = <0x3e8>;
  5990. qcom,max-current = <0xc>;
  5991. qcom,default-state = "off";
  5992. qcom,id = <0x4>;
  5993. linux,default-trigger = "none";
  5994. qcom,start-idx = <0x1>;
  5995. qcom,duty-pcts = [00 00 00 00 00 00 00 00 00 00 00 19 32 4b 64 64 32 19 00 00 00 00 00 00 00 00 00 00 00];
  5996. qcom,lut-flags = <0x3>;
  5997. qcom,pause-lo = <0x0>;
  5998. qcom,pause-hi = <0x0>;
  5999. qcom,ramp-step-ms = <0xff>;
  6000. qcom,use-blink;
  6001. };
  6002.  
  6003. qcom,rgb_2 {
  6004. label = "rgb";
  6005. linux,name = "blue";
  6006. qcom,mode = "pwm";
  6007. qcom,pwm-channel = <0x4>;
  6008. qcom,pwm-us = <0x3e8>;
  6009. qcom,max-current = <0xc>;
  6010. qcom,id = <0x5>;
  6011. qcom,start-idx = <0x1>;
  6012. qcom,duty-pcts = [00 00 00 00 00 00 00 00 00 00 00 19 32 4b 64 64 32 19 00 00 00 00 00 00 00 00 00 00 00];
  6013. qcom,lut-flags = <0x3>;
  6014. qcom,pause-lo = <0x0>;
  6015. qcom,pause-hi = <0x0>;
  6016. qcom,ramp-step-ms = <0xff>;
  6017. qcom,use-blink;
  6018. };
  6019. };
  6020.  
  6021. qcom,leds@d100 {
  6022. compatible = "qcom,leds-qpnp";
  6023. reg = <0xd100 0x100>;
  6024. label = "rgb";
  6025. status = "disabled";
  6026. };
  6027.  
  6028. qcom,leds@d200 {
  6029. compatible = "qcom,leds-qpnp";
  6030. reg = <0xd200 0x100>;
  6031. label = "rgb";
  6032. status = "disabled";
  6033. };
  6034.  
  6035. qcom,leds@d300 {
  6036. compatible = "qcom,leds-qpnp";
  6037. reg = <0xd300 0x100>;
  6038. label = "flash";
  6039. flash-boost-supply = <0x55>;
  6040. torch-boost-supply = <0x4d>;
  6041. flash-wa-supply = <0x56>;
  6042. status = "okay";
  6043.  
  6044. qcom,flash_0 {
  6045. qcom,max-current = <0x3e8>;
  6046. qcom,default-state = "off";
  6047. qcom,headroom = <0x3>;
  6048. qcom,duration = <0x500>;
  6049. qcom,clamp-curr = <0xc8>;
  6050. qcom,startup-dly = <0x3>;
  6051. qcom,safety-timer;
  6052. label = "flash";
  6053. linux,default-trigger = "flash0_trigger";
  6054. qcom,id = <0x1>;
  6055. linux,name = "led:flash_0";
  6056. qcom,current = <0x1f4>;
  6057. linux,phandle = <0x78>;
  6058. phandle = <0x78>;
  6059. };
  6060.  
  6061. qcom,flash_1 {
  6062. qcom,max-current = <0x3e8>;
  6063. qcom,default-state = "off";
  6064. qcom,headroom = <0x3>;
  6065. qcom,duration = <0x500>;
  6066. qcom,clamp-curr = <0xc8>;
  6067. qcom,startup-dly = <0x3>;
  6068. qcom,safety-timer;
  6069. linux,default-trigger = "flash1_trigger";
  6070. label = "flash";
  6071. qcom,id = <0x2>;
  6072. linux,name = "led:flash_1";
  6073. qcom,current = <0x1f4>;
  6074. linux,phandle = <0x79>;
  6075. phandle = <0x79>;
  6076. };
  6077.  
  6078. qcom,flash_torch {
  6079. qcom,max-current = <0xc8>;
  6080. qcom,default-state = "off";
  6081. qcom,headroom = <0x0>;
  6082. qcom,startup-dly = <0x1>;
  6083. linux,default-trigger = "torch_trigger";
  6084. label = "flash";
  6085. qcom,id = <0x2>;
  6086. linux,name = "led:flash_torch";
  6087. qcom,current = <0x23>;
  6088. qcom,torch-enable;
  6089. linux,phandle = <0x77>;
  6090. phandle = <0x77>;
  6091. };
  6092. };
  6093.  
  6094. qcom,leds@d400 {
  6095. compatible = "qcom,leds-qpnp";
  6096. reg = <0xd400 0x100>;
  6097. label = "flash";
  6098. status = "disabled";
  6099. };
  6100.  
  6101. qcom,leds@d500 {
  6102. compatible = "qcom,leds-qpnp";
  6103. reg = <0xd500 0x100>;
  6104. label = "flash";
  6105. status = "disabled";
  6106. };
  6107.  
  6108. qcom,leds@d600 {
  6109. compatible = "qcom,leds-qpnp";
  6110. reg = <0xd600 0x100>;
  6111. label = "flash";
  6112. status = "disabled";
  6113. };
  6114.  
  6115. qcom,leds@d700 {
  6116. compatible = "qcom,leds-qpnp";
  6117. reg = <0xd700 0x100>;
  6118. label = "flash";
  6119. status = "disabled";
  6120. };
  6121.  
  6122. qcom,leds@d800 {
  6123. compatible = "qcom,leds-qpnp";
  6124. reg = <0xd800 0x100>;
  6125. label = "wled";
  6126. status = "okay";
  6127.  
  6128. qcom,wled_0 {
  6129. label = "wled";
  6130. linux,name = "wled:backlight";
  6131. linux,default-trigger = "bkl-trigger";
  6132. qcom,cs-out-en;
  6133. qcom,op-fdbck = <0x1>;
  6134. qcom,default-state = "on";
  6135. qcom,max-current = <0x19>;
  6136. qcom,ctrl-delay-us = <0x0>;
  6137. qcom,boost-curr-lim = <0x5>;
  6138. qcom,cp-sel = <0x0>;
  6139. qcom,switch-freq = <0xb>;
  6140. qcom,ovp-val = <0x2>;
  6141. qcom,num-strings = <0x3>;
  6142. qcom,id = <0x0>;
  6143. };
  6144. };
  6145.  
  6146. qcom,leds@d900 {
  6147. compatible = "qcom,leds-qpnp";
  6148. reg = <0xd900 0x100>;
  6149. label = "wled";
  6150. status = "disabled";
  6151. };
  6152.  
  6153. qcom,leds@da00 {
  6154. compatible = "qcom,leds-qpnp";
  6155. reg = <0xda00 0x100>;
  6156. label = "wled";
  6157. status = "disabled";
  6158. };
  6159.  
  6160. qcom,leds@db00 {
  6161. compatible = "qcom,leds-qpnp";
  6162. reg = <0xdb00 0x100>;
  6163. label = "wled";
  6164. status = "disabled";
  6165. };
  6166.  
  6167. qcom,leds@dc00 {
  6168. compatible = "qcom,leds-qpnp";
  6169. reg = <0xdc00 0x100>;
  6170. label = "wled";
  6171. status = "disabled";
  6172. };
  6173.  
  6174. qcom,leds@dd00 {
  6175. compatible = "qcom,leds-qpnp";
  6176. reg = <0xdd00 0x100>;
  6177. label = "wled";
  6178. status = "disabled";
  6179. };
  6180.  
  6181. qcom,leds@de00 {
  6182. compatible = "qcom,leds-qpnp";
  6183. reg = <0xde00 0x100>;
  6184. label = "wled";
  6185. status = "disabled";
  6186. };
  6187.  
  6188. qcom,leds@df00 {
  6189. compatible = "qcom,leds-qpnp";
  6190. reg = <0xdf00 0x100>;
  6191. label = "wled";
  6192. status = "disabled";
  6193. };
  6194.  
  6195. qcom,leds@e000 {
  6196. compatible = "qcom,leds-qpnp";
  6197. reg = <0xe000 0x100>;
  6198. label = "wled";
  6199. status = "disabled";
  6200. };
  6201.  
  6202. qcom,leds@e100 {
  6203. compatible = "qcom,leds-qpnp";
  6204. reg = <0xe100 0x100>;
  6205. label = "wled";
  6206. status = "disabled";
  6207. };
  6208.  
  6209. qcom,leds@e200 {
  6210. compatible = "qcom,leds-qpnp";
  6211. reg = <0xe200 0x100>;
  6212. label = "kpdbl";
  6213. status = "okay";
  6214.  
  6215. qcom,kpdbl1 {
  6216. label = "kpdbl";
  6217. linux,name = "kpdbl-pwm-1";
  6218. qcom,mode = "pwm";
  6219. qcom,pwm-channel = <0x8>;
  6220. qcom,pwm-us = <0x3e8>;
  6221. qcom,id = <0x7>;
  6222. qcom,max-current = <0x14>;
  6223. qcom,row-id = <0x0>;
  6224. qcom,row-src-en;
  6225. qcom,always-on;
  6226. qcom,start-idx = <0x1>;
  6227. qcom,ramp-step-ms = <0x78>;
  6228. qcom,duty-pcts = [00 00 00 00 64 64 00 00 00 00];
  6229. qcom,use-blink;
  6230. qcom,in-order-command-processing;
  6231. };
  6232.  
  6233. qcom,kpdbl2 {
  6234. label = "kpdbl";
  6235. linux,name = "kpdbl-pwm-2";
  6236. qcom,mode = "pwm";
  6237. qcom,pwm-channel = <0x9>;
  6238. qcom,pwm-us = <0x3e8>;
  6239. qcom,id = <0x7>;
  6240. qcom,max-current = <0x14>;
  6241. qcom,row-id = <0x1>;
  6242. qcom,row-src-en;
  6243. qcom,start-idx = <0x1>;
  6244. qcom,ramp-step-ms = <0x78>;
  6245. qcom,duty-pcts = [00 00 00 00 64 64 00 00 00 00];
  6246. qcom,use-blink;
  6247. qcom,in-order-command-processing;
  6248. };
  6249.  
  6250. qcom,kpdbl3 {
  6251. label = "kpdbl";
  6252. linux,name = "kpdbl-pwm-3";
  6253. qcom,mode = "pwm";
  6254. qcom,pwm-channel = <0xa>;
  6255. qcom,pwm-us = <0x3e8>;
  6256. qcom,id = <0x7>;
  6257. qcom,max-current = <0x14>;
  6258. qcom,row-id = <0x2>;
  6259. qcom,row-src-en;
  6260. qcom,start-idx = <0x1>;
  6261. qcom,ramp-step-ms = <0x78>;
  6262. qcom,duty-pcts = [00 00 00 00 64 64 00 00 00 00];
  6263. qcom,use-blink;
  6264. qcom,in-order-command-processing;
  6265. };
  6266.  
  6267. qcom,kpdbl4 {
  6268. label = "kpdbl";
  6269. linux,name = "kpdbl-pwm-4";
  6270. qcom,mode = "pwm";
  6271. qcom,pwm-channel = <0xb>;
  6272. qcom,pwm-us = <0x3e8>;
  6273. qcom,id = <0x7>;
  6274. qcom,max-current = <0x14>;
  6275. qcom,row-id = <0x3>;
  6276. qcom,row-src-en;
  6277. qcom,start-idx = <0x1>;
  6278. qcom,ramp-step-ms = <0x78>;
  6279. qcom,duty-pcts = [00 00 00 00 64 64 00 00 00 00];
  6280. qcom,use-blink;
  6281. qcom,in-order-command-processing;
  6282. };
  6283. };
  6284.  
  6285. pwm@b100 {
  6286. compatible = "qcom,qpnp-pwm";
  6287. reg = <0xb100 0x100 0xb042 0x7e>;
  6288. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6289. qcom,channel-id = <0x0>;
  6290. };
  6291.  
  6292. pwm@b200 {
  6293. compatible = "qcom,qpnp-pwm";
  6294. reg = <0xb200 0x100 0xb042 0x7e>;
  6295. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6296. qcom,channel-id = <0x1>;
  6297. };
  6298.  
  6299. pwm@b300 {
  6300. compatible = "qcom,qpnp-pwm";
  6301. reg = <0xb300 0x100 0xb042 0x7e>;
  6302. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6303. qcom,channel-id = <0x2>;
  6304. };
  6305.  
  6306. pwm@b400 {
  6307. compatible = "qcom,qpnp-pwm";
  6308. reg = <0xb400 0x100 0xb042 0x7e>;
  6309. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6310. qcom,channel-id = <0x3>;
  6311. };
  6312.  
  6313. pwm@b500 {
  6314. compatible = "qcom,qpnp-pwm";
  6315. reg = <0xb500 0x100 0xb042 0x7e>;
  6316. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6317. qcom,channel-id = <0x4>;
  6318. };
  6319.  
  6320. pwm@b600 {
  6321. compatible = "qcom,qpnp-pwm";
  6322. reg = <0xb600 0x100 0xb042 0x7e>;
  6323. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6324. qcom,channel-id = <0x5>;
  6325. };
  6326.  
  6327. pwm@b700 {
  6328. compatible = "qcom,qpnp-pwm";
  6329. reg = <0xb700 0x100 0xb042 0x7e>;
  6330. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6331. qcom,channel-id = <0x6>;
  6332. };
  6333.  
  6334. pwm@b800 {
  6335. compatible = "qcom,qpnp-pwm";
  6336. reg = <0xb800 0x100 0xb042 0x7e>;
  6337. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6338. qcom,channel-id = <0x7>;
  6339. };
  6340.  
  6341. pwm@e400 {
  6342. compatible = "qcom,qpnp-pwm";
  6343. reg = <0xe400 0x100 0xe342 0x1e>;
  6344. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6345. qcom,channel-id = <0x8>;
  6346. };
  6347.  
  6348. pwm@e500 {
  6349. compatible = "qcom,qpnp-pwm";
  6350. reg = <0xe500 0x100 0xe342 0x1e>;
  6351. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6352. qcom,channel-id = <0x9>;
  6353. };
  6354.  
  6355. pwm@e600 {
  6356. compatible = "qcom,qpnp-pwm";
  6357. reg = <0xe600 0x100 0xe342 0x1e>;
  6358. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6359. qcom,channel-id = <0xa>;
  6360. };
  6361.  
  6362. pwm@e700 {
  6363. compatible = "qcom,qpnp-pwm";
  6364. reg = <0xe700 0x100 0xe342 0x1e>;
  6365. reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base";
  6366. qcom,channel-id = <0xb>;
  6367. };
  6368. };
  6369. };
  6370.  
  6371. i2c@f9967000 {
  6372. cell-index = <0x0>;
  6373. compatible = "qcom,i2c-qup";
  6374. reg = <0xf9967000 0x1000>;
  6375. #address-cells = <0x1>;
  6376. #size-cells = <0x0>;
  6377. reg-names = "qup_phys_addr";
  6378. interrupts = <0x0 0x69 0x0>;
  6379. interrupt-names = "qup_err_intr";
  6380. qcom,i2c-bus-freq = <0x186a0>;
  6381. qcom,i2c-src-freq = <0x124f800>;
  6382. qcom,master-id = <0x54>;
  6383.  
  6384. isa1200@48 {
  6385. status = "okay";
  6386. reg = <0x48>;
  6387. vcc_i2c-supply = <0x2d>;
  6388. compatible = "imagis,isa1200";
  6389. label = "vibrator";
  6390. imagis,chip-en;
  6391. imagis,need-pwm-clk;
  6392. imagis,ext-clk-en;
  6393. imagis,hap-en-gpio = <0x5 0x56 0x0>;
  6394. imagis,max-timeout = <0x3a98>;
  6395. imagis,pwm-div = <0x100>;
  6396. imagis,mode-ctrl = <0x2>;
  6397.  
  6398. imagis,regulator {
  6399. regulator-name = "vcc_i2c";
  6400. regulator-min-microvolt = <0x1b7740>;
  6401. regulator-max-microvolt = <0x1b7740>;
  6402. regulator-max-microamp = <0x2490>;
  6403. };
  6404. };
  6405. };
  6406.  
  6407. i2c@f9923000 {
  6408. cell-index = <0x1>;
  6409. compatible = "qcom,i2c-qup";
  6410. reg = <0xf9923000 0x1000>;
  6411. #address-cells = <0x1>;
  6412. #size-cells = <0x0>;
  6413. reg-names = "qup_phys_addr";
  6414. interrupts = <0x0 0x5f 0x0>;
  6415. interrupt-names = "qup_err_intr";
  6416. qcom,i2c-bus-freq = <0x186a0>;
  6417. qcom,i2c-src-freq = <0x124f800>;
  6418. qcom,scl-gpio = <0x5 0x3 0x0>;
  6419. qcom,sda-gpio = <0x5 0x2 0x0>;
  6420. qcom,master-id = <0x56>;
  6421. status = "disabled";
  6422. };
  6423.  
  6424. i2c@f9924000 {
  6425. cell-index = <0x2>;
  6426. compatible = "qcom,i2c-qup";
  6427. reg = <0xf9924000 0x1000>;
  6428. #address-cells = <0x1>;
  6429. #size-cells = <0x0>;
  6430. reg-names = "qup_phys_addr";
  6431. interrupts = <0x0 0x60 0x0>;
  6432. interrupt-names = "qup_err_intr";
  6433. qcom,i2c-bus-freq = <0x5dc00>;
  6434. qcom,i2c-src-freq = <0x124f800>;
  6435. qcom,master-id = <0x56>;
  6436. qcom,scl-gpio = <0x5 0x7 0x0>;
  6437. qcom,sda-gpio = <0x5 0x6 0x0>;
  6438.  
  6439. synaptics_dsx@20 {
  6440. compatible = "synaptics,dsx";
  6441. reg = <0x20>;
  6442. interrupt-parent = <0x5>;
  6443. interrupts = <0x1c 0x2>;
  6444. vcc_i2c-supply = <0x2d>;
  6445. synaptics,bus-reg-name = "vcc_i2c";
  6446. synaptics,irq-gpio = <0x5 0x1c 0x0>;
  6447. synaptics,irq-on-state = <0x0>;
  6448. synaptics,irq-flags = <0x2008>;
  6449. synaptics,power-delay-ms = <0xa0>;
  6450. synaptics,reset-gpio = <0x5 0x37 0x0>;
  6451. synaptics,reset-on-state = <0x0>;
  6452. synaptics,reset-delay-ms = <0x64>;
  6453. synaptics,vir-button-codes = <0x66 0x64 0x708 0x64 0x3c 0x9e 0x12c 0x708 0x64 0x3c>;
  6454. };
  6455.  
  6456. atmel_mxt_ts@4a {
  6457. compatible = "atmel,mxt-ts";
  6458. reg = <0x4a>;
  6459. interrupt-parent = <0x5>;
  6460. interrupts = <0x3d 0x2>;
  6461. vdd_ana-supply = <0x4e>;
  6462. vcc_i2c-supply = <0x57>;
  6463. atmel,reset-gpio = <0x5 0x3c 0x0>;
  6464. atmel,irq-gpio = <0x5 0x3d 0x0>;
  6465. atmel,panel-coords = <0x0 0x0 0x2f8 0x590>;
  6466. atmel,display-coords = <0x0 0x0 0x2d0 0x500>;
  6467. atmel,i2c-pull-up;
  6468. atmel,no-force-update;
  6469.  
  6470. atmel,cfg_1 {
  6471. atmel,fw-name = "atmel_8974_fluid_v1_0_AA.hex";
  6472. atmel,family-id = <0x82>;
  6473. atmel,variant-id = <0x19>;
  6474. atmel,version = <0x10>;
  6475. atmel,build = <0xaa>;
  6476. atmel,config = [00 00 00 00 00 00 15 01 00 03 0a 0c 00 00 20 08 32 03 0f 00 0a 0a 00 00 0a 0a 00 00 83 00 00 18 0e 00 70 46 02 01 00 0a 03 31 04 05 0a 0a 90 05 f8 02 05 f1 f1 0f 00 00 08 2d 12 06 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 33 1e 19 10 80 00 00 00 ff 00 00 00 10 10 00 00 03 00 00 01 08 0a 28 0a 02 0a 00 8c 00 20 00 00 00 00 00 00 00 00 00 00 00 00 18 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 2a 00 16 00 00 00 00 0b 01 02 03 04 08 00 00 08 10 18 05 00 0a 05 05 50 14 19 34 1a 7f 00 00 00 00 00 00 00 00 00 30 05 02 00 01 00 05 00 00 00 00 00 00 00 00];
  6477. };
  6478. };
  6479. };
  6480.  
  6481. spi@f9923000 {
  6482. compatible = "qcom,spi-qup-v2";
  6483. #address-cells = <0x1>;
  6484. #size-cells = <0x0>;
  6485. reg-names = "spi_physical", "spi_bam_physical";
  6486. reg = <0xf9923000 0x1000 0xf9904000 0x19000>;
  6487. interrupt-names = "spi_irq", "spi_bam_irq";
  6488. interrupts = <0x0 0x5f 0x0 0x0 0xee 0x0>;
  6489. spi-max-frequency = <0x124f800>;
  6490. qcom,gpio-mosi = <0x5 0x0 0x0>;
  6491. qcom,gpio-miso = <0x5 0x1 0x0>;
  6492. qcom,gpio-clk = <0x5 0x3 0x0>;
  6493. qcom,gpio-cs0 = <0x5 0x9 0x0>;
  6494. qcom,infinite-mode = <0x0>;
  6495. qcom,use-bam;
  6496. qcom,ver-reg-exists;
  6497. qcom,bam-consumer-pipe-index = <0xc>;
  6498. qcom,bam-producer-pipe-index = <0xd>;
  6499. qcom,master-id = <0x56>;
  6500.  
  6501. ethernet-switch@2 {
  6502. compatible = "micrel,ks8851";
  6503. reg = <0x2>;
  6504. interrupt-parent = <0x5>;
  6505. interrupts = <0x5e 0x0>;
  6506. spi-max-frequency = <0x493e00>;
  6507. rst-gpio = <0x58 0x6 0x0>;
  6508. vdd-io-supply = <0x59>;
  6509. vdd-phy-supply = <0x59>;
  6510. };
  6511. };
  6512.  
  6513. qcom,clock-krait@f9016000 {
  6514. compatible = "qcom,clock-krait-8974";
  6515. reg = <0xf9016000 0x20 0xf908a000 0x20 0xf909a000 0x20 0xf90aa000 0x20 0xf90ba000 0x20 0xfc4b80b0 0x8>;
  6516. reg-names = "hfpll_l2_clk", "hfpll0_clk", "hfpll1_clk", "hfpll2_clk", "hfpll3_clk", "efuse";
  6517. cpu0-supply = <0x5a>;
  6518. cpu1-supply = <0x5b>;
  6519. cpu2-supply = <0x5c>;
  6520. cpu3-supply = <0x5d>;
  6521. l2-dig-supply = <0x5e>;
  6522. hfpll-dig-supply = <0x5e>;
  6523. hfpll-analog-supply = <0x5f>;
  6524. qcom,hfpll-config-val = <0x4d0405d>;
  6525. qcom,hfpll-user-vco-mask = <0x100000>;
  6526. qcom,pvs-config-ver = <0x1>;
  6527. qcom,l2-fmax = <0x0 0x0 0x22551000 0x4 0x3dcc5000 0x5 0x66ff3000 0x7>;
  6528. qcom,speed0-pvs0-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xc6f98 0x49 0x14997000 0xc96a8 0x55 0x192d5000 0xcbdb8 0x68 0x1dc13000 0xce4c8 0x7c 0x22551000 0xd0bd8 0x90 0x26e8f000 0xd32e8 0xa5 0x2b7cd000 0xd59f8 0xba 0x3010b000 0xd9490 0xd0 0x34a49000 0xdbba0 0xe5 0x39387000 0xdf638 0xfc 0x3dcc5000 0xe1d48 0x113 0x42603000 0xe57e0 0x12a 0x46f41000 0xe7ef0 0x141 0x4b87f000 0xeb988 0x15a 0x501bd000 0xef420 0x173 0x54afb000 0xf2eb8 0x18d 0x59439000 0xf6950 0x1a7 0x5dd77000 0xfa3e8 0x1c2 0x626b5000 0xfde80 0x1dd 0x66ff3000 0x101918 0x1fa 0x6b931000 0x1053b0 0x218 0x7026f000 0x108e48 0x237 0x74bad000 0x10c8e0 0x256>;
  6529. qcom,speed0-pvs1-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x49 0x14997000 0xc5c10 0x55 0x192d5000 0xc8320 0x68 0x1dc13000 0xcaa30 0x7c 0x22551000 0xcd140 0x90 0x26e8f000 0xcf850 0xa5 0x2b7cd000 0xd1f60 0xba 0x3010b000 0xd59f8 0xd0 0x34a49000 0xd8108 0xe5 0x39387000 0xda818 0xfc 0x3dcc5000 0xde2b0 0x113 0x42603000 0xe09c0 0x12a 0x46f41000 0xe30d0 0x141 0x4b87f000 0xe6b68 0x15a 0x501bd000 0xea600 0x173 0x54afb000 0xee098 0x18d 0x59439000 0xf1b30 0x1a7 0x5dd77000 0xf55c8 0x1c2 0x626b5000 0xf9060 0x1dd 0x66ff3000 0xfb770 0x1fa 0x6b931000 0xff208 0x218 0x7026f000 0x102ca0 0x237 0x74bad000 0x106738 0x256>;
  6530. qcom,speed0-pvs2-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbfa68 0x49 0x14997000 0xc2178 0x55 0x192d5000 0xc4888 0x68 0x1dc13000 0xc6f98 0x7c 0x22551000 0xc96a8 0x90 0x26e8f000 0xcbdb8 0xa5 0x2b7cd000 0xce4c8 0xba 0x3010b000 0xd0bd8 0xd0 0x34a49000 0xd32e8 0xe5 0x39387000 0xd59f8 0xfc 0x3dcc5000 0xd9490 0x113 0x42603000 0xdbba0 0x12a 0x46f41000 0xde2b0 0x141 0x4b87f000 0xe1d48 0x15a 0x501bd000 0xe57e0 0x173 0x54afb000 0xe9278 0x18d 0x59439000 0xecd10 0x1a7 0x5dd77000 0xef420 0x1c2 0x626b5000 0xf2eb8 0x1dd 0x66ff3000 0xf55c8 0x1fa 0x6b931000 0xf9060 0x218 0x7026f000 0xfcaf8 0x237 0x74bad000 0x100590 0x256>;
  6531. qcom,speed0-pvs3-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x49 0x14997000 0xbe6e0 0x55 0x192d5000 0xc0df0 0x68 0x1dc13000 0xc3500 0x7c 0x22551000 0xc5c10 0x90 0x26e8f000 0xc8320 0xa5 0x2b7cd000 0xcaa30 0xba 0x3010b000 0xcd140 0xd0 0x34a49000 0xcf850 0xe5 0x39387000 0xd1f60 0xfc 0x3dcc5000 0xd59f8 0x113 0x42603000 0xd8108 0x12a 0x46f41000 0xda818 0x141 0x4b87f000 0xde2b0 0x15a 0x501bd000 0xe1d48 0x173 0x54afb000 0xe4458 0x18d 0x59439000 0xe7ef0 0x1a7 0x5dd77000 0xea600 0x1c2 0x626b5000 0xecd10 0x1dd 0x66ff3000 0xf07a8 0x1fa 0x6b931000 0xf2eb8 0x218 0x7026f000 0xf6950 0x237 0x74bad000 0xfa3e8 0x256>;
  6532. qcom,speed0-pvs4-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x49 0x14997000 0xbd358 0x55 0x192d5000 0xbe6e0 0x68 0x1dc13000 0xc0df0 0x7c 0x22551000 0xc3500 0x90 0x26e8f000 0xc5c10 0xa5 0x2b7cd000 0xc8320 0xba 0x3010b000 0xcaa30 0xd0 0x34a49000 0xcd140 0xe5 0x39387000 0xcf850 0xfc 0x3dcc5000 0xd1f60 0x113 0x42603000 0xd4670 0x12a 0x46f41000 0xd6d80 0x141 0x4b87f000 0xda818 0x15a 0x501bd000 0xde2b0 0x173 0x54afb000 0xe09c0 0x18d 0x59439000 0xe30d0 0x1a7 0x5dd77000 0xe57e0 0x1c2 0x626b5000 0xe7ef0 0x1dd 0x66ff3000 0xea600 0x1fa 0x6b931000 0xee098 0x218 0x7026f000 0xf07a8 0x237 0x74bad000 0xf4240 0x256>;
  6533. qcom,speed0-pvs5-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x49 0x14997000 0xb98c0 0x55 0x192d5000 0xbbfd0 0x68 0x1dc13000 0xbe6e0 0x7c 0x22551000 0xc0df0 0x90 0x26e8f000 0xc3500 0xa5 0x2b7cd000 0xc5c10 0xba 0x3010b000 0xc8320 0xd0 0x34a49000 0xcaa30 0xe5 0x39387000 0xcd140 0xfc 0x3dcc5000 0xcf850 0x113 0x42603000 0xd1f60 0x12a 0x46f41000 0xd4670 0x141 0x4b87f000 0xd6d80 0x15a 0x501bd000 0xd9490 0x173 0x54afb000 0xdbba0 0x18d 0x59439000 0xde2b0 0x1a7 0x5dd77000 0xe09c0 0x1c2 0x626b5000 0xe30d0 0x1dd 0x66ff3000 0xe57e0 0x1fa 0x6b931000 0xe9278 0x218 0x7026f000 0xeb988 0x237 0x74bad000 0xee098 0x256>;
  6534. qcom,speed0-pvs6-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x49 0x14997000 0xb71b0 0x55 0x192d5000 0xb98c0 0x68 0x1dc13000 0xbbfd0 0x7c 0x22551000 0xbe6e0 0x90 0x26e8f000 0xc0df0 0xa5 0x2b7cd000 0xc3500 0xba 0x3010b000 0xc5c10 0xd0 0x34a49000 0xc8320 0xe5 0x39387000 0xcaa30 0xfc 0x3dcc5000 0xcd140 0x113 0x42603000 0xcf850 0x12a 0x46f41000 0xd1f60 0x141 0x4b87f000 0xd4670 0x15a 0x501bd000 0xd59f8 0x173 0x54afb000 0xd8108 0x18d 0x59439000 0xda818 0x1a7 0x5dd77000 0xdcf28 0x1c2 0x626b5000 0xdf638 0x1dd 0x66ff3000 0xe09c0 0x1fa 0x6b931000 0xe30d0 0x218 0x7026f000 0xe57e0 0x237 0x74bad000 0xe7ef0 0x256>;
  6535. qcom,speed2-pvs0-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x48 0x14997000 0xc3500 0x53 0x192d5000 0xc4888 0x66 0x1dc13000 0xc6f98 0x79 0x22551000 0xc96a8 0x8d 0x26e8f000 0xcbdb8 0xa1 0x2b7cd000 0xce4c8 0xb5 0x3010b000 0xd0bd8 0xca 0x34a49000 0xd32e8 0xdf 0x39387000 0xd59f8 0xf5 0x3dcc5000 0xd9490 0x10b 0x42603000 0xdbba0 0x121 0x46f41000 0xdf638 0x139 0x4b87f000 0xe1d48 0x150 0x501bd000 0xe57e0 0x168 0x54afb000 0xe7ef0 0x17f 0x59439000 0xeb988 0x199 0x5dd77000 0xef420 0x1b3 0x626b5000 0xf2eb8 0x1cd 0x66ff3000 0xf6950 0x1e8 0x6b931000 0xfa3e8 0x204 0x7026f000 0xfde80 0x21f 0x74bad000 0x101918 0x23d 0x794eb000 0x1053b0 0x25c 0x7de29000 0x108e48 0x27c 0x802c8000 0x10c8e0 0x290>;
  6536. qcom,speed2-pvs1-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x48 0x14997000 0xc3500 0x53 0x192d5000 0xc3500 0x66 0x1dc13000 0xc3500 0x79 0x22551000 0xc5c10 0x8d 0x26e8f000 0xc8320 0xa1 0x2b7cd000 0xcaa30 0xb5 0x3010b000 0xcd140 0xca 0x34a49000 0xcf850 0xdf 0x39387000 0xd1f60 0xf5 0x3dcc5000 0xd59f8 0x10b 0x42603000 0xd8108 0x121 0x46f41000 0xda818 0x139 0x4b87f000 0xde2b0 0x150 0x501bd000 0xe09c0 0x168 0x54afb000 0xe30d0 0x17f 0x59439000 0xe6b68 0x199 0x5dd77000 0xea600 0x1b3 0x626b5000 0xee098 0x1cd 0x66ff3000 0xf1b30 0x1e8 0x6b931000 0xf55c8 0x204 0x7026f000 0xf9060 0x21f 0x74bad000 0xfb770 0x23d 0x794eb000 0xff208 0x25c 0x7de29000 0x102ca0 0x27c 0x802c8000 0x106738 0x290>;
  6537. qcom,speed2-pvs2-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x48 0x14997000 0xbd358 0x53 0x192d5000 0xbd358 0x66 0x1dc13000 0xbfa68 0x79 0x22551000 0xc2178 0x8d 0x26e8f000 0xc4888 0xa1 0x2b7cd000 0xc6f98 0xb5 0x3010b000 0xc96a8 0xca 0x34a49000 0xcbdb8 0xdf 0x39387000 0xce4c8 0xf5 0x3dcc5000 0xd0bd8 0x10b 0x42603000 0xd32e8 0x121 0x46f41000 0xd59f8 0x139 0x4b87f000 0xd9490 0x150 0x501bd000 0xdbba0 0x168 0x54afb000 0xde2b0 0x17f 0x59439000 0xe1d48 0x199 0x5dd77000 0xe57e0 0x1b3 0x626b5000 0xe9278 0x1cd 0x66ff3000 0xecd10 0x1e8 0x6b931000 0xef420 0x204 0x7026f000 0xf2eb8 0x21f 0x74bad000 0xf55c8 0x23d 0x794eb000 0xf9060 0x25c 0x7de29000 0xfcaf8 0x27c 0x802c8000 0x100590 0x290>;
  6538. qcom,speed2-pvs3-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x48 0x14997000 0xbd358 0x53 0x192d5000 0xbd358 0x66 0x1dc13000 0xbd358 0x79 0x22551000 0xbe6e0 0x8d 0x26e8f000 0xc0df0 0xa1 0x2b7cd000 0xc3500 0xb5 0x3010b000 0xc5c10 0xca 0x34a49000 0xc8320 0xdf 0x39387000 0xcaa30 0xf5 0x3dcc5000 0xcd140 0x10b 0x42603000 0xcf850 0x121 0x46f41000 0xd1f60 0x139 0x4b87f000 0xd59f8 0x150 0x501bd000 0xd8108 0x168 0x54afb000 0xda818 0x17f 0x59439000 0xde2b0 0x199 0x5dd77000 0xe1d48 0x1b3 0x626b5000 0xe4458 0x1cd 0x66ff3000 0xe7ef0 0x1e8 0x6b931000 0xea600 0x204 0x7026f000 0xecd10 0x21f 0x74bad000 0xf07a8 0x23d 0x794eb000 0xf2eb8 0x25c 0x7de29000 0xf6950 0x27c 0x802c8000 0xfa3e8 0x290>;
  6539. qcom,speed2-pvs4-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x48 0x14997000 0xbd358 0x53 0x192d5000 0xbd358 0x66 0x1dc13000 0xbd358 0x79 0x22551000 0xbd358 0x8d 0x26e8f000 0xbe6e0 0xa1 0x2b7cd000 0xc0df0 0xb5 0x3010b000 0xc3500 0xca 0x34a49000 0xc5c10 0xdf 0x39387000 0xc8320 0xf5 0x3dcc5000 0xcaa30 0x10b 0x42603000 0xcd140 0x121 0x46f41000 0xcf850 0x139 0x4b87f000 0xd1f60 0x150 0x501bd000 0xd4670 0x168 0x54afb000 0xd6d80 0x17f 0x59439000 0xda818 0x199 0x5dd77000 0xde2b0 0x1b3 0x626b5000 0xe09c0 0x1cd 0x66ff3000 0xe30d0 0x1e8 0x6b931000 0xe57e0 0x204 0x7026f000 0xe7ef0 0x21f 0x74bad000 0xea600 0x23d 0x794eb000 0xee098 0x25c 0x7de29000 0xf07a8 0x27c 0x802c8000 0xf4240 0x290>;
  6540. qcom,speed2-pvs5-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x48 0x14997000 0xb71b0 0x53 0x192d5000 0xb71b0 0x66 0x1dc13000 0xb71b0 0x79 0x22551000 0xb98c0 0x8d 0x26e8f000 0xbbfd0 0xa1 0x2b7cd000 0xbe6e0 0xb5 0x3010b000 0xc0df0 0xca 0x34a49000 0xc3500 0xdf 0x39387000 0xc5c10 0xf5 0x3dcc5000 0xc8320 0x10b 0x42603000 0xcaa30 0x121 0x46f41000 0xcd140 0x139 0x4b87f000 0xcf850 0x150 0x501bd000 0xd1f60 0x168 0x54afb000 0xd4670 0x17f 0x59439000 0xd6d80 0x199 0x5dd77000 0xd9490 0x1b3 0x626b5000 0xdbba0 0x1cd 0x66ff3000 0xde2b0 0x1e8 0x6b931000 0xe09c0 0x204 0x7026f000 0xe30d0 0x21f 0x74bad000 0xe57e0 0x23d 0x794eb000 0xe9278 0x25c 0x7de29000 0xeb988 0x27c 0x802c8000 0xee098 0x290>;
  6541. qcom,speed2-pvs6-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x48 0x14997000 0xb71b0 0x53 0x192d5000 0xb71b0 0x66 0x1dc13000 0xb71b0 0x79 0x22551000 0xb71b0 0x8d 0x26e8f000 0xb98c0 0xa1 0x2b7cd000 0xbbfd0 0xb5 0x3010b000 0xbe6e0 0xca 0x34a49000 0xc0df0 0xdf 0x39387000 0xc3500 0xf5 0x3dcc5000 0xc5c10 0x10b 0x42603000 0xc8320 0x121 0x46f41000 0xcaa30 0x139 0x4b87f000 0xcd140 0x150 0x501bd000 0xcf850 0x168 0x54afb000 0xd1f60 0x17f 0x59439000 0xd4670 0x199 0x5dd77000 0xd59f8 0x1b3 0x626b5000 0xd8108 0x1cd 0x66ff3000 0xda818 0x1e8 0x6b931000 0xdcf28 0x204 0x7026f000 0xdf638 0x21f 0x74bad000 0xe09c0 0x23d 0x794eb000 0xe30d0 0x25c 0x7de29000 0xe57e0 0x27c 0x802c8000 0xe7ef0 0x290>;
  6542. qcom,speed1-pvs0-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4a 0x14997000 0xbd358 0x55 0x192d5000 0xbd358 0x68 0x1dc13000 0xbe6e0 0x7c 0x22551000 0xc0df0 0x90 0x26e8f000 0xc3500 0xa4 0x2b7cd000 0xc5c10 0xb8 0x3010b000 0xc8320 0xce 0x34a49000 0xcaa30 0xe3 0x39387000 0xcd140 0xf9 0x3dcc5000 0xcf850 0x10f 0x42603000 0xd32e8 0x127 0x46f41000 0xd59f8 0x13e 0x4b87f000 0xd9490 0x156 0x501bd000 0xdbba0 0x16d 0x54afb000 0xdf638 0x188 0x59439000 0xe1d48 0x1a0 0x5dd77000 0xe57e0 0x1ba 0x626b5000 0xe9278 0x1d5 0x66ff3000 0xecd10 0x1f1 0x6b931000 0xf07a8 0x20d 0x7026f000 0xf4240 0x22a 0x74bad000 0xf7cd8 0x247 0x794eb000 0xfb770 0x265 0x7de29000 0xff208 0x282 0x802c8000 0x102ca0 0x297 0x82767000 0x102ca0 0x2a3 0x870a5000 0x106738 0x2c4>;
  6543. qcom,speed1-pvs1-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4a 0x14997000 0xbd358 0x55 0x192d5000 0xbd358 0x68 0x1dc13000 0xbd358 0x7c 0x22551000 0xbd358 0x90 0x26e8f000 0xbfa68 0xa4 0x2b7cd000 0xc2178 0xb8 0x3010b000 0xc4888 0xce 0x34a49000 0xc6f98 0xe3 0x39387000 0xc96a8 0xf9 0x3dcc5000 0xcbdb8 0x10f 0x42603000 0xcf850 0x127 0x46f41000 0xd1f60 0x13e 0x4b87f000 0xd4670 0x156 0x501bd000 0xd8108 0x16d 0x54afb000 0xda818 0x188 0x59439000 0xdcf28 0x1a0 0x5dd77000 0xe09c0 0x1ba 0x626b5000 0xe4458 0x1d5 0x66ff3000 0xe7ef0 0x1f1 0x6b931000 0xeb988 0x20d 0x7026f000 0xef420 0x22a 0x74bad000 0xf2eb8 0x247 0x794eb000 0xf55c8 0x265 0x7de29000 0xf9060 0x282 0x802c8000 0xfcaf8 0x297 0x82767000 0xfcaf8 0x2a3 0x870a5000 0x100590 0x2c4>;
  6544. qcom,speed1-pvs2-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x4a 0x14997000 0xb71b0 0x55 0x192d5000 0xb71b0 0x68 0x1dc13000 0xb71b0 0x7c 0x22551000 0xb98c0 0x90 0x26e8f000 0xbbfd0 0xa4 0x2b7cd000 0xbe6e0 0xb8 0x3010b000 0xc0df0 0xce 0x34a49000 0xc3500 0xe3 0x39387000 0xc5c10 0xf9 0x3dcc5000 0xc8320 0x10f 0x42603000 0xcaa30 0x127 0x46f41000 0xcd140 0x13e 0x4b87f000 0xcf850 0x156 0x501bd000 0xd32e8 0x16d 0x54afb000 0xd59f8 0x188 0x59439000 0xd8108 0x1a0 0x5dd77000 0xdbba0 0x1ba 0x626b5000 0xdf638 0x1d5 0x66ff3000 0xe30d0 0x1f1 0x6b931000 0xe6b68 0x20d 0x7026f000 0xe9278 0x22a 0x74bad000 0xecd10 0x247 0x794eb000 0xef420 0x265 0x7de29000 0xf2eb8 0x282 0x802c8000 0xf6950 0x297 0x82767000 0xf6950 0x2a3 0x870a5000 0xfa3e8 0x2c4>;
  6545. qcom,speed1-pvs3-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x4a 0x14997000 0xb71b0 0x55 0x192d5000 0xb71b0 0x68 0x1dc13000 0xb71b0 0x7c 0x22551000 0xb71b0 0x90 0x26e8f000 0xb8538 0xa4 0x2b7cd000 0xbac48 0xb8 0x3010b000 0xbd358 0xce 0x34a49000 0xbfa68 0xe3 0x39387000 0xc2178 0xf9 0x3dcc5000 0xc4888 0x10f 0x42603000 0xc6f98 0x127 0x46f41000 0xc96a8 0x13e 0x4b87f000 0xcbdb8 0x156 0x501bd000 0xcf850 0x16d 0x54afb000 0xd1f60 0x188 0x59439000 0xd4670 0x1a0 0x5dd77000 0xd8108 0x1ba 0x626b5000 0xdbba0 0x1d5 0x66ff3000 0xde2b0 0x1f1 0x6b931000 0xe1d48 0x20d 0x7026f000 0xe4458 0x22a 0x74bad000 0xe6b68 0x247 0x794eb000 0xea600 0x265 0x7de29000 0xecd10 0x282 0x802c8000 0xf07a8 0x297 0x82767000 0xf07a8 0x2a3 0x870a5000 0xf4240 0x2c4>;
  6546. qcom,speed1-pvs4-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x4a 0x14997000 0xb71b0 0x55 0x192d5000 0xb71b0 0x68 0x1dc13000 0xb71b0 0x7c 0x22551000 0xb71b0 0x90 0x26e8f000 0xb71b0 0xa4 0x2b7cd000 0xb8538 0xb8 0x3010b000 0xbac48 0xce 0x34a49000 0xbd358 0xe3 0x39387000 0xbfa68 0xf9 0x3dcc5000 0xc2178 0x10f 0x42603000 0xc4888 0x127 0x46f41000 0xc6f98 0x13e 0x4b87f000 0xc96a8 0x156 0x501bd000 0xcbdb8 0x16d 0x54afb000 0xce4c8 0x188 0x59439000 0xd0bd8 0x1a0 0x5dd77000 0xd4670 0x1ba 0x626b5000 0xd8108 0x1d5 0x66ff3000 0xda818 0x1f1 0x6b931000 0xdcf28 0x20d 0x7026f000 0xdf638 0x22a 0x74bad000 0xe1d48 0x247 0x794eb000 0xe4458 0x265 0x7de29000 0xe7ef0 0x282 0x802c8000 0xea600 0x297 0x82767000 0xea600 0x2a3 0x870a5000 0xee098 0x2c4>;
  6547. qcom,speed1-pvs5-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb1008 0x4a 0x14997000 0xb1008 0x55 0x192d5000 0xb1008 0x68 0x1dc13000 0xb1008 0x7c 0x22551000 0xb1008 0x90 0x26e8f000 0xb3718 0xa4 0x2b7cd000 0xb5e28 0xb8 0x3010b000 0xb8538 0xce 0x34a49000 0xbac48 0xe3 0x39387000 0xbd358 0xf9 0x3dcc5000 0xbfa68 0x10f 0x42603000 0xc2178 0x127 0x46f41000 0xc4888 0x13e 0x4b87f000 0xc6f98 0x156 0x501bd000 0xc96a8 0x16d 0x54afb000 0xcbdb8 0x188 0x59439000 0xce4c8 0x1a0 0x5dd77000 0xd0bd8 0x1ba 0x626b5000 0xd32e8 0x1d5 0x66ff3000 0xd59f8 0x1f1 0x6b931000 0xd8108 0x20d 0x7026f000 0xda818 0x22a 0x74bad000 0xdcf28 0x247 0x794eb000 0xdf638 0x265 0x7de29000 0xe30d0 0x282 0x802c8000 0xe57e0 0x297 0x82767000 0xe57e0 0x2a3 0x870a5000 0xe7ef0 0x2c4>;
  6548. qcom,speed1-pvs6-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb1008 0x4a 0x14997000 0xb1008 0x55 0x192d5000 0xb1008 0x68 0x1dc13000 0xb1008 0x7c 0x22551000 0xb1008 0x90 0x26e8f000 0xb1008 0xa4 0x2b7cd000 0xb3718 0xb8 0x3010b000 0xb5e28 0xce 0x34a49000 0xb8538 0xe3 0x39387000 0xbac48 0xf9 0x3dcc5000 0xbd358 0x10f 0x42603000 0xbfa68 0x127 0x46f41000 0xc2178 0x13e 0x4b87f000 0xc4888 0x156 0x501bd000 0xc6f98 0x16d 0x54afb000 0xc96a8 0x188 0x59439000 0xcbdb8 0x1a0 0x5dd77000 0xce4c8 0x1ba 0x626b5000 0xcf850 0x1d5 0x66ff3000 0xd1f60 0x1f1 0x6b931000 0xd4670 0x20d 0x7026f000 0xd6d80 0x22a 0x74bad000 0xd9490 0x247 0x794eb000 0xda818 0x265 0x7de29000 0xdcf28 0x282 0x802c8000 0xdf638 0x297 0x82767000 0xdf638 0x2a3 0x870a5000 0xe1d48 0x2c4>;
  6549. qcom,speed3-pvs0-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc3500 0x7d 0x22551000 0xc3500 0x91 0x26e8f000 0xc5c10 0xa5 0x2b7cd000 0xc8320 0xba 0x3010b000 0xcaa30 0xd0 0x34a49000 0xcd140 0xe5 0x39387000 0xcf850 0xfb 0x3dcc5000 0xd1f60 0x111 0x42603000 0xd4670 0x128 0x46f41000 0xd6d80 0x13f 0x4b87f000 0xd9490 0x156 0x501bd000 0xdbba0 0x16d 0x54afb000 0xde2b0 0x186 0x59439000 0xe09c0 0x19f 0x5dd77000 0xe30d0 0x1b7 0x626b5000 0xe6b68 0x1d1 0x66ff3000 0xea600 0x1ed 0x6b931000 0xee098 0x209 0x7026f000 0xf1b30 0x225 0x74bad000 0xf55c8 0x243 0x794eb000 0xf9060 0x260 0x7de29000 0xfcaf8 0x27e 0x802c8000 0x100590 0x29b 0x82767000 0x100590 0x29b 0x870a5000 0x104028 0x2bc 0x8b9e3000 0x107ac0 0x2de 0x90321000 0x10b558 0x301 0x927c0000 0x10c8e0 0x311>;
  6550. qcom,speed3-pvs1-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc3500 0x7d 0x22551000 0xc3500 0x91 0x26e8f000 0xc3500 0xa5 0x2b7cd000 0xc3500 0xba 0x3010b000 0xc4888 0xd0 0x34a49000 0xc6f98 0xe5 0x39387000 0xc96a8 0xfb 0x3dcc5000 0xcbdb8 0x111 0x42603000 0xce4c8 0x128 0x46f41000 0xd0bd8 0x13f 0x4b87f000 0xd32e8 0x156 0x501bd000 0xd59f8 0x16d 0x54afb000 0xd8108 0x186 0x59439000 0xda818 0x19f 0x5dd77000 0xdcf28 0x1b7 0x626b5000 0xe09c0 0x1d1 0x66ff3000 0xe4458 0x1ed 0x6b931000 0xe7ef0 0x209 0x7026f000 0xeb988 0x225 0x74bad000 0xef420 0x243 0x794eb000 0xf2eb8 0x260 0x7de29000 0xf6950 0x27e 0x802c8000 0xfa3e8 0x29b 0x82767000 0xfa3e8 0x29b 0x870a5000 0xfde80 0x2bc 0x8b9e3000 0x101918 0x2de 0x90321000 0x1053b0 0x301 0x927c0000 0x106738 0x311>;
  6551. qcom,speed3-pvs2-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7d 0x22551000 0xbd358 0x91 0x26e8f000 0xbd358 0xa5 0x2b7cd000 0xbd358 0xba 0x3010b000 0xbe6e0 0xd0 0x34a49000 0xc0df0 0xe5 0x39387000 0xc3500 0xfb 0x3dcc5000 0xc5c10 0x111 0x42603000 0xc8320 0x128 0x46f41000 0xcaa30 0x13f 0x4b87f000 0xcd140 0x156 0x501bd000 0xcf850 0x16d 0x54afb000 0xd1f60 0x186 0x59439000 0xd4670 0x19f 0x5dd77000 0xd6d80 0x1b7 0x626b5000 0xda818 0x1d1 0x66ff3000 0xde2b0 0x1ed 0x6b931000 0xe1d48 0x209 0x7026f000 0xe57e0 0x225 0x74bad000 0xe9278 0x243 0x794eb000 0xecd10 0x260 0x7de29000 0xf07a8 0x27e 0x802c8000 0xf4240 0x29b 0x82767000 0xf4240 0x29b 0x870a5000 0xf7cd8 0x2bc 0x8b9e3000 0xfb770 0x2de 0x90321000 0xff208 0x301 0x927c0000 0x100590 0x311>;
  6552. qcom,speed3-pvs3-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7d 0x22551000 0xbd358 0x91 0x26e8f000 0xbd358 0xa5 0x2b7cd000 0xbd358 0xba 0x3010b000 0xbd358 0xd0 0x34a49000 0xbd358 0xe5 0x39387000 0xbe6e0 0xfb 0x3dcc5000 0xbfa68 0x111 0x42603000 0xc2178 0x128 0x46f41000 0xc4888 0x13f 0x4b87f000 0xc6f98 0x156 0x501bd000 0xc96a8 0x16d 0x54afb000 0xcbdb8 0x186 0x59439000 0xce4c8 0x19f 0x5dd77000 0xd0bd8 0x1b7 0x626b5000 0xd4670 0x1d1 0x66ff3000 0xd8108 0x1ed 0x6b931000 0xdbba0 0x209 0x7026f000 0xdf638 0x225 0x74bad000 0xe30d0 0x243 0x794eb000 0xe6b68 0x260 0x7de29000 0xea600 0x27e 0x802c8000 0xee098 0x29b 0x82767000 0xee098 0x29b 0x870a5000 0xf1b30 0x2bc 0x8b9e3000 0xf55c8 0x2de 0x90321000 0xf9060 0x301 0x927c0000 0xfa3e8 0x311>;
  6553. qcom,speed3-pvs4-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7d 0x22551000 0xbd358 0x91 0x26e8f000 0xbd358 0xa5 0x2b7cd000 0xbd358 0xba 0x3010b000 0xbd358 0xd0 0x34a49000 0xbd358 0xe5 0x39387000 0xbd358 0xfb 0x3dcc5000 0xbd358 0x111 0x42603000 0xbd358 0x128 0x46f41000 0xbe6e0 0x13f 0x4b87f000 0xc0df0 0x156 0x501bd000 0xc3500 0x16d 0x54afb000 0xc5c10 0x186 0x59439000 0xc8320 0x19f 0x5dd77000 0xcaa30 0x1b7 0x626b5000 0xce4c8 0x1d1 0x66ff3000 0xd1f60 0x1ed 0x6b931000 0xd59f8 0x209 0x7026f000 0xd9490 0x225 0x74bad000 0xdcf28 0x243 0x794eb000 0xe09c0 0x260 0x7de29000 0xe4458 0x27e 0x802c8000 0xe7ef0 0x29b 0x82767000 0xe7ef0 0x29b 0x870a5000 0xeb988 0x2bc 0x8b9e3000 0xef420 0x2de 0x90321000 0xf2eb8 0x301 0x927c0000 0xf4240 0x311>;
  6554. qcom,speed3-pvs5-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x4c 0x14997000 0xb71b0 0x57 0x192d5000 0xb71b0 0x6a 0x1dc13000 0xb71b0 0x7d 0x22551000 0xb71b0 0x91 0x26e8f000 0xb71b0 0xa5 0x2b7cd000 0xb71b0 0xba 0x3010b000 0xb71b0 0xd0 0x34a49000 0xb71b0 0xe5 0x39387000 0xb71b0 0xfb 0x3dcc5000 0xb71b0 0x111 0x42603000 0xb71b0 0x128 0x46f41000 0xb98c0 0x13f 0x4b87f000 0xbbfd0 0x156 0x501bd000 0xbe6e0 0x16d 0x54afb000 0xc0df0 0x186 0x59439000 0xc3500 0x19f 0x5dd77000 0xc5c10 0x1b7 0x626b5000 0xc8320 0x1d1 0x66ff3000 0xcbdb8 0x1ed 0x6b931000 0xcf850 0x209 0x7026f000 0xd32e8 0x225 0x74bad000 0xd6d80 0x243 0x794eb000 0xda818 0x260 0x7de29000 0xde2b0 0x27e 0x802c8000 0xe1d48 0x29b 0x82767000 0xe1d48 0x29b 0x870a5000 0xe57e0 0x2bc 0x8b9e3000 0xe9278 0x2de 0x90321000 0xecd10 0x301 0x927c0000 0xee098 0x311>;
  6555. qcom,speed3-pvs6-bin-v0 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x4c 0x14997000 0xb71b0 0x57 0x192d5000 0xb71b0 0x6a 0x1dc13000 0xb71b0 0x7d 0x22551000 0xb71b0 0x91 0x26e8f000 0xb71b0 0xa5 0x2b7cd000 0xb71b0 0xba 0x3010b000 0xb71b0 0xd0 0x34a49000 0xb71b0 0xe5 0x39387000 0xb71b0 0xfb 0x3dcc5000 0xb71b0 0x111 0x42603000 0xb71b0 0x128 0x46f41000 0xb71b0 0x13f 0x4b87f000 0xb8538 0x156 0x501bd000 0xbac48 0x16d 0x54afb000 0xbd358 0x186 0x59439000 0xbfa68 0x19f 0x5dd77000 0xc2178 0x1b7 0x626b5000 0xc4888 0x1d1 0x66ff3000 0xc6f98 0x1ed 0x6b931000 0xc96a8 0x209 0x7026f000 0xcd140 0x225 0x74bad000 0xd0bd8 0x243 0x794eb000 0xd4670 0x260 0x7de29000 0xd8108 0x27e 0x802c8000 0xdbba0 0x29b 0x82767000 0xdbba0 0x29b 0x870a5000 0xdf638 0x2bc 0x8b9e3000 0xe30d0 0x2de 0x90321000 0xe6b68 0x301 0x927c0000 0xe7ef0 0x311>;
  6556. qcom,speed1-pvs0-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc5c10 0x57 0x192d5000 0xc8320 0x6c 0x1dc13000 0xcaa30 0x81 0x22551000 0xcd140 0x96 0x26e8f000 0xcf850 0xab 0x2b7cd000 0xd1f60 0xc1 0x3010b000 0xd4670 0xd7 0x34a49000 0xd6d80 0xed 0x39387000 0xd9490 0x104 0x3dcc5000 0xdbba0 0x11a 0x42603000 0xde2b0 0x132 0x46f41000 0xe09c0 0x14a 0x4b87f000 0xe30d0 0x162 0x501bd000 0xe57e0 0x17a 0x54afb000 0xe9278 0x194 0x59439000 0xecd10 0x1af 0x5dd77000 0xf07a8 0x1ca 0x626b5000 0xf4240 0x1e6 0x66ff3000 0xf7cd8 0x203 0x6b931000 0xfb770 0x21f 0x7026f000 0xff208 0x23c 0x74bad000 0x102ca0 0x25c 0x794eb000 0x106738 0x27c 0x7de29000 0x10a1d0 0x29d 0x802c8000 0x10dc68 0x2bf 0x82767000 0x10dc68 0x2bf 0x870a5000 0x111700 0x2e2>;
  6557. qcom,speed1-pvs1-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc5c10 0x6c 0x1dc13000 0xc8320 0x81 0x22551000 0xcaa30 0x96 0x26e8f000 0xcd140 0xab 0x2b7cd000 0xcf850 0xc1 0x3010b000 0xd1f60 0xd7 0x34a49000 0xd4670 0xed 0x39387000 0xd6d80 0x104 0x3dcc5000 0xd9490 0x11a 0x42603000 0xdbba0 0x132 0x46f41000 0xde2b0 0x14a 0x4b87f000 0xe09c0 0x162 0x501bd000 0xe30d0 0x17a 0x54afb000 0xe6b68 0x194 0x59439000 0xea600 0x1af 0x5dd77000 0xee098 0x1ca 0x626b5000 0xf1b30 0x1e6 0x66ff3000 0xf55c8 0x203 0x6b931000 0xf9060 0x21f 0x7026f000 0xfcaf8 0x23c 0x74bad000 0x100590 0x25c 0x794eb000 0x104028 0x27c 0x7de29000 0x107ac0 0x29d 0x802c8000 0x10b558 0x2bf 0x82767000 0x10b558 0x2bf 0x870a5000 0x10eff0 0x2e2>;
  6558. qcom,speed1-pvs2-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc5c10 0x81 0x22551000 0xc8320 0x96 0x26e8f000 0xcaa30 0xab 0x2b7cd000 0xcd140 0xc1 0x3010b000 0xcf850 0xd7 0x34a49000 0xd1f60 0xed 0x39387000 0xd4670 0x104 0x3dcc5000 0xd6d80 0x11a 0x42603000 0xd9490 0x132 0x46f41000 0xdbba0 0x14a 0x4b87f000 0xde2b0 0x162 0x501bd000 0xe09c0 0x17a 0x54afb000 0xe4458 0x194 0x59439000 0xe7ef0 0x1af 0x5dd77000 0xeb988 0x1ca 0x626b5000 0xef420 0x1e6 0x66ff3000 0xf2eb8 0x203 0x6b931000 0xf6950 0x21f 0x7026f000 0xfa3e8 0x23c 0x74bad000 0xfde80 0x25c 0x794eb000 0x101918 0x27c 0x7de29000 0x1053b0 0x29d 0x802c8000 0x108e48 0x2bf 0x82767000 0x108e48 0x2bf 0x870a5000 0x10c8e0 0x2e2>;
  6559. qcom,speed1-pvs3-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc5c10 0x96 0x26e8f000 0xc8320 0xab 0x2b7cd000 0xcaa30 0xc1 0x3010b000 0xcd140 0xd7 0x34a49000 0xcf850 0xed 0x39387000 0xd1f60 0x104 0x3dcc5000 0xd4670 0x11a 0x42603000 0xd6d80 0x132 0x46f41000 0xd9490 0x14a 0x4b87f000 0xdbba0 0x162 0x501bd000 0xde2b0 0x17a 0x54afb000 0xe1d48 0x194 0x59439000 0xe57e0 0x1af 0x5dd77000 0xe9278 0x1ca 0x626b5000 0xecd10 0x1e6 0x66ff3000 0xf07a8 0x203 0x6b931000 0xf4240 0x21f 0x7026f000 0xf7cd8 0x23c 0x74bad000 0xfb770 0x25c 0x794eb000 0xff208 0x27c 0x7de29000 0x102ca0 0x29d 0x802c8000 0x106738 0x2bf 0x82767000 0x106738 0x2bf 0x870a5000 0x10a1d0 0x2e2>;
  6560. qcom,speed1-pvs4-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc5c10 0xab 0x2b7cd000 0xc8320 0xc1 0x3010b000 0xcaa30 0xd7 0x34a49000 0xcd140 0xed 0x39387000 0xcf850 0x104 0x3dcc5000 0xd1f60 0x11a 0x42603000 0xd4670 0x132 0x46f41000 0xd6d80 0x14a 0x4b87f000 0xd9490 0x162 0x501bd000 0xdbba0 0x17a 0x54afb000 0xdf638 0x194 0x59439000 0xe30d0 0x1af 0x5dd77000 0xe6b68 0x1ca 0x626b5000 0xea600 0x1e6 0x66ff3000 0xee098 0x203 0x6b931000 0xf1b30 0x21f 0x7026f000 0xf55c8 0x23c 0x74bad000 0xf9060 0x25c 0x794eb000 0xfcaf8 0x27c 0x7de29000 0x100590 0x29d 0x802c8000 0x104028 0x2bf 0x82767000 0x104028 0x2bf 0x870a5000 0x107ac0 0x2e2>;
  6561. qcom,speed1-pvs5-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc5c10 0xc1 0x3010b000 0xc8320 0xd7 0x34a49000 0xcaa30 0xed 0x39387000 0xcd140 0x104 0x3dcc5000 0xcf850 0x11a 0x42603000 0xd1f60 0x132 0x46f41000 0xd4670 0x14a 0x4b87f000 0xd6d80 0x162 0x501bd000 0xd9490 0x17a 0x54afb000 0xdcf28 0x194 0x59439000 0xe09c0 0x1af 0x5dd77000 0xe4458 0x1ca 0x626b5000 0xe7ef0 0x1e6 0x66ff3000 0xeb988 0x203 0x6b931000 0xef420 0x21f 0x7026f000 0xf2eb8 0x23c 0x74bad000 0xf6950 0x25c 0x794eb000 0xfa3e8 0x27c 0x7de29000 0xfde80 0x29d 0x802c8000 0x101918 0x2bf 0x82767000 0x101918 0x2bf 0x870a5000 0x1053b0 0x2e2>;
  6562. qcom,speed1-pvs6-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc5c10 0x96 0x26e8f000 0xc8320 0xab 0x2b7cd000 0xcaa30 0xc1 0x3010b000 0xcd140 0xd7 0x34a49000 0xcf850 0xed 0x39387000 0xd1f60 0x104 0x3dcc5000 0xd4670 0x11a 0x42603000 0xd6d80 0x132 0x46f41000 0xd9490 0x14a 0x4b87f000 0xdbba0 0x162 0x501bd000 0xde2b0 0x17a 0x54afb000 0xe1d48 0x194 0x59439000 0xe57e0 0x1af 0x5dd77000 0xe9278 0x1ca 0x626b5000 0xecd10 0x1e6 0x66ff3000 0xf07a8 0x203 0x6b931000 0xf4240 0x21f 0x7026f000 0xf7cd8 0x23c 0x74bad000 0xfb770 0x25c 0x794eb000 0xff208 0x27c 0x7de29000 0x102ca0 0x29d 0x802c8000 0x106738 0x2bf 0x82767000 0x106738 0x2bf 0x870a5000 0x10a1d0 0x2e2>;
  6563. qcom,speed1-pvs7-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc5c10 0xab 0x2b7cd000 0xc8320 0xc1 0x3010b000 0xcaa30 0xd7 0x34a49000 0xcd140 0xed 0x39387000 0xcf850 0x104 0x3dcc5000 0xd1f60 0x11a 0x42603000 0xd4670 0x132 0x46f41000 0xd6d80 0x14a 0x4b87f000 0xd9490 0x162 0x501bd000 0xdbba0 0x17a 0x54afb000 0xdf638 0x194 0x59439000 0xe30d0 0x1af 0x5dd77000 0xe6b68 0x1ca 0x626b5000 0xea600 0x1e6 0x66ff3000 0xee098 0x203 0x6b931000 0xf1b30 0x21f 0x7026f000 0xf55c8 0x23c 0x74bad000 0xf9060 0x25c 0x794eb000 0xfcaf8 0x27c 0x7de29000 0x100590 0x29d 0x802c8000 0x104028 0x2bf 0x82767000 0x104028 0x2bf 0x870a5000 0x107ac0 0x2e2>;
  6564. qcom,speed1-pvs8-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc5c10 0xc1 0x3010b000 0xc8320 0xd7 0x34a49000 0xcaa30 0xed 0x39387000 0xcd140 0x104 0x3dcc5000 0xcf850 0x11a 0x42603000 0xd1f60 0x132 0x46f41000 0xd4670 0x14a 0x4b87f000 0xd6d80 0x162 0x501bd000 0xd9490 0x17a 0x54afb000 0xdcf28 0x194 0x59439000 0xe09c0 0x1af 0x5dd77000 0xe4458 0x1ca 0x626b5000 0xe7ef0 0x1e6 0x66ff3000 0xeb988 0x203 0x6b931000 0xef420 0x21f 0x7026f000 0xf2eb8 0x23c 0x74bad000 0xf6950 0x25c 0x794eb000 0xfa3e8 0x27c 0x7de29000 0xfde80 0x29d 0x802c8000 0x101918 0x2bf 0x82767000 0x101918 0x2bf 0x870a5000 0x1053b0 0x2e2>;
  6565. qcom,speed1-pvs9-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc4888 0xc1 0x3010b000 0xc6f98 0xd7 0x34a49000 0xc96a8 0xed 0x39387000 0xcbdb8 0x104 0x3dcc5000 0xce4c8 0x11a 0x42603000 0xd0bd8 0x132 0x46f41000 0xd32e8 0x14a 0x4b87f000 0xd59f8 0x162 0x501bd000 0xd8108 0x17a 0x54afb000 0xda818 0x194 0x59439000 0xde2b0 0x1af 0x5dd77000 0xe1d48 0x1ca 0x626b5000 0xe57e0 0x1e6 0x66ff3000 0xe9278 0x203 0x6b931000 0xecd10 0x21f 0x7026f000 0xf07a8 0x23c 0x74bad000 0xf4240 0x25c 0x794eb000 0xf7cd8 0x27c 0x7de29000 0xfb770 0x29d 0x802c8000 0xff208 0x2bf 0x82767000 0xff208 0x2bf 0x870a5000 0x102ca0 0x2e2>;
  6566. qcom,speed1-pvs10-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc4888 0xc1 0x3010b000 0xc6f98 0xd7 0x34a49000 0xc96a8 0xed 0x39387000 0xcbdb8 0x104 0x3dcc5000 0xce4c8 0x11a 0x42603000 0xd0bd8 0x132 0x46f41000 0xd32e8 0x14a 0x4b87f000 0xd59f8 0x162 0x501bd000 0xd8108 0x17a 0x54afb000 0xda818 0x194 0x59439000 0xde2b0 0x1af 0x5dd77000 0xe1d48 0x1ca 0x626b5000 0xe57e0 0x1e6 0x66ff3000 0xe9278 0x203 0x6b931000 0xecd10 0x21f 0x7026f000 0xf07a8 0x23c 0x74bad000 0xf4240 0x25c 0x794eb000 0xf7cd8 0x27c 0x7de29000 0xfb770 0x29d 0x802c8000 0xff208 0x2bf 0x82767000 0xff208 0x2bf 0x870a5000 0x102ca0 0x2e2>;
  6567. qcom,speed1-pvs11-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc3500 0xc1 0x3010b000 0xc5c10 0xd7 0x34a49000 0xc8320 0xed 0x39387000 0xcaa30 0x104 0x3dcc5000 0xcd140 0x11a 0x42603000 0xcf850 0x132 0x46f41000 0xd1f60 0x14a 0x4b87f000 0xd4670 0x162 0x501bd000 0xd6d80 0x17a 0x54afb000 0xd9490 0x194 0x59439000 0xdbba0 0x1af 0x5dd77000 0xdf638 0x1ca 0x626b5000 0xe30d0 0x1e6 0x66ff3000 0xe6b68 0x203 0x6b931000 0xea600 0x21f 0x7026f000 0xee098 0x23c 0x74bad000 0xf1b30 0x25c 0x794eb000 0xf55c8 0x27c 0x7de29000 0xf9060 0x29d 0x802c8000 0xfcaf8 0x2bf 0x82767000 0xfcaf8 0x2bf 0x870a5000 0x100590 0x2e2>;
  6568. qcom,speed1-pvs12-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc3500 0xc1 0x3010b000 0xc3500 0xd7 0x34a49000 0xc5c10 0xed 0x39387000 0xc8320 0x104 0x3dcc5000 0xcaa30 0x11a 0x42603000 0xcd140 0x132 0x46f41000 0xcf850 0x14a 0x4b87f000 0xd1f60 0x162 0x501bd000 0xd4670 0x17a 0x54afb000 0xd6d80 0x194 0x59439000 0xd9490 0x1af 0x5dd77000 0xdcf28 0x1ca 0x626b5000 0xe09c0 0x1e6 0x66ff3000 0xe4458 0x203 0x6b931000 0xe7ef0 0x21f 0x7026f000 0xeb988 0x23c 0x74bad000 0xef420 0x25c 0x794eb000 0xf2eb8 0x27c 0x7de29000 0xf6950 0x29d 0x802c8000 0xfa3e8 0x2bf 0x82767000 0xfa3e8 0x2bf 0x870a5000 0xfde80 0x2e2>;
  6569. qcom,speed1-pvs13-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc3500 0xc1 0x3010b000 0xc3500 0xd7 0x34a49000 0xc5c10 0xed 0x39387000 0xc8320 0x104 0x3dcc5000 0xc96a8 0x11a 0x42603000 0xcbdb8 0x132 0x46f41000 0xce4c8 0x14a 0x4b87f000 0xd0bd8 0x162 0x501bd000 0xd32e8 0x17a 0x54afb000 0xd59f8 0x194 0x59439000 0xd8108 0x1af 0x5dd77000 0xda818 0x1ca 0x626b5000 0xde2b0 0x1e6 0x66ff3000 0xe1d48 0x203 0x6b931000 0xe57e0 0x21f 0x7026f000 0xe9278 0x23c 0x74bad000 0xecd10 0x25c 0x794eb000 0xf07a8 0x27c 0x7de29000 0xf4240 0x29d 0x802c8000 0xf7cd8 0x2bf 0x82767000 0xf7cd8 0x2bf 0x870a5000 0xfb770 0x2e2>;
  6570. qcom,speed1-pvs14-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc3500 0xc1 0x3010b000 0xc3500 0xd7 0x34a49000 0xc5c10 0xed 0x39387000 0xc5c10 0x104 0x3dcc5000 0xc6f98 0x11a 0x42603000 0xc8320 0x132 0x46f41000 0xc96a8 0x14a 0x4b87f000 0xcbdb8 0x162 0x501bd000 0xce4c8 0x17a 0x54afb000 0xd0bd8 0x194 0x59439000 0xd32e8 0x1af 0x5dd77000 0xd59f8 0x1ca 0x626b5000 0xd8108 0x1e6 0x66ff3000 0xda818 0x203 0x6b931000 0xdcf28 0x21f 0x7026f000 0xdf638 0x23c 0x74bad000 0xe30d0 0x25c 0x794eb000 0xe6b68 0x27c 0x7de29000 0xea600 0x29d 0x802c8000 0xee098 0x2bf 0x82767000 0xee098 0x2bf 0x870a5000 0xf1b30 0x2e2>;
  6571. qcom,speed1-pvs15-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6c 0x1dc13000 0xc3500 0x81 0x22551000 0xc3500 0x96 0x26e8f000 0xc3500 0xab 0x2b7cd000 0xc3500 0xc1 0x3010b000 0xc3500 0xd7 0x34a49000 0xc3500 0xed 0x39387000 0xc3500 0x104 0x3dcc5000 0xc3500 0x11a 0x42603000 0xc5c10 0x132 0x46f41000 0xc8320 0x14a 0x4b87f000 0xcaa30 0x162 0x501bd000 0xcd140 0x17a 0x54afb000 0xcf850 0x194 0x59439000 0xd1f60 0x1af 0x5dd77000 0xd4670 0x1ca 0x626b5000 0xd6d80 0x1e6 0x66ff3000 0xd9490 0x203 0x6b931000 0xdbba0 0x21f 0x7026f000 0xde2b0 0x23c 0x74bad000 0xe09c0 0x25c 0x794eb000 0xe4458 0x27c 0x7de29000 0xe7ef0 0x29d 0x802c8000 0xeb988 0x2bf 0x82767000 0xeb988 0x2bf 0x870a5000 0xef420 0x2e2>;
  6572. qcom,speed3-pvs0-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc5c10 0x7e 0x22551000 0xc8320 0x93 0x26e8f000 0xcaa30 0xa8 0x2b7cd000 0xcd140 0xbd 0x3010b000 0xcf850 0xd3 0x34a49000 0xd1f60 0xe9 0x39387000 0xd4670 0x100 0x3dcc5000 0xd6d80 0x116 0x42603000 0xd9490 0x12d 0x46f41000 0xdbba0 0x144 0x4b87f000 0xde2b0 0x15c 0x501bd000 0xe09c0 0x174 0x54afb000 0xe30d0 0x18c 0x59439000 0xe57e0 0x1a5 0x5dd77000 0xe7ef0 0x1be 0x626b5000 0xeb988 0x1d9 0x66ff3000 0xef420 0x1f5 0x6b931000 0xf2eb8 0x211 0x7026f000 0xf6950 0x22e 0x74bad000 0xfa3e8 0x24c 0x794eb000 0xfde80 0x269 0x7de29000 0x101918 0x289 0x802c8000 0x1053b0 0x2aa 0x82767000 0x1053b0 0x2aa 0x870a5000 0x108e48 0x2cc 0x8b9e3000 0x10c8e0 0x2ef 0x90321000 0x110378 0x312 0x927c0000 0x111700 0x322>;
  6573. qcom,speed3-pvs1-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc3500 0x7e 0x22551000 0xc5c10 0x93 0x26e8f000 0xc8320 0xa8 0x2b7cd000 0xcaa30 0xbd 0x3010b000 0xcd140 0xd3 0x34a49000 0xcf850 0xe9 0x39387000 0xd1f60 0x100 0x3dcc5000 0xd4670 0x116 0x42603000 0xd6d80 0x12d 0x46f41000 0xd9490 0x144 0x4b87f000 0xdbba0 0x15c 0x501bd000 0xde2b0 0x174 0x54afb000 0xe09c0 0x18c 0x59439000 0xe30d0 0x1a5 0x5dd77000 0xe57e0 0x1be 0x626b5000 0xe9278 0x1d9 0x66ff3000 0xecd10 0x1f5 0x6b931000 0xf07a8 0x211 0x7026f000 0xf4240 0x22e 0x74bad000 0xf7cd8 0x24c 0x794eb000 0xfb770 0x269 0x7de29000 0xff208 0x289 0x802c8000 0x102ca0 0x2aa 0x82767000 0x102ca0 0x2aa 0x870a5000 0x106738 0x2cc 0x8b9e3000 0x10a1d0 0x2ef 0x90321000 0x10dc68 0x312 0x927c0000 0x10eff0 0x322>;
  6574. qcom,speed3-pvs2-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc3500 0x7e 0x22551000 0xc3500 0x93 0x26e8f000 0xc5c10 0xa8 0x2b7cd000 0xc8320 0xbd 0x3010b000 0xcaa30 0xd3 0x34a49000 0xcd140 0xe9 0x39387000 0xcf850 0x100 0x3dcc5000 0xd1f60 0x116 0x42603000 0xd4670 0x12d 0x46f41000 0xd6d80 0x144 0x4b87f000 0xd9490 0x15c 0x501bd000 0xdbba0 0x174 0x54afb000 0xde2b0 0x18c 0x59439000 0xe09c0 0x1a5 0x5dd77000 0xe30d0 0x1be 0x626b5000 0xe6b68 0x1d9 0x66ff3000 0xea600 0x1f5 0x6b931000 0xee098 0x211 0x7026f000 0xf1b30 0x22e 0x74bad000 0xf55c8 0x24c 0x794eb000 0xf9060 0x269 0x7de29000 0xfcaf8 0x289 0x802c8000 0x100590 0x2aa 0x82767000 0x100590 0x2aa 0x870a5000 0x104028 0x2cc 0x8b9e3000 0x107ac0 0x2ef 0x90321000 0x10b558 0x312 0x927c0000 0x10c8e0 0x322>;
  6575. qcom,speed3-pvs3-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc3500 0x7e 0x22551000 0xc3500 0x93 0x26e8f000 0xc3500 0xa8 0x2b7cd000 0xc5c10 0xbd 0x3010b000 0xc8320 0xd3 0x34a49000 0xcaa30 0xe9 0x39387000 0xcd140 0x100 0x3dcc5000 0xcf850 0x116 0x42603000 0xd1f60 0x12d 0x46f41000 0xd4670 0x144 0x4b87f000 0xd6d80 0x15c 0x501bd000 0xd9490 0x174 0x54afb000 0xdbba0 0x18c 0x59439000 0xde2b0 0x1a5 0x5dd77000 0xe09c0 0x1be 0x626b5000 0xe4458 0x1d9 0x66ff3000 0xe7ef0 0x1f5 0x6b931000 0xeb988 0x211 0x7026f000 0xef420 0x22e 0x74bad000 0xf2eb8 0x24c 0x794eb000 0xf6950 0x269 0x7de29000 0xfa3e8 0x289 0x802c8000 0xfde80 0x2aa 0x82767000 0xfde80 0x2aa 0x870a5000 0x101918 0x2cc 0x8b9e3000 0x1053b0 0x2ef 0x90321000 0x108e48 0x312 0x927c0000 0x10a1d0 0x322>;
  6576. qcom,speed3-pvs4-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc3500 0x7e 0x22551000 0xc3500 0x93 0x26e8f000 0xc3500 0xa8 0x2b7cd000 0xc3500 0xbd 0x3010b000 0xc5c10 0xd3 0x34a49000 0xc8320 0xe9 0x39387000 0xcaa30 0x100 0x3dcc5000 0xcd140 0x116 0x42603000 0xcf850 0x12d 0x46f41000 0xd1f60 0x144 0x4b87f000 0xd4670 0x15c 0x501bd000 0xd6d80 0x174 0x54afb000 0xd9490 0x18c 0x59439000 0xdbba0 0x1a5 0x5dd77000 0xde2b0 0x1be 0x626b5000 0xe1d48 0x1d9 0x66ff3000 0xe57e0 0x1f5 0x6b931000 0xe9278 0x211 0x7026f000 0xecd10 0x22e 0x74bad000 0xf07a8 0x24c 0x794eb000 0xf4240 0x269 0x7de29000 0xf7cd8 0x289 0x802c8000 0xfb770 0x2aa 0x82767000 0xfb770 0x2aa 0x870a5000 0xff208 0x2cc 0x8b9e3000 0x102ca0 0x2ef 0x90321000 0x106738 0x312 0x927c0000 0x107ac0 0x322>;
  6577. qcom,speed3-pvs5-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xc3500 0x4c 0x14997000 0xc3500 0x57 0x192d5000 0xc3500 0x6a 0x1dc13000 0xc3500 0x7e 0x22551000 0xc3500 0x93 0x26e8f000 0xc3500 0xa8 0x2b7cd000 0xc3500 0xbd 0x3010b000 0xc3500 0xd3 0x34a49000 0xc5c10 0xe9 0x39387000 0xc8320 0x100 0x3dcc5000 0xcaa30 0x116 0x42603000 0xcd140 0x12d 0x46f41000 0xcf850 0x144 0x4b87f000 0xd1f60 0x15c 0x501bd000 0xd4670 0x174 0x54afb000 0xd6d80 0x18c 0x59439000 0xd9490 0x1a5 0x5dd77000 0xdbba0 0x1be 0x626b5000 0xdf638 0x1d9 0x66ff3000 0xe30d0 0x1f5 0x6b931000 0xe6b68 0x211 0x7026f000 0xea600 0x22e 0x74bad000 0xee098 0x24c 0x794eb000 0xf1b30 0x269 0x7de29000 0xf55c8 0x289 0x802c8000 0xf9060 0x2aa 0x82767000 0xf9060 0x2aa 0x870a5000 0xfcaf8 0x2cc 0x8b9e3000 0x100590 0x2ef 0x90321000 0x104028 0x312 0x927c0000 0x1053b0 0x322>;
  6578. qcom,speed3-pvs6-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbe6e0 0xbd 0x3010b000 0xc0df0 0xd3 0x34a49000 0xc3500 0xe9 0x39387000 0xc5c10 0x100 0x3dcc5000 0xc8320 0x116 0x42603000 0xcaa30 0x12d 0x46f41000 0xcd140 0x144 0x4b87f000 0xcf850 0x15c 0x501bd000 0xd1f60 0x174 0x54afb000 0xd4670 0x18c 0x59439000 0xd6d80 0x1a5 0x5dd77000 0xd9490 0x1be 0x626b5000 0xdcf28 0x1d9 0x66ff3000 0xe09c0 0x1f5 0x6b931000 0xe4458 0x211 0x7026f000 0xe7ef0 0x22e 0x74bad000 0xeb988 0x24c 0x794eb000 0xef420 0x269 0x7de29000 0xf2eb8 0x289 0x802c8000 0xf6950 0x2aa 0x82767000 0xf6950 0x2aa 0x870a5000 0xfa3e8 0x2cc 0x8b9e3000 0xfde80 0x2ef 0x90321000 0x101918 0x312 0x927c0000 0x102ca0 0x322>;
  6579. qcom,speed3-pvs7-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbe6e0 0xbd 0x3010b000 0xbfa68 0xd3 0x34a49000 0xc2178 0xe9 0x39387000 0xc4888 0x100 0x3dcc5000 0xc6f98 0x116 0x42603000 0xc96a8 0x12d 0x46f41000 0xcbdb8 0x144 0x4b87f000 0xce4c8 0x15c 0x501bd000 0xd0bd8 0x174 0x54afb000 0xd32e8 0x18c 0x59439000 0xd59f8 0x1a5 0x5dd77000 0xd8108 0x1be 0x626b5000 0xda818 0x1d9 0x66ff3000 0xde2b0 0x1f5 0x6b931000 0xe1d48 0x211 0x7026f000 0xe57e0 0x22e 0x74bad000 0xe9278 0x24c 0x794eb000 0xecd10 0x269 0x7de29000 0xf07a8 0x289 0x802c8000 0xf4240 0x2aa 0x82767000 0xf4240 0x2aa 0x870a5000 0xf7cd8 0x2cc 0x8b9e3000 0xfb770 0x2ef 0x90321000 0xff208 0x312 0x927c0000 0x100590 0x322>;
  6580. qcom,speed3-pvs8-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbd358 0xbd 0x3010b000 0xbe6e0 0xd3 0x34a49000 0xbfa68 0xe9 0x39387000 0xc2178 0x100 0x3dcc5000 0xc4888 0x116 0x42603000 0xc6f98 0x12d 0x46f41000 0xc96a8 0x144 0x4b87f000 0xcbdb8 0x15c 0x501bd000 0xce4c8 0x174 0x54afb000 0xd0bd8 0x18c 0x59439000 0xd32e8 0x1a5 0x5dd77000 0xd59f8 0x1be 0x626b5000 0xd8108 0x1d9 0x66ff3000 0xdbba0 0x1f5 0x6b931000 0xdf638 0x211 0x7026f000 0xe30d0 0x22e 0x74bad000 0xe6b68 0x24c 0x794eb000 0xea600 0x269 0x7de29000 0xee098 0x289 0x802c8000 0xf1b30 0x2aa 0x82767000 0xf1b30 0x2aa 0x870a5000 0xf55c8 0x2cc 0x8b9e3000 0xf9060 0x2ef 0x90321000 0xfcaf8 0x312 0x927c0000 0xfde80 0x322>;
  6581. qcom,speed3-pvs9-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbd358 0xbd 0x3010b000 0xbd358 0xd3 0x34a49000 0xbe6e0 0xe9 0x39387000 0xc0df0 0x100 0x3dcc5000 0xc3500 0x116 0x42603000 0xc5c10 0x12d 0x46f41000 0xc8320 0x144 0x4b87f000 0xcaa30 0x15c 0x501bd000 0xcd140 0x174 0x54afb000 0xcf850 0x18c 0x59439000 0xd1f60 0x1a5 0x5dd77000 0xd4670 0x1be 0x626b5000 0xd6d80 0x1d9 0x66ff3000 0xd9490 0x1f5 0x6b931000 0xdcf28 0x211 0x7026f000 0xe09c0 0x22e 0x74bad000 0xe4458 0x24c 0x794eb000 0xe7ef0 0x269 0x7de29000 0xeb988 0x289 0x802c8000 0xef420 0x2aa 0x82767000 0xef420 0x2aa 0x870a5000 0xf2eb8 0x2cc 0x8b9e3000 0xf6950 0x2ef 0x90321000 0xfa3e8 0x312 0x927c0000 0xfb770 0x322>;
  6582. qcom,speed3-pvs10-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbd358 0xbd 0x3010b000 0xbd358 0xd3 0x34a49000 0xbe6e0 0xe9 0x39387000 0xbfa68 0x100 0x3dcc5000 0xc2178 0x116 0x42603000 0xc4888 0x12d 0x46f41000 0xc6f98 0x144 0x4b87f000 0xc96a8 0x15c 0x501bd000 0xcbdb8 0x174 0x54afb000 0xce4c8 0x18c 0x59439000 0xd0bd8 0x1a5 0x5dd77000 0xd32e8 0x1be 0x626b5000 0xd59f8 0x1d9 0x66ff3000 0xd8108 0x1f5 0x6b931000 0xda818 0x211 0x7026f000 0xde2b0 0x22e 0x74bad000 0xe1d48 0x24c 0x794eb000 0xe57e0 0x269 0x7de29000 0xe9278 0x289 0x802c8000 0xecd10 0x2aa 0x82767000 0xecd10 0x2aa 0x870a5000 0xf07a8 0x2cc 0x8b9e3000 0xf4240 0x2ef 0x90321000 0xf7cd8 0x312 0x927c0000 0xf9060 0x322>;
  6583. qcom,speed3-pvs11-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbd358 0xbd 0x3010b000 0xbd358 0xd3 0x34a49000 0xbd358 0xe9 0x39387000 0xbe6e0 0x100 0x3dcc5000 0xc0df0 0x116 0x42603000 0xc3500 0x12d 0x46f41000 0xc5c10 0x144 0x4b87f000 0xc8320 0x15c 0x501bd000 0xcaa30 0x174 0x54afb000 0xcd140 0x18c 0x59439000 0xcf850 0x1a5 0x5dd77000 0xd1f60 0x1be 0x626b5000 0xd4670 0x1d9 0x66ff3000 0xd6d80 0x1f5 0x6b931000 0xd9490 0x211 0x7026f000 0xdbba0 0x22e 0x74bad000 0xdf638 0x24c 0x794eb000 0xe30d0 0x269 0x7de29000 0xe6b68 0x289 0x802c8000 0xea600 0x2aa 0x82767000 0xea600 0x2aa 0x870a5000 0xee098 0x2cc 0x8b9e3000 0xf1b30 0x2ef 0x90321000 0xf55c8 0x312 0x927c0000 0xf6950 0x322>;
  6584. qcom,speed3-pvs12-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbd358 0xbd 0x3010b000 0xbd358 0xd3 0x34a49000 0xbd358 0xe9 0x39387000 0xbe6e0 0x100 0x3dcc5000 0xbfa68 0x116 0x42603000 0xc2178 0x12d 0x46f41000 0xc4888 0x144 0x4b87f000 0xc6f98 0x15c 0x501bd000 0xc96a8 0x174 0x54afb000 0xcbdb8 0x18c 0x59439000 0xce4c8 0x1a5 0x5dd77000 0xd0bd8 0x1be 0x626b5000 0xd32e8 0x1d9 0x66ff3000 0xd59f8 0x1f5 0x6b931000 0xd8108 0x211 0x7026f000 0xda818 0x22e 0x74bad000 0xdcf28 0x24c 0x794eb000 0xe09c0 0x269 0x7de29000 0xe4458 0x289 0x802c8000 0xe7ef0 0x2aa 0x82767000 0xe7ef0 0x2aa 0x870a5000 0xeb988 0x2cc 0x8b9e3000 0xef420 0x2ef 0x90321000 0xf2eb8 0x312 0x927c0000 0xf4240 0x322>;
  6585. qcom,speed3-pvs13-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xbd358 0x4c 0x14997000 0xbd358 0x57 0x192d5000 0xbd358 0x6a 0x1dc13000 0xbd358 0x7e 0x22551000 0xbd358 0x93 0x26e8f000 0xbd358 0xa8 0x2b7cd000 0xbd358 0xbd 0x3010b000 0xbd358 0xd3 0x34a49000 0xbd358 0xe9 0x39387000 0xbd358 0x100 0x3dcc5000 0xbe6e0 0x116 0x42603000 0xc0df0 0x12d 0x46f41000 0xc3500 0x144 0x4b87f000 0xc5c10 0x15c 0x501bd000 0xc8320 0x174 0x54afb000 0xcaa30 0x18c 0x59439000 0xcd140 0x1a5 0x5dd77000 0xcf850 0x1be 0x626b5000 0xd1f60 0x1d9 0x66ff3000 0xd4670 0x1f5 0x6b931000 0xd6d80 0x211 0x7026f000 0xd9490 0x22e 0x74bad000 0xdbba0 0x24c 0x794eb000 0xde2b0 0x269 0x7de29000 0xe1d48 0x289 0x802c8000 0xe57e0 0x2aa 0x82767000 0xe57e0 0x2aa 0x870a5000 0xe9278 0x2cc 0x8b9e3000 0xecd10 0x2ef 0x90321000 0xf07a8 0x312 0x927c0000 0xf1b30 0x322>;
  6586. qcom,speed3-pvs14-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x4c 0x14997000 0xb71b0 0x57 0x192d5000 0xb71b0 0x6a 0x1dc13000 0xb71b0 0x7e 0x22551000 0xb71b0 0x93 0x26e8f000 0xb71b0 0xa8 0x2b7cd000 0xb71b0 0xbd 0x3010b000 0xb71b0 0xd3 0x34a49000 0xb8538 0xe9 0x39387000 0xbac48 0x100 0x3dcc5000 0xbd358 0x116 0x42603000 0xbfa68 0x12d 0x46f41000 0xc2178 0x144 0x4b87f000 0xc4888 0x15c 0x501bd000 0xc6f98 0x174 0x54afb000 0xc96a8 0x18c 0x59439000 0xcbdb8 0x1a5 0x5dd77000 0xce4c8 0x1be 0x626b5000 0xd0bd8 0x1d9 0x66ff3000 0xd32e8 0x1f5 0x6b931000 0xd59f8 0x211 0x7026f000 0xd8108 0x22e 0x74bad000 0xda818 0x24c 0x794eb000 0xdcf28 0x269 0x7de29000 0xdf638 0x289 0x802c8000 0xe30d0 0x2aa 0x82767000 0xe30d0 0x2aa 0x870a5000 0xe6b68 0x2cc 0x8b9e3000 0xea600 0x2ef 0x90321000 0xee098 0x312 0x927c0000 0xef420 0x322>;
  6587. qcom,speed3-pvs15-bin-v1 = <0x0 0x0 0x0 0x11e1a300 0xb71b0 0x4c 0x14997000 0xb71b0 0x57 0x192d5000 0xb71b0 0x6a 0x1dc13000 0xb71b0 0x7e 0x22551000 0xb71b0 0x93 0x26e8f000 0xb71b0 0xa8 0x2b7cd000 0xb71b0 0xbd 0x3010b000 0xb71b0 0xd3 0x34a49000 0xb8538 0xe9 0x39387000 0xb98c0 0x100 0x3dcc5000 0xbbfd0 0x116 0x42603000 0xbe6e0 0x12d 0x46f41000 0xc0df0 0x144 0x4b87f000 0xc3500 0x15c 0x501bd000 0xc5c10 0x174 0x54afb000 0xc8320 0x18c 0x59439000 0xcaa30 0x1a5 0x5dd77000 0xcd140 0x1be 0x626b5000 0xcf850 0x1d9 0x66ff3000 0xd1f60 0x1f5 0x6b931000 0xd4670 0x211 0x7026f000 0xd6d80 0x22e 0x74bad000 0xd9490 0x24c 0x794eb000 0xdbba0 0x269 0x7de29000 0xde2b0 0x289 0x802c8000 0xe09c0 0x2aa 0x82767000 0xe09c0 0x2aa 0x870a5000 0xe4458 0x2cc 0x8b9e3000 0xe7ef0 0x2ef 0x90321000 0xeb988 0x312 0x927c0000 0xecd10 0x322>;
  6588. };
  6589.  
  6590. qcom,cpubw {
  6591. compatible = "qcom,cpubw";
  6592. qcom,cpu-mem-ports = <0x1 0x200 0x2 0x200>;
  6593. qcom,bw-tbl = <0x17d 0x23c 0x2fa 0x478 0x5f5 0x926 0xdb5 0x124c 0x17d7 0x1bbe>;
  6594. };
  6595.  
  6596. qcom,kraitbw-l2pm {
  6597. compatible = "qcom,kraitbw-l2pm";
  6598. interrupts = <0x0 0x1 0x1>;
  6599. qcom,bytes-per-beat = <0x8>;
  6600. };
  6601.  
  6602. qcom,msm-cpufreq@0 {
  6603. reg = <0x0 0x4>;
  6604. compatible = "qcom,msm-cpufreq";
  6605. qcom,cpufreq-table = <0x493e0 0x493e0 0x23c 0x67200 0x67200 0x478 0x9f600 0x79e00 0x5f5 0xb2200 0x8ca00 0x926 0xd7a00 0x8ca00 0x926 0xea600 0xea600 0xdb5 0xfd200 0xfd200 0xdb5 0x122a00 0xfd200 0xdb5 0x135600 0x135600 0x124c 0x16da00 0x16da00 0x124c 0x180600 0x180600 0x17d7 0x1a5e00 0x193200 0x17d7 0x1de200 0x1a5e00 0x1bbe 0x229200 0x1a5e00 0x1bbe 0x258000 0x1a5e00 0x1bbe>;
  6606. };
  6607.  
  6608. qcom,ssusb@f9200000 {
  6609. compatible = "qcom,dwc-usb3-msm";
  6610. reg = <0xf9200000 0xfc000 0xfd4ab000 0x4>;
  6611. #address-cells = <0x1>;
  6612. #size-cells = <0x1>;
  6613. ranges;
  6614. interrupt-parent = <0x60>;
  6615. interrupts = <0x0 0x1>;
  6616. #interrupt-cells = <0x1>;
  6617. interrupt-map-mask = <0x0 0xffffffff>;
  6618. interrupt-map = <0x0 0x0 0x1 0x0 0x85 0x0 0x0 0x1 0x61 0x0 0x0 0x9 0x0>;
  6619. interrupt-names = "hs_phy_irq", "pmic_id_irq";
  6620. ssusb_vdd_dig-supply = <0x23>;
  6621. SSUSB_1p8-supply = <0x41>;
  6622. hsusb_vdd_dig-supply = <0x23>;
  6623. HSUSB_1p8-supply = <0x41>;
  6624. HSUSB_3p3-supply = <0x42>;
  6625. vbus_dwc3-supply = <0x62>;
  6626. qcom,dwc-usb3-msm-dbm-eps = <0x4>;
  6627. qcom,vdd-voltage-level = <0x1 0x5 0x7>;
  6628. qcom,dwc-hsphy-init = <0xd191a4>;
  6629. qcom,misc-ref = <0x63>;
  6630. dwc_usb3-adc_tm = <0x51>;
  6631. qcom,dwc-usb3-msm-tx-fifo-size = <0x7400>;
  6632. qcom,dwc-usb3-msm-qdss-tx-fifo-size = <0x2000>;
  6633. qcom,msm-bus,name = "usb3";
  6634. qcom,msm-bus,num-cases = <0x2>;
  6635. qcom,msm-bus,num-paths = <0x1>;
  6636. qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x0 0x0 0x3d 0x200 0x3a980 0xea600>;
  6637. qcom,usbin-vadc = <0x4f>;
  6638. qcom,utmi-clk-rate = <0x16e3600>;
  6639. qcom,otg-capability;
  6640. linux,phandle = <0x60>;
  6641. phandle = <0x60>;
  6642.  
  6643. dwc3@f9200000 {
  6644. compatible = "synopsys,dwc3";
  6645. reg = <0xf9200000 0xfc000>;
  6646. interrupt-parent = <0x1>;
  6647. interrupts = <0x0 0x83 0x0 0x0 0xb3 0x0>;
  6648. interrupt-names = "irq", "otg_irq";
  6649. tx-fifo-resize;
  6650. };
  6651. };
  6652.  
  6653. qcom,ehci-host@f9a55000 {
  6654. compatible = "qcom,ehci-host";
  6655. status = "ok";
  6656. reg = <0xf9a55000 0x400>;
  6657. interrupts = <0x0 0x86 0x0 0x0 0x8c 0x0>;
  6658. interrupt-names = "core_irq", "async_irq";
  6659. HSUSB_VDDCX-supply = <0x64>;
  6660. HSUSB_1p8-supply = <0x41>;
  6661. HSUSB_3p3-supply = <0x42>;
  6662. qcom,usb2-enable-hsphy2;
  6663. qcom,usb2-power-budget = <0x1f4>;
  6664. hsusb_vdd_dig-supply = <0x23>;
  6665. qcom,vdd-voltage-level = <0x1 0x2 0x3 0x5 0x7>;
  6666. vbus-supply = <0x4d>;
  6667. };
  6668.  
  6669. qcom,lpass@fe200000 {
  6670. compatible = "qcom,pil-q6v5-lpass";
  6671. reg = <0xfe200000 0x100 0xfd485100 0x10 0xfc4016c0 0x4>;
  6672. reg-names = "qdsp6_base", "halt_base", "restart_reg";
  6673. vdd_cx-supply = <0x23>;
  6674. interrupts = <0x0 0xa2 0x1>;
  6675. qcom,firmware-name = "adsp";
  6676. qcom,gpio-err-fatal = <0x65 0x0 0x0>;
  6677. qcom,gpio-proxy-unvote = <0x65 0x2 0x0>;
  6678. qcom,gpio-err-ready = <0x65 0x1 0x0>;
  6679. qcom,gpio-force-stop = <0x66 0x0 0x0>;
  6680. };
  6681.  
  6682. qcom,msm-adsp-loader {
  6683. compatible = "qcom,adsp-loader";
  6684. qcom,adsp-state = <0x0>;
  6685. };
  6686.  
  6687. qcom,msm-audio-ion {
  6688. compatible = "qcom,msm-audio-ion";
  6689. };
  6690.  
  6691. qti,msm-pcm {
  6692. compatible = "qti,msm-pcm-dsp";
  6693. qti,msm-pcm-dsp-id = <0x0>;
  6694. };
  6695.  
  6696. qti,msm-pcm-low-latency {
  6697. compatible = "qti,msm-pcm-dsp";
  6698. qti,msm-pcm-dsp-id = <0x1>;
  6699. qti,msm-pcm-low-latency;
  6700. qti,latency-level = "regular";
  6701. };
  6702.  
  6703. qcom,msm-pcm-routing {
  6704. compatible = "qcom,msm-pcm-routing";
  6705. };
  6706.  
  6707. qcom,msm-pcm-lpa {
  6708. compatible = "qcom,msm-pcm-lpa";
  6709. };
  6710.  
  6711. qcom,msm-compr-dsp {
  6712. compatible = "qcom,msm-compr-dsp";
  6713. };
  6714.  
  6715. qcom,msm-compress-dsp {
  6716. compatible = "qcom,msm-compress-dsp";
  6717. };
  6718.  
  6719. qcom,msm-voip-dsp {
  6720. compatible = "qcom,msm-voip-dsp";
  6721. };
  6722.  
  6723. qcom,msm-pcm-voice {
  6724. compatible = "qcom,msm-pcm-voice";
  6725. };
  6726.  
  6727. qcom,msm-stub-codec {
  6728. compatible = "qcom,msm-stub-codec";
  6729. };
  6730.  
  6731. qcom,msm-dai-fe {
  6732. compatible = "qcom,msm-dai-fe";
  6733. };
  6734.  
  6735. qcom,msm-pcm-afe {
  6736. compatible = "qcom,msm-pcm-afe";
  6737. };
  6738.  
  6739. qcom,msm-dai-q6-hdmi {
  6740. compatible = "qcom,msm-dai-q6-hdmi";
  6741. qcom,msm-dai-q6-dev-id = <0x8>;
  6742. };
  6743.  
  6744. qcom,msm-lsm-client {
  6745. compatible = "qcom,msm-lsm-client";
  6746. };
  6747.  
  6748. qti,msm-pcm-loopback {
  6749. compatible = "qti,msm-pcm-loopback";
  6750. };
  6751.  
  6752. qcom,msm-voice-svc {
  6753. compatible = "qcom,msm-voice-svc";
  6754. };
  6755.  
  6756. qcom,msm-dai-q6 {
  6757. compatible = "qcom,msm-dai-q6";
  6758.  
  6759. qcom,msm-dai-q6-sb-0-rx {
  6760. compatible = "qcom,msm-dai-q6-dev";
  6761. qcom,msm-dai-q6-dev-id = <0x4000>;
  6762. };
  6763.  
  6764. qcom,msm-dai-q6-sb-0-tx {
  6765. compatible = "qcom,msm-dai-q6-dev";
  6766. qcom,msm-dai-q6-dev-id = <0x4001>;
  6767. };
  6768.  
  6769. qcom,msm-dai-q6-sb-1-rx {
  6770. compatible = "qcom,msm-dai-q6-dev";
  6771. qcom,msm-dai-q6-dev-id = <0x4002>;
  6772. };
  6773.  
  6774. qcom,msm-dai-q6-sb-1-tx {
  6775. compatible = "qcom,msm-dai-q6-dev";
  6776. qcom,msm-dai-q6-dev-id = <0x4003>;
  6777. };
  6778.  
  6779. qcom,msm-dai-q6-sb-2-rx {
  6780. compatible = "qcom,msm-dai-q6-dev";
  6781. qcom,msm-dai-q6-dev-id = <0x4004>;
  6782. };
  6783.  
  6784. qcom,msm-dai-q6-sb-2-tx {
  6785. compatible = "qcom,msm-dai-q6-dev";
  6786. qcom,msm-dai-q6-dev-id = <0x4005>;
  6787. };
  6788.  
  6789. qcom,msm-dai-q6-sb-3-rx {
  6790. compatible = "qcom,msm-dai-q6-dev";
  6791. qcom,msm-dai-q6-dev-id = <0x4006>;
  6792. };
  6793.  
  6794. qcom,msm-dai-q6-sb-3-tx {
  6795. compatible = "qcom,msm-dai-q6-dev";
  6796. qcom,msm-dai-q6-dev-id = <0x4007>;
  6797. };
  6798.  
  6799. qcom,msm-dai-q6-sb-4-rx {
  6800. compatible = "qcom,msm-dai-q6-dev";
  6801. qcom,msm-dai-q6-dev-id = <0x4008>;
  6802. };
  6803.  
  6804. qcom,msm-dai-q6-sb-4-tx {
  6805. compatible = "qcom,msm-dai-q6-dev";
  6806. qcom,msm-dai-q6-dev-id = <0x4009>;
  6807. };
  6808.  
  6809. qcom,msm-dai-q6-sb-5-tx {
  6810. compatible = "qcom,msm-dai-q6-dev";
  6811. qcom,msm-dai-q6-dev-id = <0x400b>;
  6812. };
  6813.  
  6814. qcom,msm-dai-q6-bt-sco-rx {
  6815. compatible = "qcom,msm-dai-q6-dev";
  6816. qcom,msm-dai-q6-dev-id = <0x3000>;
  6817. };
  6818.  
  6819. qcom,msm-dai-q6-bt-sco-tx {
  6820. compatible = "qcom,msm-dai-q6-dev";
  6821. qcom,msm-dai-q6-dev-id = <0x3001>;
  6822. };
  6823.  
  6824. qcom,msm-dai-q6-int-fm-rx {
  6825. compatible = "qcom,msm-dai-q6-dev";
  6826. qcom,msm-dai-q6-dev-id = <0x3004>;
  6827. };
  6828.  
  6829. qcom,msm-dai-q6-int-fm-tx {
  6830. compatible = "qcom,msm-dai-q6-dev";
  6831. qcom,msm-dai-q6-dev-id = <0x3005>;
  6832. };
  6833.  
  6834. qcom,msm-dai-q6-be-afe-pcm-rx {
  6835. compatible = "qcom,msm-dai-q6-dev";
  6836. qcom,msm-dai-q6-dev-id = <0xe0>;
  6837. };
  6838.  
  6839. qcom,msm-dai-q6-be-afe-pcm-tx {
  6840. compatible = "qcom,msm-dai-q6-dev";
  6841. qcom,msm-dai-q6-dev-id = <0xe1>;
  6842. };
  6843.  
  6844. qcom,msm-dai-q6-afe-proxy-rx {
  6845. compatible = "qcom,msm-dai-q6-dev";
  6846. qcom,msm-dai-q6-dev-id = <0xf1>;
  6847. };
  6848.  
  6849. qcom,msm-dai-q6-afe-proxy-tx {
  6850. compatible = "qcom,msm-dai-q6-dev";
  6851. qcom,msm-dai-q6-dev-id = <0xf0>;
  6852. };
  6853.  
  6854. qcom,msm-dai-q6-incall-record-rx {
  6855. compatible = "qcom,msm-dai-q6-dev";
  6856. qcom,msm-dai-q6-dev-id = <0x8003>;
  6857. };
  6858.  
  6859. qcom,msm-dai-q6-incall-record-tx {
  6860. compatible = "qcom,msm-dai-q6-dev";
  6861. qcom,msm-dai-q6-dev-id = <0x8004>;
  6862. };
  6863.  
  6864. qcom,msm-dai-q6-incall-music-rx {
  6865. compatible = "qcom,msm-dai-q6-dev";
  6866. qcom,msm-dai-q6-dev-id = <0x8005>;
  6867. };
  6868.  
  6869. qcom,msm-dai-q6-incall-music-2-rx {
  6870. compatible = "qcom,msm-dai-q6-dev";
  6871. qcom,msm-dai-q6-dev-id = <0x8002>;
  6872. };
  6873. };
  6874.  
  6875. qcom,msm-pri-auxpcm {
  6876. compatible = "qcom,msm-auxpcm-dev";
  6877. qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>;
  6878. qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>;
  6879. qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>;
  6880. qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>;
  6881. qcom,msm-cpudai-auxpcm-slot = <0x1 0x1>;
  6882. qcom,msm-cpudai-auxpcm-data = <0x0 0x0>;
  6883. qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
  6884. qcom,msm-auxpcm-interface = "primary";
  6885. };
  6886.  
  6887. qcom,msm-sec-auxpcm {
  6888. compatible = "qcom,msm-auxpcm-dev";
  6889. qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>;
  6890. qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>;
  6891. qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>;
  6892. qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>;
  6893. qcom,msm-cpudai-auxpcm-slot = <0x1 0x1>;
  6894. qcom,msm-cpudai-auxpcm-data = <0x0 0x0>;
  6895. qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
  6896. qcom,msm-auxpcm-interface = "secondary";
  6897. };
  6898.  
  6899. qcom,msm-dai-mi2s {
  6900. compatible = "qcom,msm-dai-mi2s";
  6901.  
  6902. qcom,msm-dai-q6-mi2s-quat {
  6903. compatible = "qcom,msm-dai-q6-mi2s";
  6904. qcom,msm-dai-q6-mi2s-dev-id = <0x3>;
  6905. qcom,msm-mi2s-rx-lines = <0x1>;
  6906. qcom,msm-mi2s-tx-lines = <0x2>;
  6907. };
  6908. };
  6909.  
  6910. qcom,msm-pcm-hostless {
  6911. compatible = "qcom,msm-pcm-hostless";
  6912. };
  6913.  
  6914. qcom,msm-ocmem-audio {
  6915. compatible = "qcom,msm-ocmem-audio";
  6916. qcom,msm-bus,name = "audio-ocmem";
  6917. qcom,msm-bus,num-cases = <0x2>;
  6918. qcom,msm-bus,num-paths = <0x1>;
  6919. qcom,msm-bus,vectors-KBps = <0xb 0x25c 0x0 0x0 0xb 0x25c 0x7efa 0x7efa>;
  6920. };
  6921.  
  6922. qcom,msm-adsp-sensors {
  6923. compatible = "qcom,msm-adsp-sensors";
  6924. };
  6925.  
  6926. qcom,mss@fc880000 {
  6927. compatible = "qcom,pil-q6v5-mss";
  6928. reg = <0xfc880000 0x100 0xfd485000 0x400 0xfc820000 0x20 0xfc401680 0x4>;
  6929. reg-names = "qdsp6_base", "halt_base", "rmb_base", "restart_reg";
  6930. interrupts = <0x0 0x18 0x1>;
  6931. vdd_mss-supply = <0x67>;
  6932. vdd_cx-supply = <0x23>;
  6933. vdd_mx-supply = <0x68>;
  6934. vdd_pll-supply = <0x2>;
  6935. qcom,vdd_pll = <0x1b7740>;
  6936. qcom,firmware-name = "mba";
  6937. qcom,pil-self-auth;
  6938. qcom,gpio-err-fatal = <0x69 0x0 0x0>;
  6939. qcom,gpio-err-ready = <0x69 0x1 0x0>;
  6940. qcom,gpio-proxy-unvote = <0x69 0x2 0x0>;
  6941. qcom,gpio-stop-ack = <0x69 0x3 0x0>;
  6942. qcom,gpio-force-stop = <0x6a 0x0 0x0>;
  6943. };
  6944.  
  6945. qcom,pronto@fb21b000 {
  6946. compatible = "qcom,pil-pronto";
  6947. reg = <0xfb21b000 0x3000 0xfc401700 0x4 0xfd485300 0xc>;
  6948. reg-names = "pmu_base", "clk_base", "halt_base";
  6949. interrupts = <0x0 0x95 0x1>;
  6950. vdd_pronto_pll-supply = <0x2>;
  6951. qcom,firmware-name = "wcnss";
  6952. qcom,gpio-err-fatal = <0x6b 0x0 0x0>;
  6953. qcom,gpio-err-ready = <0x6b 0x1 0x0>;
  6954. qcom,gpio-proxy-unvote = <0x6b 0x2 0x0>;
  6955. qcom,gpio-force-stop = <0x6c 0x0 0x0>;
  6956. };
  6957.  
  6958. qcom,iris-fm {
  6959. compatible = "qcom,iris_fm";
  6960. };
  6961.  
  6962. qcom,wcnss-wlan@fb000000 {
  6963. compatible = "qcom,wcnss_wlan";
  6964. reg = <0xfb000000 0x280000 0xf9011008 0x4>;
  6965. reg-names = "wcnss_mmio", "wcnss_fiq";
  6966. interrupts = <0x0 0x91 0x0 0x0 0x92 0x0>;
  6967. interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
  6968. qcom,pronto-vddmx-supply = <0x68>;
  6969. qcom,pronto-vddcx-supply = <0x64>;
  6970. qcom,pronto-vddpx-supply = <0x2d>;
  6971. qcom,iris-vddxo-supply = <0x41>;
  6972. qcom,iris-vddrfa-supply = <0x6d>;
  6973. qcom,iris-vddpa-supply = <0x6e>;
  6974. qcom,iris-vdddig-supply = <0x2d>;
  6975. gpios = <0x5 0x24 0x0 0x5 0x25 0x0 0x5 0x26 0x0 0x5 0x27 0x0 0x5 0x28 0x0>;
  6976. qcom,has-48mhz-xo;
  6977. qcom,has-pronto-hw;
  6978. qcom,wcnss-pm = <0xb 0x13 0x4b0 0x1 0x1 0x6>;
  6979. };
  6980.  
  6981. qcom,ocmem@fdd00000 {
  6982. compatible = "qcom,msm-ocmem";
  6983. reg = <0xfdd00000 0x2000 0xfdd02000 0x2000 0xfe039000 0x400 0xfec00000 0x180000>;
  6984. reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
  6985. interrupts = <0x0 0x4c 0x0 0x0 0x4d 0x0>;
  6986. interrupt-names = "ocmem_irq", "dm_irq";
  6987. qcom,ocmem-num-regions = <0x3>;
  6988. qcom,ocmem-num-macros = <0x18>;
  6989. qcom,resource-type = <0x706d636f>;
  6990. #address-cells = <0x1>;
  6991. #size-cells = <0x1>;
  6992. ranges = <0x0 0xfec00000 0x180000>;
  6993.  
  6994. partition@0 {
  6995. reg = <0x0 0x100000>;
  6996. qcom,ocmem-part-name = "graphics";
  6997. qcom,ocmem-part-min = <0x80000>;
  6998. };
  6999.  
  7000. partition@80000 {
  7001. reg = <0x100000 0x80000>;
  7002. qcom,ocmem-part-name = "lp_audio";
  7003. qcom,ocmem-part-min = <0x80000>;
  7004. };
  7005.  
  7006. partition@100000 {
  7007. reg = <0x100000 0x80000>;
  7008. qcom,ocmem-part-name = "video";
  7009. qcom,ocmem-part-min = <0x55000>;
  7010. };
  7011. };
  7012.  
  7013. qcom,rpm-smd {
  7014. compatible = "qcom,rpm-smd";
  7015. rpm-channel-name = "rpm_requests";
  7016. rpm-channel-type = <0xf>;
  7017.  
  7018. rpm-regulator-smpb1 {
  7019. qcom,resource-name = "smpb";
  7020. qcom,resource-id = <0x1>;
  7021. qcom,regulator-type = <0x1>;
  7022. qcom,hpm-min-load = <0x186a0>;
  7023. compatible = "qcom,rpm-regulator-smd-resource";
  7024. status = "okay";
  7025.  
  7026. regulator-s1 {
  7027. regulator-name = "8841_s1";
  7028. qcom,set = <0x3>;
  7029. status = "okay";
  7030. compatible = "qcom,rpm-regulator-smd";
  7031. regulator-min-microvolt = <0xa4cb8>;
  7032. regulator-max-microvolt = <0x100590>;
  7033. linux,phandle = <0x68>;
  7034. phandle = <0x68>;
  7035. };
  7036.  
  7037. regulator-s1-ao {
  7038. regulator-name = "8841_s1_ao";
  7039. qcom,set = <0x1>;
  7040. regulator-min-microvolt = <0xa4cb8>;
  7041. regulator-max-microvolt = <0x100590>;
  7042. status = "okay";
  7043. compatible = "qcom,rpm-regulator-smd";
  7044. };
  7045.  
  7046. regulator-s1-so {
  7047. regulator-name = "8841_s1_so";
  7048. qcom,set = <0x2>;
  7049. regulator-min-microvolt = <0xa4cb8>;
  7050. regulator-max-microvolt = <0x100590>;
  7051. qcom,init-voltage = <0xa4cb8>;
  7052. status = "okay";
  7053. compatible = "qcom,rpm-regulator-smd";
  7054. };
  7055. };
  7056.  
  7057. rpm-regulator-smpb2 {
  7058. qcom,resource-name = "smpb";
  7059. qcom,resource-id = <0x2>;
  7060. qcom,regulator-type = <0x1>;
  7061. qcom,hpm-min-load = <0x186a0>;
  7062. compatible = "qcom,rpm-regulator-smd-resource";
  7063. status = "okay";
  7064.  
  7065. regulator-s2 {
  7066. regulator-name = "8841_s2";
  7067. qcom,set = <0x3>;
  7068. status = "okay";
  7069. compatible = "qcom,rpm-regulator-smd";
  7070. regulator-min-microvolt = <0x7a120>;
  7071. regulator-max-microvolt = <0x100590>;
  7072. linux,phandle = <0x64>;
  7073. phandle = <0x64>;
  7074. };
  7075.  
  7076. regulator-s2-corner {
  7077. regulator-name = "8841_s2_corner";
  7078. qcom,set = <0x3>;
  7079. regulator-min-microvolt = <0x1>;
  7080. regulator-max-microvolt = <0x7>;
  7081. qcom,use-voltage-corner;
  7082. compatible = "qcom,rpm-regulator-smd";
  7083. qcom,consumer-supplies = "vdd_dig", "";
  7084. qcom,init-smps-mode = <0x0>;
  7085. linux,phandle = <0x23>;
  7086. phandle = <0x23>;
  7087. };
  7088.  
  7089. regulator-s2-corner-ao {
  7090. regulator-name = "8841_s2_corner_ao";
  7091. qcom,set = <0x1>;
  7092. regulator-min-microvolt = <0x1>;
  7093. regulator-max-microvolt = <0x7>;
  7094. qcom,use-voltage-corner;
  7095. compatible = "qcom,rpm-regulator-smd";
  7096. linux,phandle = <0x5e>;
  7097. phandle = <0x5e>;
  7098. };
  7099.  
  7100. regulator-s2-floor-corner {
  7101. compatible = "qcom,rpm-regulator-smd";
  7102. regulator-name = "8841_s2_floor_corner";
  7103. qcom,set = <0x3>;
  7104. regulator-min-microvolt = <0x1>;
  7105. regulator-max-microvolt = <0x7>;
  7106. qcom,use-voltage-floor-corner;
  7107. qcom,always-send-voltage;
  7108. linux,phandle = <0x6f>;
  7109. phandle = <0x6f>;
  7110. };
  7111. };
  7112.  
  7113. rpm-regulator-smpb3 {
  7114. qcom,resource-name = "smpb";
  7115. qcom,resource-id = <0x3>;
  7116. qcom,regulator-type = <0x1>;
  7117. qcom,hpm-min-load = <0x186a0>;
  7118. compatible = "qcom,rpm-regulator-smd-resource";
  7119. status = "okay";
  7120.  
  7121. regulator-s3 {
  7122. regulator-name = "8841_s3";
  7123. qcom,set = <0x3>;
  7124. status = "okay";
  7125. compatible = "qcom,rpm-regulator-smd";
  7126. regulator-min-microvolt = <0x100590>;
  7127. regulator-max-microvolt = <0x100590>;
  7128. qcom,init-voltage = <0x100590>;
  7129. linux,phandle = <0x67>;
  7130. phandle = <0x67>;
  7131. };
  7132. };
  7133.  
  7134. rpm-regulator-smpb4 {
  7135. qcom,resource-name = "smpb";
  7136. qcom,resource-id = <0x4>;
  7137. qcom,regulator-type = <0x1>;
  7138. qcom,hpm-min-load = <0x186a0>;
  7139. compatible = "qcom,rpm-regulator-smd-resource";
  7140. status = "okay";
  7141.  
  7142. regulator-s4 {
  7143. regulator-name = "8841_s4";
  7144. qcom,set = <0x3>;
  7145. status = "okay";
  7146. compatible = "qcom,rpm-regulator-smd";
  7147. regulator-min-microvolt = <0xc6f98>;
  7148. regulator-max-microvolt = <0xdbba0>;
  7149. };
  7150.  
  7151. regulator-s4-corner {
  7152. compatible = "qcom,rpm-regulator-smd";
  7153. regulator-name = "8841_s4_corner";
  7154. qcom,set = <0x3>;
  7155. qcom,use-voltage-corner;
  7156. regulator-min-microvolt = <0x1>;
  7157. regulator-max-microvolt = <0x7>;
  7158. qcom,init-voltage-corner = <0x3>;
  7159. linux,phandle = <0x1a>;
  7160. phandle = <0x1a>;
  7161. };
  7162.  
  7163. regulator-s4-floor-corner {
  7164. compatible = "qcom,rpm-regulator-smd";
  7165. regulator-name = "8841_s4_floor_corner";
  7166. qcom,set = <0x3>;
  7167. regulator-min-microvolt = <0x1>;
  7168. regulator-max-microvolt = <0x7>;
  7169. qcom,use-voltage-floor-corner;
  7170. qcom,always-send-voltage;
  7171. linux,phandle = <0x70>;
  7172. phandle = <0x70>;
  7173. };
  7174. };
  7175.  
  7176. rpm-regulator-smpa1 {
  7177. qcom,resource-name = "smpa";
  7178. qcom,resource-id = <0x1>;
  7179. qcom,regulator-type = <0x1>;
  7180. qcom,hpm-min-load = <0x186a0>;
  7181. compatible = "qcom,rpm-regulator-smd-resource";
  7182. status = "okay";
  7183.  
  7184. regulator-s1 {
  7185. regulator-name = "8941_s1";
  7186. qcom,set = <0x3>;
  7187. status = "okay";
  7188. compatible = "qcom,rpm-regulator-smd";
  7189. regulator-min-microvolt = <0x13d620>;
  7190. regulator-max-microvolt = <0x13d620>;
  7191. qcom,init-voltage = <0x13d620>;
  7192. };
  7193. };
  7194.  
  7195. rpm-regulator-smpa2 {
  7196. qcom,resource-name = "smpa";
  7197. qcom,resource-id = <0x2>;
  7198. qcom,regulator-type = <0x1>;
  7199. qcom,hpm-min-load = <0x186a0>;
  7200. compatible = "qcom,rpm-regulator-smd-resource";
  7201. status = "okay";
  7202.  
  7203. regulator-s2 {
  7204. regulator-name = "8941_s2";
  7205. qcom,set = <0x3>;
  7206. status = "okay";
  7207. compatible = "qcom,rpm-regulator-smd";
  7208. regulator-min-microvolt = <0x20ce70>;
  7209. regulator-max-microvolt = <0x20ce70>;
  7210. qcom,init-voltage = <0x20ce70>;
  7211. linux,phandle = <0x4b>;
  7212. phandle = <0x4b>;
  7213. };
  7214. };
  7215.  
  7216. rpm-regulator-smpa3 {
  7217. qcom,resource-name = "smpa";
  7218. qcom,resource-id = <0x3>;
  7219. qcom,regulator-type = <0x1>;
  7220. qcom,hpm-min-load = <0x186a0>;
  7221. compatible = "qcom,rpm-regulator-smd-resource";
  7222. status = "okay";
  7223.  
  7224. regulator-s3 {
  7225. regulator-name = "8941_s3";
  7226. qcom,set = <0x3>;
  7227. status = "okay";
  7228. compatible = "qcom,rpm-regulator-smd";
  7229. regulator-min-microvolt = <0x1b7740>;
  7230. regulator-max-microvolt = <0x1b7740>;
  7231. qcom,init-voltage = <0x1b7740>;
  7232. linux,phandle = <0x2d>;
  7233. phandle = <0x2d>;
  7234. };
  7235. };
  7236.  
  7237. rpm-regulator-ldoa1 {
  7238. qcom,resource-name = "ldoa";
  7239. qcom,resource-id = <0x1>;
  7240. qcom,regulator-type = <0x0>;
  7241. qcom,hpm-min-load = <0x2710>;
  7242. compatible = "qcom,rpm-regulator-smd-resource";
  7243. status = "okay";
  7244.  
  7245. regulator-l1 {
  7246. regulator-name = "8941_l1";
  7247. qcom,set = <0x3>;
  7248. status = "okay";
  7249. compatible = "qcom,rpm-regulator-smd";
  7250. regulator-min-microvolt = <0x12b128>;
  7251. regulator-max-microvolt = <0x12b128>;
  7252. qcom,init-voltage = <0x12b128>;
  7253. linux,phandle = <0x4c>;
  7254. phandle = <0x4c>;
  7255. };
  7256. };
  7257.  
  7258. rpm-regulator-ldoa2 {
  7259. qcom,resource-name = "ldoa";
  7260. qcom,resource-id = <0x2>;
  7261. qcom,regulator-type = <0x0>;
  7262. qcom,hpm-min-load = <0x2710>;
  7263. compatible = "qcom,rpm-regulator-smd-resource";
  7264. status = "okay";
  7265.  
  7266. regulator-l2 {
  7267. regulator-name = "8941_l2";
  7268. qcom,set = <0x3>;
  7269. status = "okay";
  7270. compatible = "qcom,rpm-regulator-smd";
  7271. regulator-min-microvolt = <0x124f80>;
  7272. regulator-max-microvolt = <0x124f80>;
  7273. qcom,init-voltage = <0x124f80>;
  7274. linux,phandle = <0x27>;
  7275. phandle = <0x27>;
  7276. };
  7277. };
  7278.  
  7279. rpm-regulator-ldoa3 {
  7280. qcom,resource-name = "ldoa";
  7281. qcom,resource-id = <0x3>;
  7282. qcom,regulator-type = <0x0>;
  7283. qcom,hpm-min-load = <0x2710>;
  7284. compatible = "qcom,rpm-regulator-smd-resource";
  7285. status = "okay";
  7286.  
  7287. regulator-l3 {
  7288. regulator-name = "8941_l3";
  7289. qcom,set = <0x3>;
  7290. status = "okay";
  7291. compatible = "qcom,rpm-regulator-smd";
  7292. regulator-min-microvolt = <0x12b128>;
  7293. regulator-max-microvolt = <0x12b128>;
  7294. qcom,init-voltage = <0x12b128>;
  7295. linux,phandle = <0x6>;
  7296. phandle = <0x6>;
  7297. };
  7298. };
  7299.  
  7300. rpm-regulator-ldoa4 {
  7301. qcom,resource-name = "ldoa";
  7302. qcom,resource-id = <0x4>;
  7303. qcom,regulator-type = <0x0>;
  7304. qcom,hpm-min-load = <0x2710>;
  7305. compatible = "qcom,rpm-regulator-smd-resource";
  7306. status = "okay";
  7307.  
  7308. regulator-l4 {
  7309. regulator-name = "8941_l4";
  7310. qcom,set = <0x3>;
  7311. status = "okay";
  7312. compatible = "qcom,rpm-regulator-smd";
  7313. regulator-min-microvolt = <0x12b128>;
  7314. regulator-max-microvolt = <0x12b128>;
  7315. qcom,init-voltage = <0x12b128>;
  7316. };
  7317. };
  7318.  
  7319. rpm-regulator-ldoa5 {
  7320. qcom,resource-name = "ldoa";
  7321. qcom,resource-id = <0x5>;
  7322. qcom,regulator-type = <0x0>;
  7323. qcom,hpm-min-load = <0x2710>;
  7324. compatible = "qcom,rpm-regulator-smd-resource";
  7325. status = "okay";
  7326.  
  7327. regulator-l5 {
  7328. regulator-name = "8941_l5";
  7329. qcom,set = <0x3>;
  7330. status = "okay";
  7331. compatible = "qcom,rpm-regulator-smd";
  7332. regulator-min-microvolt = <0x1b7740>;
  7333. regulator-max-microvolt = <0x1b7740>;
  7334. qcom,init-voltage = <0x1b7740>;
  7335. };
  7336. };
  7337.  
  7338. rpm-regulator-ldoa6 {
  7339. qcom,resource-name = "ldoa";
  7340. qcom,resource-id = <0x6>;
  7341. qcom,regulator-type = <0x0>;
  7342. qcom,hpm-min-load = <0x2710>;
  7343. compatible = "qcom,rpm-regulator-smd-resource";
  7344. status = "okay";
  7345.  
  7346. regulator-l6 {
  7347. regulator-name = "8941_l6";
  7348. qcom,set = <0x3>;
  7349. status = "okay";
  7350. compatible = "qcom,rpm-regulator-smd";
  7351. regulator-min-microvolt = <0x1b7740>;
  7352. regulator-max-microvolt = <0x1b7740>;
  7353. qcom,init-voltage = <0x1b7740>;
  7354. linux,phandle = <0x41>;
  7355. phandle = <0x41>;
  7356. };
  7357. };
  7358.  
  7359. rpm-regulator-ldoa7 {
  7360. qcom,resource-name = "ldoa";
  7361. qcom,resource-id = <0x7>;
  7362. qcom,regulator-type = <0x0>;
  7363. qcom,hpm-min-load = <0x2710>;
  7364. compatible = "qcom,rpm-regulator-smd-resource";
  7365. status = "okay";
  7366.  
  7367. regulator-l7 {
  7368. regulator-name = "8941_l7";
  7369. qcom,set = <0x3>;
  7370. status = "okay";
  7371. compatible = "qcom,rpm-regulator-smd";
  7372. regulator-min-microvolt = <0x1b7740>;
  7373. regulator-max-microvolt = <0x1b7740>;
  7374. qcom,init-voltage = <0x1b7740>;
  7375. };
  7376. };
  7377.  
  7378. rpm-regulator-ldoa8 {
  7379. qcom,resource-name = "ldoa";
  7380. qcom,resource-id = <0x8>;
  7381. qcom,regulator-type = <0x0>;
  7382. qcom,hpm-min-load = <0x2710>;
  7383. compatible = "qcom,rpm-regulator-smd-resource";
  7384. status = "okay";
  7385.  
  7386. regulator-l8 {
  7387. regulator-name = "8941_l8";
  7388. qcom,set = <0x3>;
  7389. status = "okay";
  7390. compatible = "qcom,rpm-regulator-smd";
  7391. regulator-min-microvolt = <0x1b7740>;
  7392. regulator-max-microvolt = <0x1b7740>;
  7393. qcom,init-voltage = <0x1b7740>;
  7394. };
  7395. };
  7396.  
  7397. rpm-regulator-ldoa9 {
  7398. qcom,resource-name = "ldoa";
  7399. qcom,resource-id = <0x9>;
  7400. qcom,regulator-type = <0x0>;
  7401. qcom,hpm-min-load = <0x2710>;
  7402. compatible = "qcom,rpm-regulator-smd-resource";
  7403. status = "okay";
  7404.  
  7405. regulator-l9 {
  7406. regulator-name = "8941_l9";
  7407. qcom,set = <0x3>;
  7408. status = "okay";
  7409. compatible = "qcom,rpm-regulator-smd";
  7410. regulator-min-microvolt = <0x1b7740>;
  7411. regulator-max-microvolt = <0x2d0370>;
  7412. qcom,init-voltage = <0x2d0370>;
  7413. };
  7414. };
  7415.  
  7416. rpm-regulator-ldoa10 {
  7417. qcom,resource-name = "ldoa";
  7418. qcom,resource-id = <0xa>;
  7419. qcom,regulator-type = <0x0>;
  7420. qcom,hpm-min-load = <0x2710>;
  7421. compatible = "qcom,rpm-regulator-smd-resource";
  7422. status = "okay";
  7423.  
  7424. regulator-l10 {
  7425. regulator-name = "8941_l10";
  7426. qcom,set = <0x3>;
  7427. status = "okay";
  7428. compatible = "qcom,rpm-regulator-smd";
  7429. regulator-min-microvolt = <0x1b7740>;
  7430. regulator-max-microvolt = <0x2d0370>;
  7431. qcom,init-voltage = <0x2d0370>;
  7432. };
  7433. };
  7434.  
  7435. rpm-regulator-ldoa11 {
  7436. qcom,resource-name = "ldoa";
  7437. qcom,resource-id = <0xb>;
  7438. qcom,regulator-type = <0x0>;
  7439. qcom,hpm-min-load = <0x2710>;
  7440. compatible = "qcom,rpm-regulator-smd-resource";
  7441. status = "okay";
  7442.  
  7443. regulator-l11 {
  7444. regulator-name = "8941_l11";
  7445. qcom,set = <0x3>;
  7446. status = "okay";
  7447. compatible = "qcom,rpm-regulator-smd";
  7448. regulator-min-microvolt = <0x12b128>;
  7449. regulator-max-microvolt = <0x149970>;
  7450. qcom,init-voltage = <0x13d620>;
  7451. linux,phandle = <0x6d>;
  7452. phandle = <0x6d>;
  7453. };
  7454. };
  7455.  
  7456. rpm-regulator-ldoa12 {
  7457. qcom,resource-name = "ldoa";
  7458. qcom,resource-id = <0xc>;
  7459. qcom,regulator-type = <0x0>;
  7460. qcom,hpm-min-load = <0x2710>;
  7461. compatible = "qcom,rpm-regulator-smd-resource";
  7462. status = "okay";
  7463.  
  7464. regulator-l12 {
  7465. regulator-name = "8941_l12";
  7466. qcom,set = <0x3>;
  7467. status = "okay";
  7468. compatible = "qcom,rpm-regulator-smd";
  7469. regulator-min-microvolt = <0x1b7740>;
  7470. regulator-max-microvolt = <0x1b7740>;
  7471. linux,phandle = <0x2>;
  7472. phandle = <0x2>;
  7473. };
  7474.  
  7475. regulator-l12-ao {
  7476. regulator-name = "8941_l12_ao";
  7477. qcom,set = <0x1>;
  7478. regulator-min-microvolt = <0x1b7740>;
  7479. regulator-max-microvolt = <0x1b7740>;
  7480. status = "okay";
  7481. compatible = "qcom,rpm-regulator-smd";
  7482. linux,phandle = <0x5f>;
  7483. phandle = <0x5f>;
  7484. };
  7485. };
  7486.  
  7487. rpm-regulator-ldoa13 {
  7488. qcom,resource-name = "ldoa";
  7489. qcom,resource-id = <0xd>;
  7490. qcom,regulator-type = <0x0>;
  7491. qcom,hpm-min-load = <0x2710>;
  7492. compatible = "qcom,rpm-regulator-smd-resource";
  7493. status = "okay";
  7494.  
  7495. regulator-l13 {
  7496. regulator-name = "8941_l13";
  7497. qcom,set = <0x3>;
  7498. status = "okay";
  7499. compatible = "qcom,rpm-regulator-smd";
  7500. regulator-min-microvolt = <0x1b7740>;
  7501. regulator-max-microvolt = <0x2d0370>;
  7502. qcom,init-voltage = <0x2d0370>;
  7503. linux,phandle = <0x11>;
  7504. phandle = <0x11>;
  7505. };
  7506. };
  7507.  
  7508. rpm-regulator-ldoa14 {
  7509. qcom,resource-name = "ldoa";
  7510. qcom,resource-id = <0xe>;
  7511. qcom,regulator-type = <0x0>;
  7512. qcom,hpm-min-load = <0x2710>;
  7513. compatible = "qcom,rpm-regulator-smd-resource";
  7514. status = "okay";
  7515.  
  7516. regulator-l14 {
  7517. regulator-name = "8941_l14";
  7518. qcom,set = <0x3>;
  7519. status = "okay";
  7520. compatible = "qcom,rpm-regulator-smd";
  7521. regulator-min-microvolt = <0x1b7740>;
  7522. regulator-max-microvolt = <0x1b7740>;
  7523. qcom,init-voltage = <0x1b7740>;
  7524. };
  7525. };
  7526.  
  7527. rpm-regulator-ldoa15 {
  7528. qcom,resource-name = "ldoa";
  7529. qcom,resource-id = <0xf>;
  7530. qcom,regulator-type = <0x0>;
  7531. qcom,hpm-min-load = <0x2710>;
  7532. compatible = "qcom,rpm-regulator-smd-resource";
  7533. status = "okay";
  7534.  
  7535. regulator-l15 {
  7536. regulator-name = "8941_l15";
  7537. qcom,set = <0x3>;
  7538. status = "okay";
  7539. compatible = "qcom,rpm-regulator-smd";
  7540. regulator-min-microvolt = <0x1f47d0>;
  7541. regulator-max-microvolt = <0x1f47d0>;
  7542. qcom,init-voltage = <0x1f47d0>;
  7543. };
  7544. };
  7545.  
  7546. rpm-regulator-ldoa16 {
  7547. qcom,resource-name = "ldoa";
  7548. qcom,resource-id = <0x10>;
  7549. qcom,regulator-type = <0x0>;
  7550. qcom,hpm-min-load = <0x2710>;
  7551. compatible = "qcom,rpm-regulator-smd-resource";
  7552. status = "okay";
  7553.  
  7554. regulator-l16 {
  7555. regulator-name = "8941_l16";
  7556. qcom,set = <0x3>;
  7557. status = "okay";
  7558. compatible = "qcom,rpm-regulator-smd";
  7559. regulator-min-microvolt = <0x2932e0>;
  7560. regulator-max-microvolt = <0x2932e0>;
  7561. qcom,init-voltage = <0x2932e0>;
  7562. };
  7563. };
  7564.  
  7565. rpm-regulator-ldoa17 {
  7566. qcom,resource-name = "ldoa";
  7567. qcom,resource-id = <0x11>;
  7568. qcom,regulator-type = <0x0>;
  7569. qcom,hpm-min-load = <0x2710>;
  7570. compatible = "qcom,rpm-regulator-smd-resource";
  7571. status = "okay";
  7572.  
  7573. regulator-l17 {
  7574. regulator-name = "8941_l17";
  7575. qcom,set = <0x3>;
  7576. status = "okay";
  7577. compatible = "qcom,rpm-regulator-smd";
  7578. regulator-min-microvolt = <0x2b7cd0>;
  7579. regulator-max-microvolt = <0x2b7cd0>;
  7580. qcom,init-voltage = <0x2b7cd0>;
  7581. linux,phandle = <0x7>;
  7582. phandle = <0x7>;
  7583. };
  7584. };
  7585.  
  7586. rpm-regulator-ldoa18 {
  7587. qcom,resource-name = "ldoa";
  7588. qcom,resource-id = <0x12>;
  7589. qcom,regulator-type = <0x0>;
  7590. qcom,hpm-min-load = <0x2710>;
  7591. compatible = "qcom,rpm-regulator-smd-resource";
  7592. status = "okay";
  7593.  
  7594. regulator-l18 {
  7595. regulator-name = "8941_l18";
  7596. qcom,set = <0x3>;
  7597. status = "okay";
  7598. compatible = "qcom,rpm-regulator-smd";
  7599. regulator-min-microvolt = <0x2b7cd0>;
  7600. regulator-max-microvolt = <0x2b7cd0>;
  7601. qcom,init-voltage = <0x2b7cd0>;
  7602. linux,phandle = <0x4e>;
  7603. phandle = <0x4e>;
  7604. };
  7605. };
  7606.  
  7607. rpm-regulator-ldoa19 {
  7608. qcom,resource-name = "ldoa";
  7609. qcom,resource-id = <0x13>;
  7610. qcom,regulator-type = <0x0>;
  7611. qcom,hpm-min-load = <0x2710>;
  7612. compatible = "qcom,rpm-regulator-smd-resource";
  7613. status = "okay";
  7614.  
  7615. regulator-l19 {
  7616. regulator-name = "8941_l19";
  7617. qcom,set = <0x3>;
  7618. status = "okay";
  7619. compatible = "qcom,rpm-regulator-smd";
  7620. regulator-min-microvolt = <0x2c4020>;
  7621. regulator-max-microvolt = <0x331df0>;
  7622. qcom,init-voltage = <0x2c4020>;
  7623. linux,phandle = <0x6e>;
  7624. phandle = <0x6e>;
  7625. };
  7626. };
  7627.  
  7628. rpm-regulator-ldoa20 {
  7629. qcom,resource-name = "ldoa";
  7630. qcom,resource-id = <0x14>;
  7631. qcom,regulator-type = <0x0>;
  7632. qcom,hpm-min-load = <0x2710>;
  7633. compatible = "qcom,rpm-regulator-smd-resource";
  7634. status = "okay";
  7635.  
  7636. regulator-l20 {
  7637. regulator-name = "8941_l20";
  7638. qcom,set = <0x3>;
  7639. status = "okay";
  7640. compatible = "qcom,rpm-regulator-smd";
  7641. regulator-min-microvolt = <0x2d0370>;
  7642. regulator-max-microvolt = <0x2d0370>;
  7643. qcom,init-voltage = <0x2d0370>;
  7644. linux,phandle = <0x43>;
  7645. phandle = <0x43>;
  7646. };
  7647. };
  7648.  
  7649. rpm-regulator-ldoa21 {
  7650. qcom,resource-name = "ldoa";
  7651. qcom,resource-id = <0x15>;
  7652. qcom,regulator-type = <0x0>;
  7653. qcom,hpm-min-load = <0x2710>;
  7654. compatible = "qcom,rpm-regulator-smd-resource";
  7655. status = "okay";
  7656.  
  7657. regulator-l21 {
  7658. regulator-name = "8941_l21";
  7659. qcom,set = <0x3>;
  7660. status = "okay";
  7661. compatible = "qcom,rpm-regulator-smd";
  7662. regulator-min-microvolt = <0x2d0370>;
  7663. regulator-max-microvolt = <0x2d0370>;
  7664. qcom,init-voltage = <0x2d0370>;
  7665. linux,phandle = <0x10>;
  7666. phandle = <0x10>;
  7667. };
  7668. };
  7669.  
  7670. rpm-regulator-ldoa22 {
  7671. qcom,resource-name = "ldoa";
  7672. qcom,resource-id = <0x16>;
  7673. qcom,regulator-type = <0x0>;
  7674. qcom,hpm-min-load = <0x2710>;
  7675. compatible = "qcom,rpm-regulator-smd-resource";
  7676. status = "okay";
  7677.  
  7678. regulator-l22 {
  7679. regulator-name = "8941_l22";
  7680. qcom,set = <0x3>;
  7681. status = "okay";
  7682. compatible = "qcom,rpm-regulator-smd";
  7683. regulator-min-microvolt = <0x2dc6c0>;
  7684. regulator-max-microvolt = <0x2dc6c0>;
  7685. qcom,init-voltage = <0x2dc6c0>;
  7686. linux,phandle = <0xd>;
  7687. phandle = <0xd>;
  7688. };
  7689. };
  7690.  
  7691. rpm-regulator-ldoa23 {
  7692. qcom,resource-name = "ldoa";
  7693. qcom,resource-id = <0x17>;
  7694. qcom,regulator-type = <0x0>;
  7695. qcom,hpm-min-load = <0x2710>;
  7696. compatible = "qcom,rpm-regulator-smd-resource";
  7697. status = "okay";
  7698.  
  7699. regulator-l23 {
  7700. regulator-name = "8941_l23";
  7701. qcom,set = <0x3>;
  7702. status = "okay";
  7703. compatible = "qcom,rpm-regulator-smd";
  7704. regulator-min-microvolt = <0x2dc6c0>;
  7705. regulator-max-microvolt = <0x2dc6c0>;
  7706. qcom,init-voltage = <0x2dc6c0>;
  7707. linux,phandle = <0xc>;
  7708. phandle = <0xc>;
  7709. };
  7710. };
  7711.  
  7712. rpm-regulator-ldoa24 {
  7713. qcom,resource-name = "ldoa";
  7714. qcom,resource-id = <0x18>;
  7715. qcom,regulator-type = <0x0>;
  7716. qcom,hpm-min-load = <0x2710>;
  7717. compatible = "qcom,rpm-regulator-smd-resource";
  7718. status = "okay";
  7719.  
  7720. regulator-l24 {
  7721. regulator-name = "8941_l24";
  7722. qcom,set = <0x3>;
  7723. status = "okay";
  7724. compatible = "qcom,rpm-regulator-smd";
  7725. regulator-min-microvolt = <0x2eebb8>;
  7726. regulator-max-microvolt = <0x2eebb8>;
  7727. qcom,init-voltage = <0x2eebb8>;
  7728. linux,phandle = <0x42>;
  7729. phandle = <0x42>;
  7730. };
  7731. };
  7732.  
  7733. rpm-regulator-vsa1 {
  7734. qcom,resource-name = "vsa";
  7735. qcom,resource-id = <0x1>;
  7736. qcom,regulator-type = <0x2>;
  7737. compatible = "qcom,rpm-regulator-smd-resource";
  7738. status = "okay";
  7739.  
  7740. regulator-lvs1 {
  7741. regulator-name = "8941_lvs1";
  7742. qcom,set = <0x3>;
  7743. status = "okay";
  7744. compatible = "qcom,rpm-regulator-smd";
  7745. linux,phandle = <0x57>;
  7746. phandle = <0x57>;
  7747. };
  7748. };
  7749.  
  7750. rpm-regulator-vsa2 {
  7751. qcom,resource-name = "vsa";
  7752. qcom,resource-id = <0x2>;
  7753. qcom,regulator-type = <0x2>;
  7754. compatible = "qcom,rpm-regulator-smd-resource";
  7755. status = "okay";
  7756.  
  7757. regulator-lvs2 {
  7758. regulator-name = "8941_lvs2";
  7759. qcom,set = <0x3>;
  7760. status = "okay";
  7761. compatible = "qcom,rpm-regulator-smd";
  7762. };
  7763. };
  7764.  
  7765. rpm-regulator-vsa3 {
  7766. qcom,resource-name = "vsa";
  7767. qcom,resource-id = <0x3>;
  7768. qcom,regulator-type = <0x2>;
  7769. compatible = "qcom,rpm-regulator-smd-resource";
  7770. status = "okay";
  7771.  
  7772. regulator-lvs3 {
  7773. regulator-name = "8941_lvs3";
  7774. qcom,set = <0x3>;
  7775. status = "okay";
  7776. compatible = "qcom,rpm-regulator-smd";
  7777. linux,phandle = <0x8>;
  7778. phandle = <0x8>;
  7779. };
  7780. };
  7781.  
  7782. rpm-regulator-vsa4 {
  7783. qcom,resource-name = "vsa";
  7784. qcom,resource-id = <0x4>;
  7785. qcom,regulator-type = <0x2>;
  7786. compatible = "qcom,rpm-regulator-smd-resource";
  7787. status = "disabled";
  7788.  
  7789. regulator-mvs1 {
  7790. regulator-name = "8941_mvs1";
  7791. qcom,set = <0x3>;
  7792. status = "disabled";
  7793. compatible = "qcom,rpm-regulator-smd";
  7794. };
  7795. };
  7796.  
  7797. rpm-regulator-vsa5 {
  7798. qcom,resource-name = "vsa";
  7799. qcom,resource-id = <0x5>;
  7800. qcom,regulator-type = <0x2>;
  7801. compatible = "qcom,rpm-regulator-smd-resource";
  7802. status = "disabled";
  7803.  
  7804. regulator-mvs2 {
  7805. regulator-name = "8941_mvs2";
  7806. qcom,set = <0x3>;
  7807. status = "disabled";
  7808. compatible = "qcom,rpm-regulator-smd";
  7809. };
  7810. };
  7811. };
  7812.  
  7813. qcom,msm-rng@f9bff000 {
  7814. compatible = "qcom,msm-rng";
  7815. reg = <0xf9bff000 0x200>;
  7816. qcom,msm-bus,name = "msm-rng-noc";
  7817. qcom,msm-bus,num-cases = <0x2>;
  7818. qcom,msm-bus,num-paths = <0x1>;
  7819. qcom,msm-bus,vectors-KBps = <0x58 0x26a 0x0 0x0 0x58 0x26a 0x0 0x320>;
  7820. };
  7821.  
  7822. qcom,qseecom@7b00000 {
  7823. compatible = "qcom,qseecom";
  7824. reg = <0x7b00000 0x500000>;
  7825. reg-names = "secapp-region";
  7826. qcom,disk-encrypt-pipe-pair = <0x2>;
  7827. qcom,file-encrypt-pipe-pair = <0x0>;
  7828. qcom,hlos-ce-hw-instance = <0x1>;
  7829. qcom,qsee-ce-hw-instance = <0x0>;
  7830. qcom,support-bus-scaling;
  7831. qcom,msm-bus,name = "qseecom-noc";
  7832. qcom,msm-bus,num-cases = <0x4>;
  7833. qcom,msm-bus,num-paths = <0x1>;
  7834. qcom,support-fde;
  7835. qcom,support-pfe;
  7836. qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x0 0x0 0x37 0x200 0x1d4c0 0x124f80 0x37 0x200 0x60180 0x3c0f00>;
  7837. };
  7838.  
  7839. qcom,wdt@f9017000 {
  7840. compatible = "qcom,msm-watchdog";
  7841. reg = <0xf9017000 0x1000>;
  7842. interrupts = <0x0 0x3 0x0 0x0 0x4 0x0>;
  7843. qcom,bark-time = <0x2af8>;
  7844. qcom,pet-time = <0x2710>;
  7845. qcom,ipi-ping;
  7846. };
  7847.  
  7848. qcom,tz-log@fe805720 {
  7849. compatible = "qcom,tz-log";
  7850. reg = <0xfe805720 0x1000>;
  7851. };
  7852.  
  7853. qcom,venus@fdce0000 {
  7854. compatible = "qcom,pil-venus";
  7855. reg = <0xfdce0000 0x4000 0xfdc80000 0x400>;
  7856. reg-names = "wrapper_base", "vbif_base";
  7857. vdd-supply = <0x3c>;
  7858. qcom,firmware-name = "venus";
  7859. };
  7860.  
  7861. qcom,cache_erp@f9012000 {
  7862. reg = <0xf9012000 0x80 0xf9089000 0x80 0xf9099000 0x80 0xf90a9000 0x80 0xf90b9000 0x80 0xf9088000 0x40 0xf9098000 0x40 0xf90a8000 0x40 0xf90b8000 0x40>;
  7863. reg-names = "l2_saw", "krait0_saw", "krait1_saw", "krait2_saw", "krait3_saw", "krait0_acs", "krait1_acs", "krait2_acs", "krait3_acs";
  7864. compatible = "qcom,cache_erp";
  7865. interrupts = <0x1 0x9 0x0 0x0 0x2 0x0>;
  7866. interrupt-names = "l1_irq", "l2_irq";
  7867. };
  7868.  
  7869. qcom,cache_dump {
  7870. compatible = "qcom,cache_dump";
  7871. qcom,l1-dump-size = <0x100000>;
  7872. qcom,l2-dump-size = <0x500000>;
  7873. };
  7874.  
  7875. tsens@fc4a8000 {
  7876. compatible = "qcom,msm-tsens";
  7877. reg = <0xfc4a8000 0x2000 0xfc4bc000 0x1000>;
  7878. reg-names = "tsens_physical", "tsens_eeprom_physical";
  7879. interrupts = <0x0 0xb8 0x0>;
  7880. qcom,sensors = <0xb>;
  7881. qcom,slope = <0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80>;
  7882. qcom,calib-mode = "fuse_map1";
  7883. };
  7884.  
  7885. jtagfuse@fc4be024 {
  7886. compatible = "qcom,jtag-fuse";
  7887. reg = <0xfc4be024 0x8>;
  7888. reg-names = "fuse-base";
  7889. };
  7890.  
  7891. qcom,msm-rtb {
  7892. compatible = "qcom,msm-rtb";
  7893. qcom,memory-reservation-type = "EBI1";
  7894. qcom,memory-reservation-size = <0x100000>;
  7895. };
  7896.  
  7897. qcom,msm-contig-mem {
  7898. compatible = "qcom,msm-contig-mem";
  7899. qcom,memory-reservation-type = "EBI1";
  7900. qcom,memory-reservation-size = <0x280000>;
  7901. };
  7902.  
  7903. qcom,qcedev@fd440000 {
  7904. compatible = "qcom,qcedev";
  7905. reg = <0xfd440000 0x20000 0xfd444000 0x1b000>;
  7906. reg-names = "crypto-base", "crypto-bam-base";
  7907. interrupts = <0x0 0xec 0x0>;
  7908. qcom,bam-pipe-pair = <0x1>;
  7909. qcom,ce-hw-instance = <0x1>;
  7910. qcom,ce-device = <0x0>;
  7911. qcom,msm-bus,name = "qcedev-noc";
  7912. qcom,msm-bus,num-cases = <0x2>;
  7913. qcom,msm-bus,num-paths = <0x1>;
  7914. qcom,msm-bus,vectors-KBps = <0x38 0x200 0x0 0x0 0x38 0x200 0x3c0f00 0x60180>;
  7915. };
  7916.  
  7917. qcom,qcrypto@fd440000 {
  7918. compatible = "qcom,qcrypto";
  7919. reg = <0xfd440000 0x20000 0xfd444000 0x1b000>;
  7920. reg-names = "crypto-base", "crypto-bam-base";
  7921. interrupts = <0x0 0xec 0x0>;
  7922. qcom,bam-pipe-pair = <0x2>;
  7923. qcom,ce-hw-instance = <0x1>;
  7924. qcom,ce-device = <0x0>;
  7925. qcom,clk-mgmt-sus-res;
  7926. qcom,msm-bus,name = "qcrypto-noc";
  7927. qcom,msm-bus,num-cases = <0x2>;
  7928. qcom,msm-bus,num-paths = <0x1>;
  7929. qcom,use-sw-aes-cbc-ecb-ctr-algo;
  7930. qcom,use-sw-aes-xts-algo;
  7931. qcom,use-sw-ahash-algo;
  7932. qcom,msm-bus,vectors-KBps = <0x38 0x200 0x0 0x0 0x38 0x200 0x3c0f00 0x60180>;
  7933. };
  7934.  
  7935. qcom,qcrypto1@fd440000 {
  7936. compatible = "qcom,qcrypto";
  7937. reg = <0xfd440000 0x20000 0xfd444000 0x1b000>;
  7938. reg-names = "crypto-base", "crypto-bam-base";
  7939. interrupts = <0x0 0xec 0x0>;
  7940. qcom,bam-pipe-pair = <0x0>;
  7941. qcom,ce-hw-instance = <0x1>;
  7942. qcom,ce-device = <0x1>;
  7943. qcom,clk-mgmt-sus-res;
  7944. qcom,msm-bus,name = "qcrypto-noc";
  7945. qcom,msm-bus,num-cases = <0x2>;
  7946. qcom,msm-bus,num-paths = <0x1>;
  7947. qcom,use-sw-aes-cbc-ecb-ctr-algo;
  7948. qcom,use-sw-aes-xts-algo;
  7949. qcom,use-sw-ahash-algo;
  7950. qcom,msm-bus,vectors-KBps = <0x38 0x200 0x0 0x0 0x38 0x200 0x3c0f00 0x60180>;
  7951. };
  7952.  
  7953. qcom,usbbam@f9304000 {
  7954. compatible = "qcom,usb-bam-msm";
  7955. reg = <0xf9304000 0x5000 0xf9a44000 0x11000 0xf92f880c 0x4>;
  7956. reg-names = "ssusb", "hsusb", "qscratch_ram1_reg";
  7957. interrupts = <0x0 0x84 0x0 0x0 0x87 0x0>;
  7958. interrupt-names = "ssusb", "hsusb";
  7959. qcom,usb-bam-num-pipes = <0x10>;
  7960. qcom,usb-bam-fifo-baseaddr = <0xf9200000>;
  7961. qcom,ignore-core-reset-ack;
  7962. qcom,disable-clk-gating;
  7963.  
  7964. qcom,pipe0 {
  7965. label = "ssusb-qdss-in-0";
  7966. qcom,usb-bam-mem-type = <0x1>;
  7967. qcom,bam-type = <0x0>;
  7968. qcom,dir = <0x1>;
  7969. qcom,pipe-num = <0x0>;
  7970. qcom,peer-bam = <0x1>;
  7971. qcom,src-bam-physical-address = <0xfc37c000>;
  7972. qcom,src-bam-pipe-index = <0x0>;
  7973. qcom,dst-bam-physical-address = <0xf9304000>;
  7974. qcom,dst-bam-pipe-index = <0x2>;
  7975. qcom,data-fifo-offset = <0xf0000>;
  7976. qcom,data-fifo-size = <0x1800>;
  7977. qcom,descriptor-fifo-offset = <0xf4000>;
  7978. qcom,descriptor-fifo-size = <0x1400>;
  7979. qcom,reset-bam-on-connect;
  7980. };
  7981.  
  7982. qcom,pipe1 {
  7983. label = "hsusb-qdss-in-0";
  7984. qcom,usb-bam-mem-type = <0x1>;
  7985. qcom,bam-type = <0x1>;
  7986. qcom,dir = <0x1>;
  7987. qcom,pipe-num = <0x0>;
  7988. qcom,peer-bam = <0x1>;
  7989. qcom,src-bam-physical-address = <0xfc37c000>;
  7990. qcom,src-bam-pipe-index = <0x0>;
  7991. qcom,dst-bam-physical-address = <0xf9a44000>;
  7992. qcom,dst-bam-pipe-index = <0x2>;
  7993. qcom,data-fifo-offset = <0xf4000>;
  7994. qcom,data-fifo-size = <0x1000>;
  7995. qcom,descriptor-fifo-offset = <0xf5000>;
  7996. qcom,descriptor-fifo-size = <0x400>;
  7997. };
  7998. };
  7999.  
  8000. qcom,msm-thermal {
  8001. compatible = "qcom,msm-thermal";
  8002. qcom,sensor-id = <0x5>;
  8003. qcom,poll-ms = <0xfa>;
  8004. qcom,limit-temp = <0x3c>;
  8005. qcom,temp-hysteresis = <0xa>;
  8006. qcom,therm-reset-temp = <0x73>;
  8007. qcom,freq-step = <0x2>;
  8008. qcom,freq-control-mask = <0xf>;
  8009. qcom,core-limit-temp = <0x50>;
  8010. qcom,core-temp-hysteresis = <0xa>;
  8011. qcom,core-control-mask = <0xe>;
  8012. qcom,hotplug-temp = <0x6e>;
  8013. qcom,hotplug-temp-hysteresis = <0x14>;
  8014. qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor6", "tsens_tz_sensor7", "tsens_tz_sensor8";
  8015. qcom,freq-mitigation-temp = <0x6e>;
  8016. qcom,freq-mitigation-temp-hysteresis = <0x14>;
  8017. qcom,freq-mitigation-value = <0xea600>;
  8018. qcom,freq-mitigation-control-mask = <0x1>;
  8019. qcom,vdd-restriction-temp = <0x5>;
  8020. qcom,vdd-restriction-temp-hysteresis = <0xa>;
  8021. vdd-dig-supply = <0x6f>;
  8022. vdd-gfx-supply = <0x70>;
  8023.  
  8024. qcom,vdd-dig-rstr {
  8025. qcom,vdd-rstr-reg = "vdd-dig";
  8026. qcom,levels = <0x5 0x7 0x7>;
  8027. qcom,min-level = <0x1>;
  8028. };
  8029.  
  8030. qcom,vdd-gfx-rstr {
  8031. qcom,vdd-rstr-reg = "vdd-gfx";
  8032. qcom,levels = <0x5 0x7 0x7>;
  8033. qcom,min-level = <0x1>;
  8034. };
  8035.  
  8036. qcom,vdd-apps-rstr {
  8037. qcom,vdd-rstr-reg = "vdd-apps";
  8038. qcom,levels = <0x1cb600 0x1de200 0x229200>;
  8039. qcom,freq-req;
  8040. };
  8041. };
  8042.  
  8043. qcom,bam_dmux@fc834000 {
  8044. compatible = "qcom,bam_dmux";
  8045. reg = <0xfc834000 0x7000>;
  8046. interrupts = <0x0 0x1d 0x1>;
  8047. qcom,rx-ring-size = <0x40>;
  8048. };
  8049.  
  8050. qcom,msm-mem-hole {
  8051. compatible = "qcom,msm-mem-hole";
  8052. qcom,memblock-remove = <0x5a00000 0x7800000 0xfa00000 0x500000>;
  8053. };
  8054.  
  8055. uart@f995d000 {
  8056. compatible = "qcom,msm-hsuart-v14";
  8057. status = "ok";
  8058. reg = <0xf995d000 0x1000 0xf9944000 0x19000>;
  8059. reg-names = "core_mem", "bam_mem";
  8060. interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
  8061. #address-cells = <0x0>;
  8062. interrupt-parent = <0x71>;
  8063. interrupts = <0x0 0x1 0x2>;
  8064. #interrupt-cells = <0x1>;
  8065. interrupt-map-mask = <0xffffffff>;
  8066. interrupt-map = <0x0 0x1 0x0 0x71 0x0 0x1 0x1 0x0 0xef 0x0 0x2 0x5 0x2a 0x0>;
  8067. qcom,bam-tx-ep-pipe-index = <0x0>;
  8068. qcom,bam-rx-ep-pipe-index = <0x1>;
  8069. qcom,msm-bus,name = "uart7";
  8070. qcom,msm-bus,num-cases = <0x2>;
  8071. qcom,msm-bus,num-paths = <0x1>;
  8072. qcom,msm-bus,vectors-KBps = <0x54 0x200 0x0 0x0 0x54 0x200 0x1f4 0x320>;
  8073. linux,phandle = <0x71>;
  8074. phandle = <0x71>;
  8075. };
  8076.  
  8077. qcom,smem@fa00000 {
  8078. compatible = "qcom,smem";
  8079. reg = <0xfa00000 0x200000 0xf9011000 0x1000 0xfc428000 0x4000>;
  8080. reg-names = "smem", "irq-reg-base", "aux-mem1";
  8081.  
  8082. qcom,smd-modem {
  8083. compatible = "qcom,smd";
  8084. qcom,smd-edge = <0x0>;
  8085. qcom,smd-irq-offset = <0x8>;
  8086. qcom,smd-irq-bitmask = <0x1000>;
  8087. qcom,pil-string = "modem";
  8088. interrupts = <0x0 0x19 0x1>;
  8089. };
  8090.  
  8091. qcom,smsm-modem {
  8092. compatible = "qcom,smsm";
  8093. qcom,smsm-edge = <0x0>;
  8094. qcom,smsm-irq-offset = <0x8>;
  8095. qcom,smsm-irq-bitmask = <0x2000>;
  8096. interrupts = <0x0 0x1a 0x1>;
  8097. };
  8098.  
  8099. qcom,smd-adsp {
  8100. compatible = "qcom,smd";
  8101. qcom,smd-edge = <0x1>;
  8102. qcom,smd-irq-offset = <0x8>;
  8103. qcom,smd-irq-bitmask = <0x100>;
  8104. qcom,pil-string = "adsp";
  8105. interrupts = <0x0 0x9c 0x1>;
  8106. };
  8107.  
  8108. qcom,smsm-adsp {
  8109. compatible = "qcom,smsm";
  8110. qcom,smsm-edge = <0x1>;
  8111. qcom,smsm-irq-offset = <0x8>;
  8112. qcom,smsm-irq-bitmask = <0x200>;
  8113. interrupts = <0x0 0x9d 0x1>;
  8114. };
  8115.  
  8116. qcom,smd-wcnss {
  8117. compatible = "qcom,smd";
  8118. qcom,smd-edge = <0x6>;
  8119. qcom,smd-irq-offset = <0x8>;
  8120. qcom,smd-irq-bitmask = <0x20000>;
  8121. qcom,pil-string = "wcnss";
  8122. interrupts = <0x0 0x8e 0x1>;
  8123. };
  8124.  
  8125. qcom,smsm-wcnss {
  8126. compatible = "qcom,smsm";
  8127. qcom,smsm-edge = <0x6>;
  8128. qcom,smsm-irq-offset = <0x8>;
  8129. qcom,smsm-irq-bitmask = <0x80000>;
  8130. interrupts = <0x0 0x90 0x1>;
  8131. };
  8132.  
  8133. qcom,smd-rpm {
  8134. compatible = "qcom,smd";
  8135. qcom,smd-edge = <0xf>;
  8136. qcom,smd-irq-offset = <0x8>;
  8137. qcom,smd-irq-bitmask = <0x1>;
  8138. interrupts = <0x0 0xa8 0x1>;
  8139. qcom,irq-no-suspend;
  8140. };
  8141. };
  8142.  
  8143. qcom,bcl {
  8144. compatible = "qcom,bcl";
  8145. };
  8146.  
  8147. i2c@f9928000 {
  8148. cell-index = <0x3>;
  8149. compatible = "qcom,i2c-qup";
  8150. reg = <0xf9928000 0x1000>;
  8151. #address-cells = <0x1>;
  8152. #size-cells = <0x0>;
  8153. reg-names = "qup_phys_addr";
  8154. interrupts = <0x0 0x64 0x0>;
  8155. interrupt-names = "qup_err_intr";
  8156. qcom,i2c-bus-freq = <0x61a80>;
  8157. qcom,i2c-src-freq = <0x124f800>;
  8158. qcom,scl-gpio = <0x5 0x1e 0x0>;
  8159. qcom,sda-gpio = <0x5 0x1d 0x0>;
  8160. qcom,master-id = <0x56>;
  8161.  
  8162. nfc-nci@e {
  8163. compatible = "qcom,nfc-nci";
  8164. reg = <0xe>;
  8165. qcom,irq-gpio = <0x5 0x39 0x0>;
  8166. qcom,dis-gpio = <0x5 0xd 0x0>;
  8167. qcom,clk-src = "BBCLK2";
  8168. interrupt-parent = <0x5>;
  8169. interrupts = <0x39 0x0>;
  8170. qcom,clk-gpio = <0x2a 0x20 0x0>;
  8171. };
  8172. };
  8173.  
  8174. qcom,ssm {
  8175. compatible = "qcom,ssm";
  8176. qcom,channel-name = "SSM_RTR";
  8177. };
  8178.  
  8179. qcom,ipc-spinlock@fd484000 {
  8180. compatible = "qcom,ipc-spinlock-sfpb";
  8181. reg = <0xfd484000 0x400>;
  8182. qcom,num-locks = <0x8>;
  8183. };
  8184.  
  8185. qcom,ipc-spinlock@fa00000 {
  8186. compatible = "qcom,ipc-spinlock-ldrex";
  8187. reg = <0xfa00000 0x200000>;
  8188. status = "disable";
  8189. };
  8190.  
  8191. cpu-pmu {
  8192. compatible = "qcom,krait-pmu";
  8193. qcom,irq-is-percpu;
  8194. interrupts = <0x1 0x7 0xf00>;
  8195. };
  8196.  
  8197. l2-pmu {
  8198. compatible = "qcom,l2-pmu";
  8199. interrupts = <0x0 0x1 0x0>;
  8200. };
  8201.  
  8202. bimc_sharedmem {
  8203. compatible = "qcom,sharedmem-uio";
  8204. reg = <0xfc380000 0x100000>;
  8205. reg-names = "bimc";
  8206. };
  8207.  
  8208. qcom,smdtty {
  8209. compatible = "qcom,smdtty";
  8210.  
  8211. qcom,smdtty-apps-fm {
  8212. qcom,smdtty-remote = "wcnss";
  8213. qcom,smdtty-port-name = "APPS_FM";
  8214. };
  8215.  
  8216. smdtty-apps-riva-bt-acl {
  8217. qcom,smdtty-remote = "wcnss";
  8218. qcom,smdtty-port-name = "APPS_RIVA_BT_ACL";
  8219. };
  8220.  
  8221. qcom,smdtty-apps-riva-bt-cmd {
  8222. qcom,smdtty-remote = "wcnss";
  8223. qcom,smdtty-port-name = "APPS_RIVA_BT_CMD";
  8224. };
  8225.  
  8226. qcom,smdtty-mbalbridge {
  8227. qcom,smdtty-remote = "modem";
  8228. qcom,smdtty-port-name = "MBALBRIDGE";
  8229. };
  8230.  
  8231. smdtty-apps-riva-ant-cmd {
  8232. qcom,smdtty-remote = "wcnss";
  8233. qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD";
  8234. };
  8235.  
  8236. smdtty-apps-riva-ant-data {
  8237. qcom,smdtty-remote = "wcnss";
  8238. qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA";
  8239. };
  8240.  
  8241. qcom,smdtty-data1 {
  8242. qcom,smdtty-remote = "modem";
  8243. qcom,smdtty-port-name = "DATA1";
  8244. };
  8245.  
  8246. qcom,smdtty-data11 {
  8247. qcom,smdtty-remote = "modem";
  8248. qcom,smdtty-port-name = "DATA11";
  8249. };
  8250.  
  8251. qcom,smdtty-data21 {
  8252. qcom,smdtty-remote = "modem";
  8253. qcom,smdtty-port-name = "DATA21";
  8254. };
  8255.  
  8256. smdtty-gpsnmea {
  8257. qcom,smdtty-remote = "modem";
  8258. qcom,smdtty-port-name = "GPSNMEA";
  8259. };
  8260.  
  8261. smdtty-loopback {
  8262. qcom,smdtty-remote = "modem";
  8263. qcom,smdtty-port-name = "LOOPBACK";
  8264. qcom,smdtty-dev-name = "LOOPBACK_TTY";
  8265. };
  8266. };
  8267.  
  8268. qcom,avtimer {
  8269. compatible = "qcom,avtimer";
  8270. reg = <0xfe053008 0x4 0xfe05300c 0x4>;
  8271. reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
  8272. };
  8273.  
  8274. qcom,iommu@fda64000 {
  8275. compatible = "qcom,msm-smmu-v1";
  8276. #address-cells = <0x1>;
  8277. #size-cells = <0x1>;
  8278. ranges;
  8279. reg = <0xfda64000 0x10000>;
  8280. reg-names = "iommu_base";
  8281. interrupts = <0x0 0x43 0x0>;
  8282. qcom,needs-alt-core-clk;
  8283. label = "jpeg_iommu";
  8284. status = "ok";
  8285. qcom,msm-bus,name = "jpeg_ebi";
  8286. qcom,msm-bus,num-cases = <0x2>;
  8287. qcom,msm-bus,num-paths = <0x1>;
  8288. qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x0 0x0 0x3e 0x200 0x0 0x3e8>;
  8289. qcom,iommu-pmu-ngroups = <0x1>;
  8290. qcom,iommu-pmu-ncounters = <0x8>;
  8291. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8292. qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x20ac 0x215c 0x220c 0x2008 0x200c 0x2010 0x2014>;
  8293. qcom,iommu-bfb-data = <0xffff 0x0 0x4 0x4 0x0 0x0 0x10 0x50 0x0 0x2804 0x9614 0x0 0x0 0x0 0x0>;
  8294. vdd-supply = <0x4>;
  8295. qcom,iommu-enable-halt;
  8296.  
  8297. qcom,iommu-ctx@fda6c000 {
  8298. compatible = "qcom,msm-smmu-v1-ctx";
  8299. reg = <0xfda6c000 0x1000>;
  8300. interrupts = <0x0 0x46 0x0>;
  8301. qcom,iommu-ctx-sids = <0x0>;
  8302. label = "jpeg_enc0";
  8303. };
  8304.  
  8305. qcom,iommu-ctx@fda6d000 {
  8306. compatible = "qcom,msm-smmu-v1-ctx";
  8307. reg = <0xfda6d000 0x1000>;
  8308. interrupts = <0x0 0x46 0x0>;
  8309. qcom,iommu-ctx-sids = <0x1>;
  8310. label = "jpeg_enc1";
  8311. };
  8312.  
  8313. qcom,iommu-ctx@fda6e000 {
  8314. compatible = "qcom,msm-smmu-v1-ctx";
  8315. reg = <0xfda6e000 0x1000>;
  8316. interrupts = <0x0 0x46 0x0>;
  8317. qcom,iommu-ctx-sids = <0x2>;
  8318. label = "jpeg_dec";
  8319. };
  8320. };
  8321.  
  8322. qcom,iommu@fd928000 {
  8323. compatible = "qcom,msm-smmu-v1";
  8324. #address-cells = <0x1>;
  8325. #size-cells = <0x1>;
  8326. ranges;
  8327. reg = <0xfd928000 0x10000>;
  8328. reg-names = "iommu_base";
  8329. interrupts = <0x0 0x49 0x0>;
  8330. qcom,iommu-secure-id = <0x1>;
  8331. label = "mdp_iommu";
  8332. qcom,msm-bus,name = "mdp_ebi";
  8333. qcom,msm-bus,num-cases = <0x2>;
  8334. qcom,msm-bus,num-paths = <0x1>;
  8335. qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x3e8>;
  8336. status = "ok";
  8337. qcom,iommu-pmu-ngroups = <0x1>;
  8338. qcom,iommu-pmu-ncounters = <0x8>;
  8339. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8340. qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x2314 0x2394 0x2414 0x2008 0x200c 0x2010 0x2014 0x2018 0x201c 0x2020>;
  8341. qcom,iommu-bfb-data = <0xffffffff 0x0 0x4 0x10 0x0 0x6800 0x6221 0x16231 0x0 0x34 0x74 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
  8342. vdd-supply = <0x22>;
  8343. qcom,iommu-enable-halt;
  8344.  
  8345. qcom,iommu-ctx@fd930000 {
  8346. compatible = "qcom,msm-smmu-v1-ctx";
  8347. reg = <0xfd930000 0x1000>;
  8348. interrupts = <0x0 0x2f 0x0>;
  8349. qcom,iommu-ctx-sids = <0x0>;
  8350. label = "mdp_0";
  8351. };
  8352.  
  8353. qcom,iommu-ctx@fd931000 {
  8354. compatible = "qcom,msm-smmu-v1-ctx";
  8355. reg = <0xfd931000 0x1000>;
  8356. interrupts = <0x0 0x2f 0x0 0x0 0x2e 0x0>;
  8357. qcom,iommu-ctx-sids = <0x1>;
  8358. label = "mdp_1";
  8359. qcom,secure-context;
  8360. };
  8361.  
  8362. qcom,iommu-ctx@fd932000 {
  8363. compatible = "qcom,msm-smmu-v1-ctx";
  8364. reg = <0xfd932000 0x1000>;
  8365. interrupts = <0x0 0x2f 0x0 0x0 0x2e 0x0>;
  8366. qcom,iommu-ctx-sids;
  8367. label = "mdp_2";
  8368. qcom,secure-context;
  8369. };
  8370. };
  8371.  
  8372. qcom,iommu@fdc84000 {
  8373. compatible = "qcom,msm-smmu-v1";
  8374. #address-cells = <0x1>;
  8375. #size-cells = <0x1>;
  8376. ranges;
  8377. reg = <0xfdc84000 0x10000 0xfdce0004 0x4>;
  8378. reg-names = "iommu_base", "clk_base";
  8379. interrupts = <0x0 0x2d 0x0>;
  8380. qcom,iommu-secure-id = <0x0>;
  8381. qcom,needs-alt-core-clk;
  8382. label = "venus_iommu";
  8383. qcom,msm-bus,name = "venus_ebi";
  8384. qcom,msm-bus,num-cases = <0x2>;
  8385. qcom,msm-bus,num-paths = <0x1>;
  8386. qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x0 0x0 0x3f 0x200 0x0 0x3e8>;
  8387. status = "ok";
  8388. qcom,iommu-pmu-ngroups = <0x1>;
  8389. qcom,iommu-pmu-ncounters = <0x8>;
  8390. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8391. qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x2314 0x2394 0x2414 0x2008 0x200c 0x2010 0x2014 0x2018 0x201c 0x2020 0x2024 0x2028 0x202c 0x2030 0x2034 0x2038>;
  8392. qcom,iommu-bfb-data = <0xffffffff 0xffffffff 0x4 0x8 0x0 0x13205 0x4000 0x14020 0x0 0x94 0x114 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
  8393. vdd-supply = <0x3c>;
  8394. qcom,iommu-enable-halt;
  8395.  
  8396. qcom,iommu-ctx@fdc8c000 {
  8397. compatible = "qcom,msm-smmu-v1-ctx";
  8398. reg = <0xfdc8c000 0x1000>;
  8399. interrupts = <0x0 0x2a 0x0>;
  8400. qcom,iommu-ctx-sids = <0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
  8401. label = "venus_ns";
  8402. linux,phandle = <0x72>;
  8403. phandle = <0x72>;
  8404. };
  8405.  
  8406. qcom,iommu-ctx@fdc8d000 {
  8407. compatible = "qcom,msm-smmu-v1-ctx";
  8408. reg = <0xfdc8d000 0x1000>;
  8409. interrupts = <0x0 0x2a 0x0 0x0 0x2b 0x0>;
  8410. qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84>;
  8411. label = "venus_sec_bitstream";
  8412. qcom,secure-context;
  8413. linux,phandle = <0x73>;
  8414. phandle = <0x73>;
  8415. };
  8416.  
  8417. qcom,iommu-ctx@fdc8e000 {
  8418. compatible = "qcom,msm-smmu-v1-ctx";
  8419. reg = <0xfdc8e000 0x1000>;
  8420. interrupts = <0x0 0x2a 0x0 0x0 0x2b 0x0>;
  8421. qcom,iommu-ctx-sids = <0xc0 0xc6>;
  8422. label = "venus_fw";
  8423. qcom,secure-context;
  8424. };
  8425.  
  8426. qcom,iommu-ctx@fdc8f000 {
  8427. compatible = "qcom,msm-smmu-v1-ctx";
  8428. reg = <0xfdc8f000 0x1000>;
  8429. interrupts = <0x0 0x2a 0x0 0x0 0x2b 0x0>;
  8430. qcom,iommu-ctx-sids = <0x85>;
  8431. label = "venus_sec_pixel";
  8432. qcom,secure-context;
  8433. linux,phandle = <0x74>;
  8434. phandle = <0x74>;
  8435. };
  8436.  
  8437. qcom,iommu-ctx@fdc90000 {
  8438. compatible = "qcom,msm-smmu-v1-ctx";
  8439. reg = <0xfdc90000 0x1000>;
  8440. interrupts = <0x0 0x2a 0x0 0x0 0x2b 0x0>;
  8441. qcom,iommu-ctx-sids = <0x87 0xa0>;
  8442. label = "venus_sec_non_pixel";
  8443. qcom,secure-context;
  8444. linux,phandle = <0x75>;
  8445. phandle = <0x75>;
  8446. };
  8447. };
  8448.  
  8449. qcom,iommu@fdb10000 {
  8450. compatible = "qcom,msm-smmu-v1";
  8451. #address-cells = <0x1>;
  8452. #size-cells = <0x1>;
  8453. ranges;
  8454. reg = <0xfdb10000 0x10000>;
  8455. reg-names = "iommu_base";
  8456. interrupts = <0x0 0x26 0x0>;
  8457. label = "kgsl_iommu";
  8458. qcom,msm-bus,name = "kgsl_ebi";
  8459. qcom,msm-bus,num-cases = <0x2>;
  8460. qcom,msm-bus,num-paths = <0x1>;
  8461. qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x0 0x0 0x1a 0x200 0x0 0x3e8>;
  8462. status = "ok";
  8463. qcom,iommu-pmu-ngroups = <0x1>;
  8464. qcom,iommu-pmu-ncounters = <0x8>;
  8465. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8466. qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x2314 0x2394 0x2414 0x2008>;
  8467. qcom,iommu-bfb-data = <0x3 0x0 0x4 0x10 0x0 0x0 0x0 0x20 0x0 0x1 0x81 0x0>;
  8468. vdd-supply = <0x1e>;
  8469. qcom,alt-vdd-supply = <0x1f>;
  8470. qcom,iommu-enable-halt;
  8471. qcom,needs-alt-core-clk;
  8472. linux,phandle = <0x20>;
  8473. phandle = <0x20>;
  8474.  
  8475. qcom,iommu-ctx@fdb18000 {
  8476. compatible = "qcom,msm-smmu-v1-ctx";
  8477. reg = <0xfdb18000 0x1000>;
  8478. interrupts = <0x0 0xf1 0x0>;
  8479. qcom,iommu-ctx-sids = <0x0>;
  8480. label = "gfx3d_user";
  8481. };
  8482.  
  8483. qcom,iommu-ctx@fdb19000 {
  8484. compatible = "qcom,msm-smmu-v1-ctx";
  8485. reg = <0xfdb19000 0x1000>;
  8486. interrupts = <0x0 0xf1 0x0>;
  8487. qcom,iommu-ctx-sids = <0x1>;
  8488. label = "gfx3d_priv";
  8489. };
  8490.  
  8491. qcom,iommu-ctx@fdb1a000 {
  8492. compatible = "qcom,msm-smmu-v1-ctx";
  8493. reg = <0xfdb1a000 0x1000>;
  8494. interrupts = <0x0 0xf1 0x0>;
  8495. qcom,iommu-ctx-sids = <0x2>;
  8496. label = "gfx3d_spare";
  8497. };
  8498. };
  8499.  
  8500. qcom,iommu@fda44000 {
  8501. compatible = "qcom,msm-smmu-v1";
  8502. #address-cells = <0x1>;
  8503. #size-cells = <0x1>;
  8504. ranges;
  8505. reg = <0xfda44000 0x10000>;
  8506. reg-names = "iommu_base";
  8507. interrupts = <0x0 0x3e 0x0>;
  8508. qcom,needs-alt-core-clk;
  8509. label = "vfe_iommu";
  8510. qcom,msm-bus,name = "vfe_ebi";
  8511. qcom,msm-bus,num-cases = <0x2>;
  8512. qcom,msm-bus,num-paths = <0x1>;
  8513. qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x0 0x0 0x1d 0x200 0x0 0x3e8>;
  8514. status = "ok";
  8515. qcom,iommu-pmu-ngroups = <0x1>;
  8516. qcom,iommu-pmu-ncounters = <0x8>;
  8517. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8518. qcom,iommu-bfb-regs = <0x204c 0x2050 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x20ac 0x215c 0x220c 0x2008 0x200c 0x2010 0x2014 0x2018 0x201c 0x2020>;
  8519. qcom,iommu-bfb-data = <0xffffffff 0x0 0x4 0x8 0x0 0x0 0x20 0x78 0x0 0x3c08 0xb41e 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
  8520. vdd-supply = <0x3>;
  8521. qcom,iommu-enable-halt;
  8522.  
  8523. qcom,iommu-ctx@fda4c000 {
  8524. compatible = "qcom,msm-smmu-v1-ctx";
  8525. reg = <0xfda4c000 0x1000>;
  8526. interrupts = <0x0 0x41 0x0>;
  8527. qcom,iommu-ctx-sids = <0x0>;
  8528. label = "vfe0";
  8529. };
  8530.  
  8531. qcom,iommu-ctx@fda4d000 {
  8532. compatible = "qcom,msm-smmu-v1-ctx";
  8533. reg = <0xfda4d000 0x1000>;
  8534. interrupts = <0x0 0x41 0x0>;
  8535. qcom,iommu-ctx-sids = <0x1>;
  8536. label = "vfe1";
  8537. };
  8538.  
  8539. qcom,iommu-ctx@fda4e000 {
  8540. compatible = "qcom,msm-smmu-v1-ctx";
  8541. reg = <0xfda4e000 0x1000>;
  8542. interrupts = <0x0 0x41 0x0>;
  8543. qcom,iommu-ctx-sids = <0x2>;
  8544. label = "cpp";
  8545. };
  8546. };
  8547.  
  8548. qcom,iommu@f9bc4000 {
  8549. compatible = "qcom,msm-smmu-v1";
  8550. #address-cells = <0x1>;
  8551. #size-cells = <0x1>;
  8552. ranges;
  8553. reg = <0xf9bc4000 0x10000>;
  8554. reg-names = "iommu_base";
  8555. interrupts = <0x0 0x99 0x0>;
  8556. label = "copss_iommu";
  8557. qcom,msm-bus,name = "copss_ebi";
  8558. qcom,msm-bus,num-cases = <0x2>;
  8559. qcom,msm-bus,num-paths = <0x1>;
  8560. qcom,msm-bus,vectors-KBps = <0x58 0x200 0x0 0x0 0x58 0x200 0x0 0x3e8>;
  8561. status = "disabled";
  8562. qcom,iommu-pmu-ngroups = <0x1>;
  8563. qcom,iommu-pmu-ncounters = <0x8>;
  8564. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8565. qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>;
  8566. qcom,iommu-bfb-data = <0x3 0x4 0x4 0x0 0x0 0x0 0x1 0x0 0x0 0x40 0x44 0x0 0x0>;
  8567. qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>;
  8568. qcom,iommu-lpae-bfb-data = <0x3 0x0 0x4 0x4 0x0 0x5 0x0 0x1 0x0 0x0 0x40 0x44 0x0>;
  8569.  
  8570. qcom,iommu-ctx@f9bcc000 {
  8571. compatible = "qcom,msm-smmu-v1-ctx";
  8572. reg = <0xf9bcc000 0x1000>;
  8573. interrupts = <0x0 0x8e 0x0>;
  8574. qcom,iommu-ctx-sids = <0x0>;
  8575. label = "copss_cb_0";
  8576. };
  8577.  
  8578. qcom,iommu-ctx@f9bcd000 {
  8579. compatible = "qcom,msm-smmu-v1-ctx";
  8580. reg = <0xf9bcd000 0x1000>;
  8581. interrupts = <0x0 0x8e 0x0>;
  8582. qcom,iommu-ctx-sids = <0x1>;
  8583. label = "copss_cb_1";
  8584. };
  8585.  
  8586. qcom,iommu-ctx@f9bce000 {
  8587. compatible = "qcom,msm-smmu-v1-ctx";
  8588. reg = <0xf9bce000 0x1000>;
  8589. interrupts = <0x0 0x8e 0x0>;
  8590. qcom,iommu-ctx-sids = <0x2>;
  8591. label = "copss_cb_2";
  8592. };
  8593.  
  8594. qcom,iommu-ctx@f9bcf000 {
  8595. compatible = "qcom,msm-smmu-v1-ctx";
  8596. reg = <0xf9bcf000 0x1000>;
  8597. interrupts = <0x0 0x8e 0x0>;
  8598. qcom,iommu-ctx-sids = <0x3>;
  8599. label = "copss_cb_3";
  8600. };
  8601.  
  8602. qcom,iommu-ctx@f9bd0000 {
  8603. compatible = "qcom,msm-smmu-v1-ctx";
  8604. reg = <0xf9bd0000 0x1000>;
  8605. interrupts = <0x0 0x8e 0x0>;
  8606. qcom,iommu-ctx-sids = <0x4>;
  8607. label = "copss_cb_4";
  8608. };
  8609.  
  8610. qcom,iommu-ctx@f9bd1000 {
  8611. compatible = "qcom,msm-smmu-v1-ctx";
  8612. reg = <0xf9bd1000 0x1000>;
  8613. interrupts = <0x0 0x8e 0x0>;
  8614. qcom,iommu-ctx-sids = <0x5>;
  8615. label = "copss_cb_5";
  8616. };
  8617.  
  8618. qcom,iommu-ctx@f9bd2000 {
  8619. compatible = "qcom,msm-smmu-v1-ctx";
  8620. reg = <0xf9bd2000 0x1000>;
  8621. interrupts = <0x0 0x8e 0x0>;
  8622. qcom,iommu-ctx-sids = <0x6>;
  8623. label = "copss_cb_6";
  8624. };
  8625.  
  8626. qcom,iommu-ctx@f9bd3000 {
  8627. compatible = "qcom,msm-smmu-v1-ctx";
  8628. reg = <0xf9bd3000 0x1000>;
  8629. interrupts = <0x0 0x8e 0x0>;
  8630. qcom,iommu-ctx-sids = <0x7>;
  8631. label = "copss_cb_7";
  8632. };
  8633. };
  8634.  
  8635. qcom,iommu@fdee4000 {
  8636. compatible = "qcom,msm-smmu-v1";
  8637. #address-cells = <0x1>;
  8638. #size-cells = <0x1>;
  8639. ranges;
  8640. reg = <0xfdee4000 0x10000>;
  8641. reg-names = "iommu_base";
  8642. interrupts = <0x0 0x93 0x0>;
  8643. label = "vpu_iommu";
  8644. qcom,msm-bus,name = "vpu_ebi";
  8645. qcom,msm-bus,num-cases = <0x2>;
  8646. qcom,msm-bus,num-paths = <0x1>;
  8647. qcom,msm-bus,vectors-KBps = <0x5d 0x200 0x0 0x0 0x5d 0x200 0x0 0x3e8>;
  8648. status = "disabled";
  8649. qcom,iommu-pmu-ngroups = <0x1>;
  8650. qcom,iommu-pmu-ncounters = <0x8>;
  8651. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8652. qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x2494 0x20ac 0x215c 0x220c 0x22bc 0x2008 0x200c 0x2010 0x2014>;
  8653. qcom,iommu-bfb-data = <0xffff 0x4 0x10 0x0 0x0 0xf 0x4b 0x0 0x1e00 0x1e00 0x5a0f 0x0 0x0 0x0 0x0 0x0>;
  8654. qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x2494 0x20ac 0x215c 0x220c 0x22bc 0x2008 0x200c 0x2010 0x2014>;
  8655. qcom,iommu-lpae-bfb-data = <0xffff 0x0 0x4 0x10 0x0 0x0 0xf 0x4b 0x1e00 0x5a2d 0x1e00 0x5a0f 0x0 0x0 0x0 0x0>;
  8656.  
  8657. qcom,iommu-ctx@fdeec000 {
  8658. compatible = "qcom,msm-smmu-v1-ctx";
  8659. reg = <0xfdeec000 0x1000>;
  8660. interrupts = <0x0 0x91 0x0>;
  8661. qcom,iommu-ctx-sids = <0x0 0x1 0x3>;
  8662. label = "vpu_cb_0";
  8663. };
  8664.  
  8665. qcom,iommu-ctx@fdeed000 {
  8666. compatible = "qcom,msm-smmu-v1-ctx";
  8667. reg = <0xfdeed000 0x1000>;
  8668. interrupts = <0x0 0x91 0x0>;
  8669. qcom,iommu-ctx-sids = <0x8 0x9>;
  8670. label = "vpu_cb_1";
  8671. };
  8672.  
  8673. qcom,iommu-ctx@fdeee000 {
  8674. compatible = "qcom,msm-smmu-v1-ctx";
  8675. reg = <0xfdeee000 0x1000>;
  8676. interrupts = <0x0 0x91 0x0>;
  8677. qcom,iommu-ctx-sids = <0x5 0x7 0xf>;
  8678. label = "vpu_cb_2";
  8679. };
  8680. };
  8681.  
  8682. qcom,iommu@fe054000 {
  8683. compatible = "qcom,msm-smmu-v1";
  8684. #address-cells = <0x1>;
  8685. #size-cells = <0x1>;
  8686. ranges;
  8687. reg = <0xfe054000 0x10000>;
  8688. reg-names = "iommu_base";
  8689. interrupts = <0x0 0xca 0x0>;
  8690. label = "lpass_qdsp_iommu";
  8691. qcom,msm-bus,name = "lpass_qdsp_ebi";
  8692. qcom,msm-bus,num-cases = <0x2>;
  8693. qcom,msm-bus,num-paths = <0x1>;
  8694. qcom,msm-bus,vectors-KBps = <0xb 0x200 0x0 0x0 0xb 0x200 0x0 0x3e8>;
  8695. status = "disabled";
  8696. qcom,iommu-pmu-ngroups = <0x1>;
  8697. qcom,iommu-pmu-ncounters = <0x8>;
  8698. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8699. qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>;
  8700. qcom,iommu-bfb-data = <0x3 0x4 0x4 0x0 0x0 0x0 0x10 0x0 0x0 0x15e 0x19e 0x0 0x0>;
  8701. qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>;
  8702. qcom,iommu-lpae-bfb-data = <0x3 0x0 0x4 0x4 0x0 0x20 0x0 0x10 0x0 0x0 0x15e 0x19e 0x0>;
  8703.  
  8704. qcom,iommu-ctx@fe05c000 {
  8705. compatible = "qcom,msm-smmu-v1-ctx";
  8706. reg = <0xfe05c000 0x1000>;
  8707. interrupts = <0x0 0x109 0x0>;
  8708. qcom,iommu-ctx-sids = <0x0>;
  8709. label = "lpass_qdsp_cb_0";
  8710. };
  8711.  
  8712. qcom,iommu-ctx@fe05d000 {
  8713. compatible = "qcom,msm-smmu-v1-ctx";
  8714. reg = <0xfe05d000 0x1000>;
  8715. interrupts = <0x0 0x109 0x0>;
  8716. qcom,iommu-ctx-sids = <0x1>;
  8717. label = "lpass_qdsp_cb_1";
  8718. };
  8719.  
  8720. qcom,iommu-ctx@fe05e000 {
  8721. compatible = "qcom,msm-smmu-v1-ctx";
  8722. reg = <0xfe05e000 0x1000>;
  8723. interrupts = <0x0 0x109 0x0>;
  8724. qcom,iommu-ctx-sids = <0x2>;
  8725. label = "lpass_qdsp_cb_2";
  8726. };
  8727.  
  8728. qcom,iommu-ctx@fe05f000 {
  8729. compatible = "qcom,msm-smmu-v1-ctx";
  8730. reg = <0xfe05f000 0x1000>;
  8731. interrupts = <0x0 0x109 0x0>;
  8732. qcom,iommu-ctx-sids = <0x3>;
  8733. label = "lpass_qdsp_cb_3";
  8734. };
  8735. };
  8736.  
  8737. qcom,iommu@fe064000 {
  8738. compatible = "qcom,msm-smmu-v1";
  8739. #address-cells = <0x1>;
  8740. #size-cells = <0x1>;
  8741. ranges;
  8742. reg = <0xfe064000 0x10000>;
  8743. reg-names = "iommu_base";
  8744. interrupts = <0x0 0xa6 0x0>;
  8745. label = "lpass_core_iommu";
  8746. qcom,msm-bus,name = "lpass_core_ebi";
  8747. qcom,msm-bus,num-cases = <0x2>;
  8748. qcom,msm-bus,num-paths = <0x1>;
  8749. qcom,msm-bus,vectors-KBps = <0x34 0x200 0x0 0x0 0x34 0x200 0x0 0x3e8>;
  8750. status = "disabled";
  8751. qcom,iommu-pmu-ngroups = <0x1>;
  8752. qcom,iommu-pmu-ncounters = <0x8>;
  8753. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8754. qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>;
  8755. qcom,iommu-bfb-data = <0x3 0x4 0x4 0x0 0x0 0x0 0x4 0x0 0x0 0x40 0x50 0x0 0x0>;
  8756. qcom,iommu-lpae-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x20ac 0x215c 0x220c 0x22bc 0x2314 0x2394 0x2414 0x2494 0x2008>;
  8757. qcom,iommu-lpae-bfb-data = <0x3 0x0 0x4 0x4 0x0 0xc 0x0 0x4 0x0 0x0 0x40 0x50 0x0>;
  8758.  
  8759. qcom,iommu-ctx@fe06c000 {
  8760. compatible = "qcom,msm-smmu-v1-ctx";
  8761. reg = <0xfe06c000 0x1000>;
  8762. interrupts = <0x0 0x10b 0x0>;
  8763. qcom,iommu-ctx-sids = <0x0>;
  8764. label = "lpass_core_cb_0";
  8765. };
  8766.  
  8767. qcom,iommu-ctx@fe06d000 {
  8768. compatible = "qcom,msm-smmu-v1-ctx";
  8769. reg = <0xfe06d000 0x1000>;
  8770. interrupts = <0x0 0x10b 0x0>;
  8771. qcom,iommu-ctx-sids = <0x1>;
  8772. label = "lpass_core_cb_1";
  8773. };
  8774.  
  8775. qcom,iommu-ctx@fe06e000 {
  8776. compatible = "qcom,msm-smmu-v1-ctx";
  8777. reg = <0xfe06e000 0x1000>;
  8778. interrupts = <0x0 0x10b 0x0>;
  8779. qcom,iommu-ctx-sids = <0x2>;
  8780. label = "lpass_core_cb_2";
  8781. };
  8782. };
  8783.  
  8784. qcom,iommu@fdfb6000 {
  8785. compatible = "qcom,msm-smmu-v1";
  8786. #address-cells = <0x1>;
  8787. #size-cells = <0x1>;
  8788. ranges;
  8789. reg = <0xfdfb6000 0x10000>;
  8790. reg-names = "iommu_base";
  8791. interrupts = <0x0 0x13b 0x0>;
  8792. qcom,needs-alt-core-clk;
  8793. label = "vcap_iommu";
  8794. status = "disabled";
  8795. qcom,msm-bus,name = "vcap_ebi";
  8796. qcom,msm-bus,num-cases = <0x2>;
  8797. qcom,msm-bus,num-paths = <0x1>;
  8798. qcom,msm-bus,vectors-KBps = <0x30 0x200 0x0 0x0 0x30 0x200 0x0 0x3e8>;
  8799. qcom,iommu-pmu-ngroups = <0x1>;
  8800. qcom,iommu-pmu-ncounters = <0x8>;
  8801. qcom,iommu-pmu-event-classes = <0x0 0x1 0x8 0x9 0xa 0x10 0x11 0x12 0x80 0x81 0x82 0x83 0x90 0x91 0x92 0xb0 0xb1>;
  8802. qcom,iommu-bfb-regs = <0x204c 0x2514 0x2540 0x256c 0x2314 0x2394 0x2414 0x2494 0x20ac 0x215c 0x220c 0x22bc 0x2008 0x200c>;
  8803. qcom,iommu-bfb-data = <0xff 0x4 0x8 0x0 0x0 0x8 0x28 0x0 0x1000 0x1000 0x3008 0x0 0x0 0x0>;
  8804.  
  8805. qcom,iommu-ctx@fdfbe000 {
  8806. compatible = "qcom,msm-smmu-v1-ctx";
  8807. reg = <0xfdfbe000 0x1000>;
  8808. interrupts = <0x0 0x139 0x0>;
  8809. qcom,iommu-ctx-sids = <0x0>;
  8810. label = "vcap_cb0";
  8811. };
  8812.  
  8813. qcom,iommu-ctx@fdfbf000 {
  8814. compatible = "qcom,msm-smmu-v1-ctx";
  8815. reg = <0xfdfbf000 0x1000>;
  8816. interrupts = <0x0 0x139 0x0>;
  8817. qcom,iommu-ctx-sids = <0x1>;
  8818. label = "vcap_cb1";
  8819. };
  8820.  
  8821. qcom,iommu-ctx@fdfc0000 {
  8822. compatible = "qcom,msm-smmu-v1-ctx";
  8823. reg = <0xfdfc0000 0x1000>;
  8824. interrupts = <0x0 0x139 0x0>;
  8825. qcom,iommu-ctx-sids;
  8826. label = "vcap_cb2";
  8827. };
  8828. };
  8829.  
  8830. qcom,iommu-domains {
  8831. compatible = "qcom,iommu-domains";
  8832.  
  8833. qcom,iommu-domain1 {
  8834. label = "venus_ns";
  8835. qcom,iommu-contexts = <0x72>;
  8836. qcom,virtual-addr-pool = <0x5dc00000 0x7f000000 0xdcc00000 0x1000000>;
  8837. linux,phandle = <0x3d>;
  8838. phandle = <0x3d>;
  8839. };
  8840.  
  8841. qcom,iommu-domain2 {
  8842. label = "venus_sec_bitstream";
  8843. qcom,iommu-contexts = <0x73>;
  8844. qcom,virtual-addr-pool = <0x4b000000 0x12c00000>;
  8845. qcom,secure-domain;
  8846. linux,phandle = <0x3e>;
  8847. phandle = <0x3e>;
  8848. };
  8849.  
  8850. qcom,iommu-domain3 {
  8851. label = "venus_sec_pixel";
  8852. qcom,iommu-contexts = <0x74>;
  8853. qcom,virtual-addr-pool = <0x25800000 0x25800000>;
  8854. qcom,secure-domain;
  8855. linux,phandle = <0x3f>;
  8856. phandle = <0x3f>;
  8857. };
  8858.  
  8859. qcom,iommu-domain4 {
  8860. label = "venus_sec_non_pixel";
  8861. qcom,iommu-contexts = <0x75>;
  8862. qcom,virtual-addr-pool = <0x1000000 0x24800000>;
  8863. qcom,secure-domain;
  8864. linux,phandle = <0x40>;
  8865. phandle = <0x40>;
  8866. };
  8867. };
  8868.  
  8869. qcom,spm@f9089000 {
  8870. compatible = "qcom,spm-v2";
  8871. #address-cells = <0x1>;
  8872. #size-cells = <0x1>;
  8873. reg = <0xf9089000 0x1000>;
  8874. qcom,core-id = <0x0>;
  8875. qcom,saw2-ver-reg = <0xfd0>;
  8876. qcom,saw2-cfg = <0x1>;
  8877. qcom,saw2-avs-ctl = <0x0>;
  8878. qcom,saw2-avs-hysteresis = <0x0>;
  8879. qcom,saw2-avs-limit = <0x0>;
  8880. qcom,saw2-avs-dly = <0x0>;
  8881. qcom,saw2-spm-dly = <0x3c102800>;
  8882. qcom,saw2-spm-ctl = <0x1>;
  8883. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  8884. qcom,saw2-spm-cmd-ret = [42 1b 00 d8 5b 03 d8 5b 0b 00 42 1b 0f];
  8885. qcom,saw2-spm-cmd-spc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8886. qcom,saw2-spm-cmd-pc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8887. };
  8888.  
  8889. qcom,spm@f9099000 {
  8890. compatible = "qcom,spm-v2";
  8891. #address-cells = <0x1>;
  8892. #size-cells = <0x1>;
  8893. reg = <0xf9099000 0x1000>;
  8894. qcom,core-id = <0x1>;
  8895. qcom,saw2-ver-reg = <0xfd0>;
  8896. qcom,saw2-cfg = <0x1>;
  8897. qcom,saw2-avs-ctl = <0x0>;
  8898. qcom,saw2-avs-hysteresis = <0x0>;
  8899. qcom,saw2-avs-limit = <0x0>;
  8900. qcom,saw2-avs-dly = <0x0>;
  8901. qcom,saw2-spm-dly = <0x3c102800>;
  8902. qcom,saw2-spm-ctl = <0x1>;
  8903. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  8904. qcom,saw2-spm-cmd-ret = [42 1b 00 d8 5b 03 d8 5b 0b 00 42 1b 0f];
  8905. qcom,saw2-spm-cmd-spc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8906. qcom,saw2-spm-cmd-pc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8907. };
  8908.  
  8909. qcom,spm@f90a9000 {
  8910. compatible = "qcom,spm-v2";
  8911. #address-cells = <0x1>;
  8912. #size-cells = <0x1>;
  8913. reg = <0xf90a9000 0x1000>;
  8914. qcom,core-id = <0x2>;
  8915. qcom,saw2-ver-reg = <0xfd0>;
  8916. qcom,saw2-cfg = <0x1>;
  8917. qcom,saw2-avs-ctl = <0x0>;
  8918. qcom,saw2-avs-hysteresis = <0x0>;
  8919. qcom,saw2-avs-limit = <0x0>;
  8920. qcom,saw2-avs-dly = <0x0>;
  8921. qcom,saw2-spm-dly = <0x3c102800>;
  8922. qcom,saw2-spm-ctl = <0x1>;
  8923. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  8924. qcom,saw2-spm-cmd-ret = [42 1b 00 d8 5b 03 d8 5b 0b 00 42 1b 0f];
  8925. qcom,saw2-spm-cmd-spc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8926. qcom,saw2-spm-cmd-pc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8927. };
  8928.  
  8929. qcom,spm@f90b9000 {
  8930. compatible = "qcom,spm-v2";
  8931. #address-cells = <0x1>;
  8932. #size-cells = <0x1>;
  8933. reg = <0xf90b9000 0x1000>;
  8934. qcom,core-id = <0x3>;
  8935. qcom,saw2-ver-reg = <0xfd0>;
  8936. qcom,saw2-cfg = <0x1>;
  8937. qcom,saw2-avs-ctl = <0x0>;
  8938. qcom,saw2-avs-hysteresis = <0x0>;
  8939. qcom,saw2-avs-limit = <0x0>;
  8940. qcom,saw2-avs-dly = <0x0>;
  8941. qcom,saw2-spm-dly = <0x3c102800>;
  8942. qcom,saw2-spm-ctl = <0x1>;
  8943. qcom,saw2-spm-cmd-wfi = [03 0b 0f];
  8944. qcom,saw2-spm-cmd-ret = [42 1b 00 d8 5b 03 d8 5b 0b 00 42 1b 0f];
  8945. qcom,saw2-spm-cmd-spc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8946. qcom,saw2-spm-cmd-pc = [00 20 80 10 e8 5b 03 3b e8 5b 82 10 0b 30 06 26 30 0f];
  8947. };
  8948.  
  8949. qcom,spm@f9012000 {
  8950. compatible = "qcom,spm-v2";
  8951. #address-cells = <0x1>;
  8952. #size-cells = <0x1>;
  8953. reg = <0xf9012000 0x1000>;
  8954. qcom,core-id = <0xffff>;
  8955. qcom,saw2-ver-reg = <0xfd0>;
  8956. qcom,saw2-cfg = <0x14>;
  8957. qcom,saw2-avs-ctl = <0x0>;
  8958. qcom,saw2-avs-hysteresis = <0x0>;
  8959. qcom,saw2-avs-limit = <0x0>;
  8960. qcom,saw2-avs-dly = <0x0>;
  8961. qcom,saw2-spm-dly = <0x3c102800>;
  8962. qcom,saw2-spm-ctl = <0x1>;
  8963. qcom,saw2-pmic-data0 = <0x2030080>;
  8964. qcom,saw2-pmic-data1 = <0x30000>;
  8965. qcom,vctl-timeout-us = <0x32>;
  8966. qcom,vctl-port = <0x0>;
  8967. qcom,phase-port = <0x1>;
  8968. qcom,pfm-port = <0x2>;
  8969. qcom,saw2-spm-cmd-ret = [1f 00 03 00 0f];
  8970. qcom,saw2-spm-cmd-gdhs = [00 32 42 03 44 50 02 32 50 0f];
  8971. qcom,saw2-spm-cmd-pc = <0x1032b0 0x11420701 0xb0124450 0x232500f>;
  8972. qcom,L2-spm-is-apcs-master;
  8973. };
  8974.  
  8975. qcom,lpm-levels {
  8976. compatible = "qcom,lpm-levels";
  8977. qcom,allow-synced-levels;
  8978. qcom,default-l2-state = "l2_cache_retention";
  8979. #address-cells = <0x1>;
  8980. #size-cells = <0x1>;
  8981. linux,phandle = <0x76>;
  8982. phandle = <0x76>;
  8983.  
  8984. qcom,cpu-modes {
  8985. compatible = "qcom,cpu-modes";
  8986.  
  8987. qcom,cpu-mode@0 {
  8988. qcom,mode = "wfi";
  8989. qcom,latency-us = <0x1>;
  8990. qcom,ss-power = <0x2cb>;
  8991. qcom,energy-overhead = <0x4524>;
  8992. qcom,time-overhead = <0x2>;
  8993. };
  8994.  
  8995. qcom,cpu-mode@1 {
  8996. qcom,mode = "retention";
  8997. qcom,latency-us = <0x23>;
  8998. qcom,ss-power = <0x21e>;
  8999. qcom,energy-overhead = <0x8868>;
  9000. qcom,time-overhead = <0x28>;
  9001. };
  9002.  
  9003. qcom,cpu-mode@2 {
  9004. qcom,mode = "standalone_pc";
  9005. qcom,latency-us = <0x12c>;
  9006. qcom,ss-power = <0x1dc>;
  9007. qcom,energy-overhead = <0x37014>;
  9008. qcom,time-overhead = <0x15e>;
  9009. };
  9010.  
  9011. qcom,cpu-mode@3 {
  9012. qcom,mode = "pc";
  9013. qcom,latency-us = <0x1f4>;
  9014. qcom,ss-power = <0x190>;
  9015. qcom,energy-overhead = <0x445c0>;
  9016. qcom,time-overhead = <0x1f4>;
  9017. qcom,use-broadcast-timer;
  9018. };
  9019. };
  9020.  
  9021. qcom,system-modes {
  9022. compatible = "qcom,system-modes";
  9023.  
  9024. qcom,system-mode@0 {
  9025. qcom,l2 = "l2_cache_gdhs";
  9026. qcom,latency-us = <0x1f4>;
  9027. qcom,ss-power = <0xa3>;
  9028. qcom,energy-overhead = <0x8d0c8>;
  9029. qcom,time-overhead = <0x3e8>;
  9030. qcom,min-cpu-mode = "standalone_pc";
  9031. qcom,sync-cpus;
  9032. };
  9033.  
  9034. qcom,system-mode@1 {
  9035. qcom,l2 = "l2_cache_pc";
  9036. qcom,latency-us = <0x7530>;
  9037. qcom,ss-power = <0x53>;
  9038. qcom,energy-overhead = <0x22b474>;
  9039. qcom,time-overhead = <0x19cd>;
  9040. qcom,min-cpu-mode = "pc";
  9041. qcom,sync-cpus;
  9042. qcom,send-rpm-sleep-set;
  9043. };
  9044. };
  9045. };
  9046.  
  9047. qcom,pm-boot {
  9048. compatible = "qcom,pm-boot";
  9049. qcom,mode = "tz";
  9050. };
  9051.  
  9052. qcom,mpm@fc4281d0 {
  9053. compatible = "qcom,mpm-v2";
  9054. reg = <0xfc4281d0 0x1000 0xf9011008 0x4>;
  9055. reg-names = "vmpm", "ipc";
  9056. interrupts = <0x0 0xab 0x1>;
  9057. qcom,ipc-bit-offset = <0x1>;
  9058. qcom,gic-parent = <0x1>;
  9059. qcom,gic-map = <0x2 0xd8 0x2f 0xa5 0x32 0xac 0x35 0x68 0x3e 0xde 0xff 0x12 0xff 0x13 0xff 0x19 0xff 0x21 0xff 0x22 0xff 0x23 0xff 0x28 0xff 0x38 0xff 0x39 0xff 0x3a 0xff 0x3b 0xff 0x3c 0xff 0x3d 0xff 0x46 0xff 0x4a 0xff 0x4b 0xff 0x4d 0xff 0x4e 0xff 0x4f 0xff 0x5e 0xff 0x61 0xff 0x63 0xff 0x66 0xff 0x69 0xff 0x6d 0xff 0x7e 0xff 0x8c 0xff 0x92 0xff 0x9b 0xff 0x9d 0xff 0x9f 0xff 0xa3 0xff 0xa6 0xff 0xaa 0xff 0xad 0xff 0xae 0xff 0xaf 0xff 0xb0 0xff 0xb1 0xff 0xb2 0xff 0xb3 0xff 0xb5 0xff 0xbc 0xff 0xbd 0xff 0xbe 0xff 0xbf 0xff 0xc0 0xff 0xc1 0xff 0xc2 0xff 0xc3 0xff 0xc4 0xff 0xc5 0xff 0xc6 0xff 0xc8 0xff 0xc9 0xff 0xca 0xff 0xcb 0xff 0xcc 0xff 0xcd 0xff 0xce 0xff 0xcf 0xff 0xd3 0xff 0xf0 0xff 0xfd 0xff 0x100 0xff 0x10c 0xff 0x10e 0xff 0x10f>;
  9060. qcom,gpio-parent = <0x5>;
  9061. qcom,gpio-map = <0x3 0x66 0x4 0x1 0x5 0x5 0x6 0x9 0x7 0x12 0x8 0x14 0x9 0x18 0xa 0x1b 0xb 0x1c 0xc 0x22 0xd 0x23 0xe 0x25 0xf 0x2a 0x10 0x2c 0x11 0x2e 0x12 0x32 0x13 0x36 0x14 0x3b 0x15 0x3d 0x16 0x3e 0x17 0x40 0x18 0x41 0x19 0x42 0x1a 0x43 0x1b 0x44 0x1c 0x47 0x1d 0x48 0x1e 0x49 0x1f 0x4a 0x20 0x4b 0x21 0x4d 0x22 0x4f 0x23 0x50 0x24 0x52 0x25 0x56 0x26 0x5c 0x27 0x5d 0x28 0x5f 0x29 0x90>;
  9062. };
  9063.  
  9064. qcom,pm-8x60@fe805664 {
  9065. compatible = "qcom,pm-8x60";
  9066. #address-cells = <0x1>;
  9067. #size-cells = <0x1>;
  9068. ranges;
  9069. reg = <0xfe805664 0x40>;
  9070. qcom,pc-mode = "tz_l2_int";
  9071. qcom,cpus-as-clocks;
  9072. qcom,lpm-levels = <0x76>;
  9073.  
  9074. qcom,pm-snoc-client {
  9075. compatible = "qcom,pm-snoc-client";
  9076. qcom,msm-bus,name = "ocimem_snoc";
  9077. qcom,msm-bus,num-cases = <0x2>;
  9078. qcom,msm-bus,num-paths = <0x1>;
  9079. qcom,msm-bus,active-only;
  9080. qcom,msm-bus,vectors-KBps = <0x36 0x249 0x0 0x0 0x36 0x249 0x0 0xc3500>;
  9081. };
  9082. };
  9083.  
  9084. qcom,cpu-sleep-status@f9088008 {
  9085. compatible = "qcom,cpu-sleep-status";
  9086. reg = <0xf9088008 0x100>;
  9087. qcom,cpu-alias-addr = <0x10000>;
  9088. qcom,sleep-status-mask = <0x80000>;
  9089. };
  9090.  
  9091. qcom,rpm-log@fc19dc00 {
  9092. compatible = "qcom,rpm-log";
  9093. reg = <0xfc19dc00 0x4000>;
  9094. qcom,rpm-addr-phys = <0xfc000000>;
  9095. qcom,offset-version = <0x4>;
  9096. qcom,offset-page-buffer-addr = <0x24>;
  9097. qcom,offset-log-len = <0x28>;
  9098. qcom,offset-log-len-mask = <0x2c>;
  9099. qcom,offset-page-indices = <0x38>;
  9100. };
  9101.  
  9102. qcom,rpm-stats@fc19dba0 {
  9103. compatible = "qcom,rpm-stats";
  9104. reg = <0xfc19dba0 0x1000>;
  9105. reg-names = "phys_addr_base";
  9106. qcom,sleep-stats-version = <0x2>;
  9107. };
  9108.  
  9109. qcom,rpm-rbcpr-stats@fc000000 {
  9110. compatible = "qcom,rpmrbcpr-stats";
  9111. reg = <0xfc000000 0x1a0000>;
  9112. qcom,start-offset = <0x190010>;
  9113. };
  9114.  
  9115. qcom,rpm-master-stats@fc428150 {
  9116. compatible = "qcom,rpm-master-stats";
  9117. reg = <0xfc428150 0x3200>;
  9118. qcom,masters = "APSS", "MPSS", "LPSS", "PRONTO";
  9119. qcom,master-stats-version = <0x2>;
  9120. qcom,master-offset = <0xa00>;
  9121. };
  9122.  
  9123. android_usb@fe8050c8 {
  9124. compatible = "qcom,android-usb";
  9125. reg = <0xfe8050c8 0xc8>;
  9126. qcom,android-usb-swfi-latency = <0x1>;
  9127. qcom,android-usb-uicc-nluns = [01];
  9128. };
  9129.  
  9130. qcom,msm-imem@fe805000 {
  9131. compatible = "qcom,msm-imem";
  9132. reg = <0xfe805000 0x1000>;
  9133. };
  9134.  
  9135. krait-pdn@f9011000 {
  9136. reg = <0xf9011000 0x1000 0xfc4b80b0 0x8>;
  9137. reg-names = "apcs_gcc", "phase-scaling-efuse";
  9138. compatible = "qcom,krait-pdn";
  9139. #address-cells = <0x1>;
  9140. #size-cells = <0x1>;
  9141. ranges;
  9142. qcom,pfm-threshold = <0x4c>;
  9143. qcom,use-phase-scaling-factor;
  9144. qcom,phase-scaling-factor-bits-pos = <0x10>;
  9145. qcom,valid-scaling-factor-versions = <0x0 0x1 0x0 0x0>;
  9146. qcom,use-phase-switching;
  9147.  
  9148. regulator@f9088000 {
  9149. compatible = "qcom,krait-regulator";
  9150. regulator-name = "krait0";
  9151. reg = <0xf9088000 0x1000 0xf908a800 0x1000>;
  9152. reg-names = "acs", "mdd";
  9153. regulator-min-microvolt = <0x7a120>;
  9154. regulator-max-microvolt = <0x10c8e0>;
  9155. qcom,headroom-voltage = <0x249f0>;
  9156. qcom,retention-voltage = <0xa4cb8>;
  9157. qcom,ldo-default-voltage = <0xb71b0>;
  9158. qcom,ldo-threshold-voltage = <0xcf850>;
  9159. qcom,ldo-delta-voltage = <0xc350>;
  9160. qcom,cpu-num = <0x0>;
  9161. linux,phandle = <0x5a>;
  9162. phandle = <0x5a>;
  9163. };
  9164.  
  9165. regulator@f9098000 {
  9166. compatible = "qcom,krait-regulator";
  9167. regulator-name = "krait1";
  9168. reg = <0xf9098000 0x1000 0xf909a800 0x1000>;
  9169. reg-names = "acs", "mdd";
  9170. regulator-min-microvolt = <0x7a120>;
  9171. regulator-max-microvolt = <0x10c8e0>;
  9172. qcom,headroom-voltage = <0x249f0>;
  9173. qcom,retention-voltage = <0xa4cb8>;
  9174. qcom,ldo-default-voltage = <0xb71b0>;
  9175. qcom,ldo-threshold-voltage = <0xcf850>;
  9176. qcom,ldo-delta-voltage = <0xc350>;
  9177. qcom,cpu-num = <0x1>;
  9178. linux,phandle = <0x5b>;
  9179. phandle = <0x5b>;
  9180. };
  9181.  
  9182. regulator@f90a8000 {
  9183. compatible = "qcom,krait-regulator";
  9184. regulator-name = "krait2";
  9185. reg = <0xf90a8000 0x1000 0xf90aa800 0x1000>;
  9186. reg-names = "acs", "mdd";
  9187. regulator-min-microvolt = <0x7a120>;
  9188. regulator-max-microvolt = <0x10c8e0>;
  9189. qcom,headroom-voltage = <0x249f0>;
  9190. qcom,retention-voltage = <0xa4cb8>;
  9191. qcom,ldo-default-voltage = <0xb71b0>;
  9192. qcom,ldo-threshold-voltage = <0xcf850>;
  9193. qcom,ldo-delta-voltage = <0xc350>;
  9194. qcom,cpu-num = <0x2>;
  9195. linux,phandle = <0x5c>;
  9196. phandle = <0x5c>;
  9197. };
  9198.  
  9199. regulator@f90b8000 {
  9200. compatible = "qcom,krait-regulator";
  9201. regulator-name = "krait3";
  9202. reg = <0xf90b8000 0x1000 0xf90ba800 0x1000>;
  9203. reg-names = "acs", "mdd";
  9204. regulator-min-microvolt = <0x7a120>;
  9205. regulator-max-microvolt = <0x10c8e0>;
  9206. qcom,headroom-voltage = <0x249f0>;
  9207. qcom,retention-voltage = <0xa4cb8>;
  9208. qcom,ldo-default-voltage = <0xb71b0>;
  9209. qcom,ldo-threshold-voltage = <0xcf850>;
  9210. qcom,ldo-delta-voltage = <0xc350>;
  9211. qcom,cpu-num = <0x3>;
  9212. linux,phandle = <0x5d>;
  9213. phandle = <0x5d>;
  9214. };
  9215. };
  9216.  
  9217. spi_eth_phy_vreg {
  9218. compatible = "regulator-fixed";
  9219. regulator-name = "ethernet_phy";
  9220. gpio = <0x58 0x5 0x0>;
  9221. enable-active-high;
  9222. linux,phandle = <0x59>;
  9223. phandle = <0x59>;
  9224. };
  9225.  
  9226. vph_pwr_vreg {
  9227. compatible = "regulator-fixed";
  9228. status = "disabled";
  9229. regulator-name = "vph_pwr";
  9230. regulator-always-on;
  9231. };
  9232.  
  9233. qcom,camera-led-flash {
  9234. cell-index = <0x0>;
  9235. compatible = "qcom,camera-led-flash";
  9236. qcom,flash-type = <0x1>;
  9237. qcom,torch-source = <0x77>;
  9238. qcom,flash-source = <0x78 0x79>;
  9239. linux,phandle = <0xb>;
  9240. phandle = <0xb>;
  9241. };
  9242.  
  9243. gen-vkeys {
  9244. compatible = "qcom,gen-vkeys";
  9245. label = "atmel_mxt_ts";
  9246. qcom,disp-maxx = <0x2d0>;
  9247. qcom,disp-maxy = <0x500>;
  9248. qcom,panel-maxx = <0x2f8>;
  9249. qcom,panel-maxy = <0x590>;
  9250. qcom,key-codes = <0x9e 0x8b 0x66 0xd9>;
  9251. };
  9252.  
  9253. gpio_keys {
  9254. compatible = "gpio-keys";
  9255. input-name = "gpio-keys";
  9256.  
  9257. camera_snapshot {
  9258. label = "camera_snapshot";
  9259. gpios = <0x2a 0x1 0x1>;
  9260. linux,input-type = <0x1>;
  9261. linux,code = <0x2fe>;
  9262. gpio-key,wakeup;
  9263. debounce-interval = <0xf>;
  9264. };
  9265.  
  9266. vol_up {
  9267. label = "volume_up";
  9268. gpios = <0x2a 0x5 0x1>;
  9269. linux,input-type = <0x1>;
  9270. linux,code = <0x73>;
  9271. gpio-key,wakeup;
  9272. debounce-interval = <0xf>;
  9273. };
  9274.  
  9275. vol_down {
  9276. label = "volume_down";
  9277. gpios = <0x2a 0x2 0x1>;
  9278. linux,input-type = <0x1>;
  9279. linux,code = <0x72>;
  9280. gpio-key,wakeup;
  9281. debounce-interval = <0xf>;
  9282. };
  9283. };
  9284. };
  9285.  
  9286. qcom,battery-data {
  9287. qcom,rpull-up-kohm = <0x64>;
  9288. qcom,vref-batt-therm = <0x1b7740>;
  9289. linux,phandle = <0x52>;
  9290. phandle = <0x52>;
  9291.  
  9292. qcom,Hip2420-batterydata {
  9293. qcom,battery-type = "Hip2420";
  9294. qcom,batt-id-kohm = <0x2f>;
  9295. qcom,chg-term-ua = <0x186a0>;
  9296. qcom,default-rbatt-mohm = <0xb2>;
  9297. qcom,fcc-mah = <0x974>;
  9298. qcom,max-voltage-uv = <0x426030>;
  9299. qcom,rbatt-capacitive-mohm = <0x0>;
  9300. qcom,v-cutoff-uv = <0x33e140>;
  9301.  
  9302. qcom,fcc-temp-lut {
  9303. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9304. qcom,lut-data = <0x939 0x95c 0x964 0x963 0x95a>;
  9305. };
  9306.  
  9307. qcom,pc-temp-ocv-lut {
  9308. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9309. qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x10 0xd 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
  9310. qcom,lut-data = <0x10ee 0x10ec 0x10e7 0x10e4 0x10dc 0x1058 0x108a 0x1099 0x109a 0x1096 0xffe 0x1042 0x105a 0x105c 0x105a 0xfb4 0x1004 0x1020 0x1024 0x1024 0xf6c 0xfd3 0xff0 0xff6 0xff7 0xf38 0xf92 0xfc6 0xfcc 0xfcc 0xf0c 0xf66 0xf9c 0xfa0 0xf9f 0xeeb 0xf3d 0xf6c 0xf74 0xf74 0xed6 0xf18 0xf34 0xf3a 0xf3a 0xec6 0xef9 0xf12 0xf16 0xf17 0xeb4 0xedc 0xef6 0xefa 0xefc 0xea0 0xec6 0xedf 0xee3 0xee4 0xe8a 0xeb5 0xeca 0xece 0xecf 0xe72 0xea3 0xeb8 0xeb8 0xeb0 0xe54 0xe8b 0xea4 0xea0 0xe96 0xe2e 0xe6e 0xe86 0xe82 0xe77 0xdf9 0xe5a 0xe64 0xe60 0xe58 0xdc0 0xe46 0xe58 0xe57 0xe4e 0xd8a 0xe2d 0xe48 0xe44 0xe35 0xd5a 0xe0f 0xe22 0xe20 0xe10 0xd40 0xdfa 0xe0a 0xe08 0xdf8 0xd1f 0xdda 0xdec 0xdea 0xdda 0xcfa 0xdb6 0xdca 0xdc9 0xdba 0xccf 0xd8a 0xda6 0xda7 0xd9c 0xca1 0xd5b 0xd82 0xd86 0xd80 0xc72 0xd29 0xd60 0xd64 0xd5f 0xc46 0xcfc 0xd38 0xd3a 0xd34 0xc20 0xcc6 0xd03 0xd06 0xcfe 0xc00 0xc83 0xcbc 0xcbc 0xcb3 0xbe0 0xc30 0xc58 0xc53 0xc42 0xbb8 0xbc4 0xbb8 0xbb8 0xbbd>;
  9311. };
  9312.  
  9313. qcom,rbatt-sf-lut {
  9314. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9315. qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x10 0xd 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1>;
  9316. qcom,lut-data = <0x4c2 0x154 0x64 0x4a 0x3e 0x4c2 0x154 0x64 0x4a 0x3e 0x464 0x159 0x68 0x4c 0x3f 0x41d 0x156 0x6c 0x4f 0x41 0x3e1 0x154 0x72 0x53 0x43 0x3c8 0x136 0x78 0x54 0x45 0x3b7 0x12b 0x7f 0x58 0x47 0x3b4 0x122 0x7a 0x61 0x4c 0x3cf 0x11c 0x64 0x4e 0x42 0x401 0x11a 0x61 0x4a 0x40 0x43c 0x118 0x61 0x4c 0x41 0x474 0x11c 0x64 0x4f 0x44 0x4b0 0x12f 0x67 0x50 0x46 0x4f2 0x153 0x66 0x4e 0x41 0x545 0x176 0x66 0x4b 0x3f 0x608 0x1a0 0x6a 0x4b 0x3f 0x804 0x1ee 0x6a 0x4b 0x40 0xabb 0x243 0x77 0x53 0x45 0xda5 0x27d 0x8f 0x5d 0x4d 0x1038 0x28d 0x93 0x65 0x54 0x11aa 0x286 0x90 0x68 0x58 0x122c 0x256 0x91 0x6a 0x5c 0x1550 0x260 0x97 0x6d 0x5d 0x19d4 0x270 0xa1 0x72 0x61 0x2218 0x286 0xb0 0x7a 0x66 0x2e68 0x2ab 0xc8 0x83 0x68 0x3fba 0x2e1 0xe5 0x90 0x72 0x5926 0x33c 0x10e 0xa6 0x7e 0x7dac 0x587 0x16f 0xd7 0x97 0xb2ec 0xb0e 0x2df 0x188 0x107>;
  9317. };
  9318. };
  9319.  
  9320. qcom,palladium-batterydata {
  9321. qcom,fcc-mah = <0x974>;
  9322. qcom,default-rbatt-mohm = <0xa6>;
  9323. qcom,rbatt-capacitive-mohm = <0x0>;
  9324. qcom,flat-ocv-threshold-uv = <0x39fbc0>;
  9325. qcom,max-voltage-uv = <0x426030>;
  9326. qcom,v-cutoff-uv = <0x33e140>;
  9327. qcom,chg-term-ua = <0x186a0>;
  9328. qcom,batt-id-kohm = <0x4b>;
  9329.  
  9330. qcom,fcc-temp-lut {
  9331. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9332. qcom,lut-data = <0x914 0x930 0x93e 0x93c 0x930>;
  9333. };
  9334.  
  9335. qcom,pc-temp-ocv-lut {
  9336. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9337. qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x10 0xd 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
  9338. qcom,lut-data = <0x10ee 0x10ea 0x10e3 0x10db 0x10d2 0x103b 0x107a 0x1091 0x1092 0x108e 0xfcc 0x102c 0x1050 0x1054 0x1052 0xf75 0xfe8 0x1017 0x101c 0x101c 0xf38 0xfa5 0xfe4 0xfed 0xff0 0xf0d 0xf70 0xfba 0xfc4 0xfc6 0xef0 0xf46 0xf8f 0xf98 0xf98 0xedc 0xf22 0xf5b 0xf68 0xf6a 0xec9 0xf02 0xf2d 0xf34 0xf36 0xeb6 0xee5 0xf0c 0xf10 0xf13 0xea1 0xecc 0xef0 0xef6 0xef8 0xe88 0xeba 0xed8 0xedd 0xedf 0xe6b 0xea8 0xec3 0xec6 0xec8 0xe48 0xe94 0xeb0 0xeb1 0xeac 0xe1c 0xe7e 0xe9b 0xe9a 0xe90 0xde6 0xe66 0xe7e 0xe7c 0xe71 0xda4 0xe4a 0xe62 0xe60 0xe56 0xd68 0xe2a 0xe52 0xe52 0xe48 0xd33 0xe04 0xe39 0xe3c 0xe33 0xd04 0xddb 0xe18 0xe18 0xe06 0xcea 0xdc3 0xdfc 0xdfc 0xdee 0xcce 0xda6 0xddf 0xddf 0xdd0 0xcac 0xd86 0xdbd 0xdbf 0xdb2 0xc8a 0xd60 0xd99 0xd9c 0xd95 0xc68 0xd31 0xd74 0xd7c 0xd78 0xc48 0xcfc 0xd50 0xd5b 0xd56 0xc2f 0xcc4 0xd28 0xd32 0xd2b 0xc13 0xc8b 0xcf4 0xcfe 0xcf5 0xbf8 0xc4e 0xcae 0xcb6 0xcaa 0xbdc 0xc09 0xc4d 0xc4f 0xc40 0xbb8 0xbb8 0xbb8 0xbb8 0xbb8>;
  9339. };
  9340.  
  9341. qcom,rbatt-sf-lut {
  9342. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9343. qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x10 0xd 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
  9344. qcom,lut-data = <0x521 0x152 0x64 0x4b 0x41 0x521 0x152 0x64 0x4b 0x41 0x49f 0x153 0x67 0x4d 0x42 0x430 0x14b 0x6c 0x51 0x44 0x3f0 0x13b 0x71 0x54 0x46 0x3d9 0x12e 0x77 0x57 0x47 0x3de 0x128 0x7c 0x5a 0x49 0x400 0x122 0x70 0x5c 0x4b 0x437 0x120 0x64 0x4e 0x43 0x479 0x11f 0x62 0x4b 0x42 0x4bb 0x11f 0x62 0x4d 0x44 0x4fd 0x125 0x63 0x4e 0x45 0x53f 0x135 0x64 0x4e 0x46 0x588 0x151 0x63 0x4d 0x43 0x635 0x17a 0x64 0x4b 0x41 0x7a8 0x1b3 0x67 0x4c 0x42 0xa07 0x204 0x69 0x4e 0x43 0xcd0 0x251 0x74 0x54 0x46 0x1014 0x28c 0x84 0x5c 0x4a 0x1417 0x2a6 0x8e 0x62 0x52 0x166e 0x2ae 0x92 0x64 0x55 0x196a 0x2b1 0x97 0x67 0x57 0x1db8 0x2a7 0x9b 0x6c 0x5c 0x223f 0x298 0xa7 0x71 0x5f 0x27e3 0x2ac 0xbb 0x78 0x63 0x2f64 0x2d3 0xd6 0x84 0x68 0x387b 0x31c 0xf6 0x91 0x6f 0x4395 0x404 0x11f 0xa5 0x79 0x50ea 0x65e 0x167 0xcc 0x91 0x6230 0xa71 0x254 0x15c 0xe8 0x7afa 0x14e2 0x4a8 0x2b8 0x1d0>;
  9345. };
  9346. };
  9347.  
  9348. qcom,mtp-3000mah {
  9349. qcom,fcc-mah = <0xbb8>;
  9350. qcom,default-rbatt-mohm = <0x71>;
  9351. qcom,max-voltage-uv = <0x401640>;
  9352. qcom,rbatt-capacitive-mohm = <0x32>;
  9353. qcom,v-cutoff-uv = <0x33e140>;
  9354. qcom,chg-term-ua = <0x30d40>;
  9355. qcom,batt-id-kohm = <0x12c>;
  9356.  
  9357. qcom,fcc-temp-lut {
  9358. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9359. qcom,lut-data = <0xbd6 0xbd9 0xbdd 0xbdb 0xbd7>;
  9360. };
  9361.  
  9362. qcom,pc-temp-ocv-lut {
  9363. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9364. qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x10 0xd 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
  9365. qcom,lut-data = <0x105f 0x105c 0x1057 0x1053 0x104e 0x100a 0x101d 0x101f 0x101d 0x1019 0xfce 0xff2 0xff2 0xff0 0xfed 0xf7e 0xfc6 0xfcc 0xfc8 0xfc3 0xf52 0xf8f 0xf9a 0xf9e 0xf9d 0xf2e 0xf6d 0xf7e 0xf7e 0xf7a 0xf10 0xf44 0xf61 0xf5f 0xf5b 0xef8 0xf23 0xf44 0xf43 0xf3f 0xee6 0xf07 0xf22 0xf26 0xf23 0xed7 0xef2 0xef7 0xef8 0xef6 0xecb 0xedf 0xee3 0xee3 0xee1 0xebf 0xed1 0xed3 0xed3 0xed1 0xeb4 0xec6 0xec7 0xec7 0xec5 0xea8 0xebf 0xebd 0xebc 0xeb9 0xe9b 0xeb8 0xeb6 0xeb2 0xeab 0xe8d 0xeac 0xeac 0xea3 0xe95 0xe7e 0xe94 0xe96 0xe8d 0xe7f 0xe70 0xe7b 0xe79 0xe71 0xe64 0xe61 0xe6f 0xe66 0xe5e 0xe53 0xe53 0xe6a 0xe64 0xe5c 0xe51 0xe4a 0xe68 0xe63 0xe5b 0xe50 0xe3e 0xe65 0xe61 0xe5a 0xe4f 0xe2f 0xe62 0xe5f 0xe59 0xe4c 0xe1c 0xe5d 0xe5c 0xe55 0xe47 0xe05 0xe53 0xe52 0xe4c 0xe37 0xde8 0xe3b 0xe34 0xe2e 0xe0f 0xdc3 0xe10 0xe02 0xdfd 0xdda 0xd92 0xdd1 0xdbe 0xdbc 0xd95 0xd42 0xd76 0xd61 0xd63 0xd33 0xcb9 0xcea 0xcc9 0xcd3 0xc8d 0xbb8 0xbb8 0xbb8 0xbb8 0xbb8>;
  9366. };
  9367.  
  9368. qcom,rbatt-sf-lut {
  9369. qcom,lut-col-legend = <0xffffffec 0x0 0x19 0x28 0x3c>;
  9370. qcom,lut-row-legend = <0x64 0x5f 0x5a 0x55 0x50 0x4b 0x46 0x41 0x3c 0x37 0x32 0x2d 0x28 0x23 0x1e 0x19 0x14 0x10 0xd 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1>;
  9371. qcom,lut-data = <0x401 0xd0 0x64 0x55 0x50 0x401 0xd0 0x64 0x55 0x50 0x408 0xe1 0x67 0x57 0x51 0x3bf 0xf9 0x6b 0x5b 0x52 0x3ba 0xf9 0x6d 0x5c 0x54 0x3b9 0xff 0x75 0x5e 0x54 0x3bd 0xe6 0x7b 0x62 0x57 0x3c8 0xd8 0x86 0x66 0x5b 0x3d7 0xd4 0x8a 0x70 0x5f 0x3ea 0xd5 0x67 0x59 0x52 0x406 0xd7 0x64 0x56 0x51 0x42a 0xdb 0x65 0x59 0x53 0x45b 0xe0 0x68 0x5c 0x55 0x49e 0xea 0x6a 0x5e 0x56 0x4ef 0xf6 0x6c 0x5c 0x54 0x54d 0x101 0x6b 0x57 0x51 0x5b8 0x105 0x66 0x55 0x50 0x61c 0x100 0x65 0x54 0x50 0x665 0x10c 0x64 0x54 0x50 0x62c 0x114 0x66 0x57 0x51 0x651 0x11d 0x68 0x57 0x52 0x686 0x12a 0x6b 0x5b 0x52 0x6bd 0x13b 0x6c 0x5c 0x53 0x6f9 0x152 0x70 0x5c 0x53 0x73a 0x169 0x6f 0x5b 0x52 0x781 0x17a 0x6c 0x59 0x54 0x7d0 0x18a 0x70 0x5c 0x57 0x847 0x1ae 0x79 0x63 0x5e 0xaeb 0x1f1 0x90 0x72 0x68 0x2241 0x40b 0x2a0 0x142 0xea>;
  9372. };
  9373. };
  9374. };
  9375. };
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