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VGA_Sync_Porch

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Jan 27th, 2021
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  1. // The purpose of this module is to modify the input HSync and VSync signals to
  2. // include some time for what is called the Front and Back porch.  The front
  3. // and back porch of a VGA interface used to have more meaning when a monitor
  4. // actually used a Cathode Ray Tube (CRT) to draw an image on the screen.  You
  5. // can read more about the details of how old VGA monitors worked.  These
  6. // days, the notion of a front and back porch is maintained, due more to
  7. // convention than to the physics of the monitor.
  8. // New standards like DVI and HDMI which are meant for digital signals have
  9. // removed this notion of the front and back porches.  Remember that VGA is an
  10. // analog interface.
  11. // This module is designed for 640x480 with a 25 MHz input clock.
  12.  
  13. module VGA_Sync_Porch #(parameter VIDEO_WIDTH = 3,  // remember to
  14.                         parameter TOTAL_COLS  = 800,  // overwrite
  15.                         parameter TOTAL_ROWS  = 525,  // these defaults
  16.                         parameter ACTIVE_COLS = 640,
  17.                         parameter ACTIVE_ROWS = 480)
  18.   (input i_Clk,
  19.    input i_HSync,
  20.    input i_VSync,
  21.    input [VIDEO_WIDTH-1:0] i_Red_Video,
  22.    input [VIDEO_WIDTH-1:0] i_Grn_Video,
  23.    input [VIDEO_WIDTH-1:0] i_Blu_Video,
  24.    output reg o_HSync,
  25.    output reg o_VSync,
  26.    output reg [VIDEO_WIDTH-1:0] o_Red_Video,
  27.    output reg [VIDEO_WIDTH-1:0] o_Grn_Video,
  28.    output reg [VIDEO_WIDTH-1:0] o_Blu_Video
  29.    );
  30.  
  31.   parameter c_FRONT_PORCH_HORZ = 18;
  32.   parameter c_BACK_PORCH_HORZ  = 50;
  33.   parameter c_FRONT_PORCH_VERT = 10;
  34.   parameter c_BACK_PORCH_VERT  = 33;
  35.  
  36.   wire w_HSync;
  37.   wire w_VSync;
  38.  
  39.   wire [9:0] w_Col_Count;
  40.   wire [9:0] w_Row_Count;
  41.  
  42.   reg [VIDEO_WIDTH-1:0] r_Red_Video = 0;
  43.   reg [VIDEO_WIDTH-1:0] r_Grn_Video = 0;
  44.   reg [VIDEO_WIDTH-1:0] r_Blu_Video = 0;
  45.  
  46.   Sync_To_Count #(.TOTAL_COLS(TOTAL_COLS),
  47.                   .TOTAL_ROWS(TOTAL_ROWS)) UUT
  48.   (.i_Clk      (i_Clk),
  49.    .i_HSync    (i_HSync),
  50.    .i_VSync    (i_VSync),
  51.    .o_HSync    (w_HSync),
  52.    .o_VSync    (w_VSync),
  53.    .o_Col_Count(w_Col_Count),
  54.    .o_Row_Count(w_Row_Count)
  55.   );
  56.      
  57.   // Purpose: Modifies the HSync and VSync signals to include Front/Back Porch
  58.   always @(posedge i_Clk)
  59.   begin
  60.     if ((w_Col_Count < c_FRONT_PORCH_HORZ + ACTIVE_COLS) ||
  61.         (w_Col_Count > TOTAL_COLS - c_BACK_PORCH_HORZ - 1))
  62.       o_HSync <= 1'b1;
  63.     else
  64.       o_HSync <= w_HSync;
  65.    
  66.     if ((w_Row_Count < c_FRONT_PORCH_VERT + ACTIVE_ROWS) ||
  67.         (w_Row_Count > TOTAL_ROWS - c_BACK_PORCH_VERT - 1))
  68.       o_VSync <= 1'b1;
  69.     else
  70.       o_VSync <= w_VSync;
  71.   end
  72.  
  73.  
  74.   // Purpose: Align input video to modified Sync pulses.
  75.   // Adds in 2 Clock Cycles of Delay
  76.   always @(posedge i_Clk)
  77.   begin
  78.     r_Red_Video <= i_Red_Video;
  79.     r_Grn_Video <= i_Grn_Video;
  80.     r_Blu_Video <= i_Blu_Video;
  81.  
  82.     o_Red_Video <= r_Red_Video;
  83.     o_Grn_Video <= r_Grn_Video;
  84.     o_Blu_Video <= r_Blu_Video;
  85.   end
  86.  
  87. endmodule
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