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  1.  
  2. ; Check banksel stuff, could be causing issues
  3. ;
  4.  
  5. ; do not change BCM_BITS, its always 8
  6. BCM_BITS     equ 8
  7.  
  8. BCM_CHANNELS equ 8
  9. BCM_BYTES    equ (BCM_CHANNELS+7)/8
  10.  
  11.     messg "BCM_BYTES" #v(BCM_BYTES)
  12.  
  13. bcm_variables macro
  14. bcm_slices         res BCM_BITS*BCM_BYTES
  15. bcm_slices_dbuf    res BCM_BITS*BCM_BYTES
  16. bcm_intensity      res BCM_CHANNELS
  17. ; local variables
  18. bcm_portbits       res 1
  19. bcm_bitvalue       res 1
  20. bcm_bitpos         res 1
  21.     endm
  22.    
  23. bcm_correct_data macro ; gamma correction array
  24. bcm_correct_table
  25.         db   0,   1,   1,   1,   1,   1,   1,   1
  26.         db   1,   1,   1,   1,   1,   1,   1,   1
  27.         db   1,   1,   1,   1,   1,   1,   1,   1
  28.         db   1,   1,   1,   1,   2,   2,   2,   2
  29.         db   2,   2,   2,   2,   2,   2,   2,   2
  30.         db   2,   2,   2,   2,   2,   2,   2,   2
  31.         db   2,   2,   2,   2,   2,   2,   2,   2
  32.         db   2,   3,   3,   3,   3,   3,   3,   3
  33.         db   3,   3,   3,   3,   3,   3,   3,   3
  34.         db   3,   3,   4,   4,   4,   4,   4,   4
  35.         db   4,   4,   4,   4,   4,   4,   5,   5
  36.         db   5,   5,   5,   5,   5,   5,   5,   6
  37.         db   6,   6,   6,   6,   6,   6,   6,   7
  38.         db   7,   7,   7,   7,   7,   7,   8,   8
  39.         db   8,   8,   8,   9,   9,   9,   9,   9
  40.         db  10,  10,  10,  10,  10,  11,  11,  11
  41.         db  11,  12,  12,  12,  13,  13,  13,  13
  42.         db  14,  14,  14,  15,  15,  15,  16,  16
  43.         db  16,  17,  17,  18,  18,  19,  19,  19
  44.         db  20,  20,  21,  21,  22,  22,  23,  23
  45.         db  24,  25,  25,  26,  26,  27,  28,  28
  46.         db  29,  30,  30,  31,  32,  33,  34,  34
  47.         db  35,  36,  37,  38,  39,  40,  41,  42
  48.         db  43,  44,  45,  46,  47,  48,  49,  51
  49.         db  52,  53,  55,  56,  57,  59,  60,  62
  50.         db  63,  65,  67,  68,  70,  72,  73,  75
  51.         db  77,  79,  81,  83,  85,  88,  90,  92
  52.         db  94,  97,  99, 102, 104, 107, 110, 113
  53.         db 116, 118, 122, 125, 128, 131, 135, 138
  54.         db 142, 145, 149, 153, 157, 161, 165, 169
  55.         db 174, 178, 183, 188, 193, 198, 203, 208
  56.         db 214, 219, 225, 231, 237, 243, 249, 255
  57.     endm
  58.  
  59. bcm_init macro
  60.    
  61.     BANKSEL bcm_slices
  62.    
  63.     CLRF bcm_bitpos, ACCESS
  64.     CLRF bcm_bitvalue, ACCESS
  65.     CLRF bcm_portbits, ACCESS
  66.    
  67.     LFSR FSR0, bcm_slices
  68.     LFSR FSR1, bcm_slices_dbuf
  69.     LFSR FSR2, bcm_intensity
  70.    
  71.     variable i
  72. i = 0
  73.  
  74.     while(i < BCM_CHANNELS)
  75.  
  76.     if(i < BCM_BITS)
  77.     CLRF POSTINC0
  78.     CLRF POSTINC1
  79.     endif
  80.    
  81.     CLRF POSTINC2
  82. i++
  83.     endw
  84.    
  85.     ; init timer and (possibly) compare shit here
  86.    
  87.     BANKSEL PIE1
  88.     BSF PIE1, TMR2IE ; enable timer2 match interrupt
  89.    
  90.     ; only nesesary if the initial intensity is anything other than 0
  91.     ;bcm_encode_slices ; encode initial timeslices
  92.    
  93.     CLRF TMR2  ; TMR2 = 0
  94.     BSF PR2, 0x01 ; PR2  = 1
  95.    
  96.     MOVLW B'00100011' ; postscaler 4x, timer off, prescaler 16x
  97.     MOVWF T2CON
  98.    
  99.     BSF T2CON, TMR2ON ; enable timer
  100.    
  101.     endm
  102.  
  103. bcm_set_intensity_lit macro output, intensity
  104.     BANKSEL bcm_intensity
  105.     LFSR  FSR2, bcm_intensity
  106.     MOVLW output
  107.     MOVFF intensity, PLUSW2
  108.     endm
  109.  
  110. bcm_encode_slices_inner_loop macro i
  111.     LFSR FSR1, bcm_intensity
  112.  
  113.     variable j
  114. j = 0
  115.    
  116.     while(j < BCM_CHANNELS)
  117.    
  118.     local bcm_encode_skip_or_#v(i)_#v(j)
  119.  
  120.     MOVLW UPPER bcm_correct_table ; load up TBLPTR
  121.     MOVWF TBLPTRU, ACCESS
  122.     MOVLW HIGH bcm_correct_table
  123.     MOVWF TBLPTRH, ACCESS
  124.     MOVLW LOW bcm_correct_table
  125.     MOVWF TBLPTRL, ACCESS
  126.    
  127.     BANKSEL bcm_intensity
  128.     MOVLW j
  129.  
  130.     ;if j==0
  131.     ;eusart_writeln_int PLUSW1
  132.     ;endif
  133.    
  134.     MOVLW j
  135.     MOVF PLUSW1, W, ACCESS
  136.  
  137.     ; add bcm_intensity[i] to TBLPTR with carry
  138.     ADDWF TBLPTRL, f, ACCESS
  139.     CLRF WREG
  140.     ADDWFC TBLPTRH, f, ACCESS
  141.     ADDWFC TBLPTRU, f, ACCESS
  142.    
  143.     TBLRD * ; grab corrected value and return in TABLAT
  144.     MOVFF TABLAT, WREG
  145.    
  146.     ;BANKSEL STATUS
  147.    
  148.     ;MOVF POSTINC1, W, ACCESS
  149.     ANDLW (0x01 << i)
  150.                                                   ; if W is 0
  151.     bz bcm_encode_skip_or_#v(i)_#v(j) ; skip IORWF
  152.  
  153. ;   MOVLW (0x01 << j)
  154. ;   IORWF bcm_portbits, f, ACCESS
  155.    
  156. ;   BANKSEL bcm_bitvalue
  157.     MOVFF bcm_bitvalue, WREG ; bcm_portbits |= bcm_bitvalue
  158.     IORWF bcm_portbits, f, ACCESS
  159.  
  160. bcm_encode_skip_or_#v(i)_#v(j)
  161.  
  162.     ;BANKSEL STATUS
  163.     BCF STATUS, C     ; clear carry, makes the rotate op a plain shift op
  164.     BANKSEL bcm_bitvalue
  165.     RLCF bcm_bitvalue, f, ACCESS
  166.  
  167. j++
  168.     endw
  169.     endm
  170.    
  171. bcm_encode_slices macro
  172.    
  173.     ; might need to stop the timer here, just to be sure?
  174.     ; at the very least, its probably a good idea to reset the TMR2/PR2 registers.
  175.    
  176.     variable i
  177. i = 0
  178.    
  179.     BANKSEL bcm_slices
  180.    
  181.     LFSR FSR0, bcm_slices_dbuf
  182.    
  183.     while(i < BCM_BITS)
  184.    
  185.     MOVLW 0x00
  186.     MOVWF bcm_portbits, ACCESS
  187.     MOVLW 0x01
  188.     MOVWF bcm_bitvalue, ACCESS
  189.        
  190.     bcm_encode_slices_inner_loop i
  191.    
  192.     MOVLW i
  193.     MOVFF bcm_portbits, PLUSW0
  194.    
  195. i++
  196.     endw
  197.  
  198.     LFSR FSR2, bcm_slices
  199.    
  200. i=0
  201.     while(i < BCM_BITS)
  202.         MOVLW i
  203.         MOVFF PLUSW0, PLUSW2
  204. i++
  205.     endw
  206.  
  207.     endm
  208.  
  209. bcm_write macro
  210.     ; if BCM_BYTES == 1 ; shortcut for 8 channels or less
  211.     BANKSEL bcm_slices
  212.     LFSR FSR2, bcm_slices
  213.     MOVFF bcm_bitpos, WREG
  214.     sr_write 1, PLUSW2 ; sr_write(bcm_slices[bcm_bitpos])
  215.    
  216.     ;BTG PORTE, RE1 ; toggle status led
  217.     ; else
  218.     ;   fill shit in later
  219.     ; endif
  220.     endm
  221.  
  222. ; timer2 stuff
  223. ; -------------
  224. ;
  225. ; prescaler slows down the internal increment rate up to 16 times
  226. ; postscaler slows down the external TMR2:PR2 match interupt rate by up to 16 times
  227. ;
  228. ; prescaler set to 16x
  229. ; postscaler set to 4x
  230. ; scalers to equal a 64x minimum delay
  231. ; this should give a refresh of 488hz
  232. ;
  233.  
  234. bcm_isr macro
  235.     local bcm_isr_update_match
  236.     local bcm_isr_end
  237.     local bcm_isr_end_write
  238.    
  239.     BANKSEL PIR1
  240.     BTFSS PIR1, TMR2IF ; if TMR2IF is set, skip the following branch, and run isr code
  241.     bra bcm_isr_end    ; if TMR2IF is NOT set, branch to end of bcm isr code
  242.  
  243.     banksel PORTE
  244.     BTG PORTE, RE1, A ; toggle status led
  245.    
  246.     ; this is wrong, and I don't know why :(
  247.     ;banksel bcm_slices
  248.     ;bcm_write ; write current value
  249.    
  250.     ;BANKSEL TMR2
  251.     ;CLRF TMR2 ; clear TMR2 counter
  252.  
  253.     BANKSEL bcm_bitpos
  254.     INCF bcm_bitpos, F, ACCESS     ; bcm_bitpos++
  255.    
  256.     MOVLW 0x07
  257.     ANDWF bcm_bitpos, F, ACCESS ; bcm_bitpos &= 7
  258.  
  259.     ;TSTFSZ bcm_bitpos        ; if not zero, update match register
  260.     ;bra bcm_isr_update_match ; else reset
  261.     bnz bcm_isr_update_match ; else reset TMR2:PR2
  262.  
  263.     BANKSEL PR2
  264.     MOVLW 0x01
  265.     MOVWF PR2, ACCESS
  266.    
  267.     bra bcm_isr_end_write ; stop processing macro, aka skip the bitpos reset
  268.  
  269. bcm_isr_update_match
  270.     ; setup delay
  271.  
  272.     BANKSEL STATUS
  273.     BCF  STATUS, C, ACCESS ; clear carry to turn rotate op into pure shift op
  274.     RLCF PR2, f, ACCESS       ; PR2 <<= 1
  275.  
  276. bcm_isr_end_write
  277.     bcm_write
  278.     CLRF TMR2 ; clear TMR2 counter
  279.  
  280. bcm_isr_end
  281.  
  282.     BCF PIR1, TMR2IF
  283.    
  284.     endm
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