jamie@t2:/tmp$ cat minimal_demo.py



from migen import *
from migen.fhdl.verilog import convert

class Test(Module):
    def __init__(self):
        self.A = Signal(4)
        self.B = Signal(4)
        self.out = Signal()
        self.out2 = Signal()
        self.comb += [
            If(self.A==7, If(self.B==4, self.out.eq(1))).Else(self.out.eq(0)),
            If(wrap(self.A==7) & wrap(self.B==4), self.out2.eq(1)).Else(self.out2.eq(0)),
        ]

t = Test()
ios=set([t.A, t.B, t.out, t.out2])
convert(t, ios=ios).write("demo.v")
jamie@t2:/tmp$ cat demo.v
/* Machine-generated using Migen */
module top(
        output reg demoSignal,
        output reg demoDefaultHighSignal,
        input sys_clk,
        output reg sys_rst
);



always @(posedge sys_clk) begin
        demoSignal <= 1'd1;
        demoDefaultHighSignal <= 1'd0;
        sys_rst <= 1'd1;
        if (sys_rst) begin
                demoSignal <= 1'd0;
                demoDefaultHighSignal <= 1'd1;
        end
end

endmodule
jamie@t2:/tmp$