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Robertson Multiplier Synthesis

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  1. Release 14.5 - xst P.58f (nt64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. --> Parameter TMPDIR set to xst/projnav.tmp
  4.  
  5.  
  6. Total REAL time to Xst completion: 0.00 secs
  7. Total CPU time to Xst completion: 0.16 secs
  8.  
  9. --> Parameter xsthdpdir set to xst
  10.  
  11.  
  12. Total REAL time to Xst completion: 0.00 secs
  13. Total CPU time to Xst completion: 0.16 secs
  14.  
  15. --> Reading design: robertson.prj
  16.  
  17. TABLE OF CONTENTS
  18. 1) Synthesis Options Summary
  19. 2) HDL Compilation
  20. 3) Design Hierarchy Analysis
  21. 4) HDL Analysis
  22. 5) HDL Synthesis
  23. 5.1) HDL Synthesis Report
  24. 6) Advanced HDL Synthesis
  25. 6.1) Advanced HDL Synthesis Report
  26. 7) Low Level Synthesis
  27. 8) Partition Report
  28. 9) Final Report
  29. 9.1) Device utilization summary
  30. 9.2) Partition Resource Summary
  31. 9.3) TIMING REPORT
  32.  
  33.  
  34. =========================================================================
  35. * Synthesis Options Summary *
  36. =========================================================================
  37. ---- Source Parameters
  38. Input File Name : "robertson.prj"
  39. Input Format : mixed
  40. Ignore Synthesis Constraint File : NO
  41.  
  42. ---- Target Parameters
  43. Output File Name : "robertson"
  44. Output Format : NGC
  45. Target Device : xc3s250e-4-tq144
  46.  
  47. ---- Source Options
  48. Top Module Name : robertson
  49. Automatic FSM Extraction : YES
  50. FSM Encoding Algorithm : Auto
  51. Safe Implementation : No
  52. FSM Style : LUT
  53. RAM Extraction : Yes
  54. RAM Style : Auto
  55. ROM Extraction : Yes
  56. Mux Style : Auto
  57. Decoder Extraction : YES
  58. Priority Encoder Extraction : Yes
  59. Shift Register Extraction : YES
  60. Logical Shifter Extraction : YES
  61. XOR Collapsing : YES
  62. ROM Style : Auto
  63. Mux Extraction : Yes
  64. Resource Sharing : YES
  65. Asynchronous To Synchronous : NO
  66. Multiplier Style : Auto
  67. Automatic Register Balancing : No
  68.  
  69. ---- Target Options
  70. Add IO Buffers : YES
  71. Global Maximum Fanout : 100000
  72. Add Generic Clock Buffer(BUFG) : 24
  73. Register Duplication : YES
  74. Slice Packing : YES
  75. Optimize Instantiated Primitives : NO
  76. Use Clock Enable : Yes
  77. Use Synchronous Set : Yes
  78. Use Synchronous Reset : Yes
  79. Pack IO Registers into IOBs : Auto
  80. Equivalent register Removal : YES
  81.  
  82. ---- General Options
  83. Optimization Goal : Speed
  84. Optimization Effort : 1
  85. Keep Hierarchy : No
  86. Netlist Hierarchy : As_Optimized
  87. RTL Output : Yes
  88. Global Optimization : AllClockNets
  89. Read Cores : YES
  90. Write Timing Constraints : NO
  91. Cross Clock Analysis : NO
  92. Hierarchy Separator : /
  93. Bus Delimiter : <>
  94. Case Specifier : Maintain
  95. Slice Utilization Ratio : 100
  96. BRAM Utilization Ratio : 100
  97. Verilog 2001 : YES
  98. Auto BRAM Packing : NO
  99. Slice Utilization Ratio Delta : 5
  100.  
  101. =========================================================================
  102.  
  103.  
  104. =========================================================================
  105. * HDL Compilation *
  106. =========================================================================
  107. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/counter_mod_N/log_functions.vhd" in Library work.
  108. Architecture log_functions of Entity log_functions is up to date.
  109. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/full_adder.vhd" in Library work.
  110. Architecture dataflow of Entity full_adder is up to date.
  111. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/xor2.vhd" in Library work.
  112. Architecture behavioral of Entity xor_2 is up to date.
  113. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/mux-generic/mux.vhd" in Library work.
  114. Architecture dataflow of Entity mux is up to date.
  115. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/Flip flop/D Edge triggered fronte di salita (behavioral)/FlipFlopD_EdgeTriggered_Salita.vhd" in Library work.
  116. Architecture behavioral of Entity flipflopd_edgetriggered_salita is up to date.
  117. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/xor-generic.vhd" in Library work.
  118. Architecture structural of Entity xor_generic is up to date.
  119. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA-generic/RCA.vhd" in Library work.
  120. Architecture structural of Entity rca is up to date.
  121. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/shift_register/flipflop_mux.vhd" in Library work.
  122. Architecture structural of Entity flipflop_mux is up to date.
  123. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/shift_register/shift_register.vhd" in Library work.
  124. Architecture structural of Entity shift_register is up to date.
  125. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/reg_clock/reg_clock.vhd" in Library work.
  126. Architecture behavioral of Entity reg_clock is up to date.
  127. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/RCAdd-Sub.vhd" in Library work.
  128. Architecture structural of Entity rcadd_sub is up to date.
  129. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/counter_mod_N/counter_mod_N.vhd" in Library work.
  130. Architecture behavioral of Entity counter_mod_n is up to date.
  131. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/robertson/control_unit.vhd" in Library work.
  132. Entity <control_unit_robertson> compiled.
  133. Entity <control_unit_robertson> (Architecture <Behavioral>) compiled.
  134. Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/robertson/robertson.vhd" in Library work.
  135. Entity <robertson> compiled.
  136. Entity <robertson> (Architecture <structural>) compiled.
  137.  
  138. =========================================================================
  139. * Design Hierarchy Analysis *
  140. =========================================================================
  141. Analyzing hierarchy for entity <robertson> in library <work> (architecture <structural>) with generics.
  142. N = 8
  143.  
  144. Analyzing hierarchy for entity <shift_register> in library <work> (architecture <structural>) with generics.
  145. right_left_n_shift = '1'
  146. width = 8
  147.  
  148. Analyzing hierarchy for entity <reg_clock> in library <work> (architecture <behavioral>) with generics.
  149. N = 8
  150.  
  151. Analyzing hierarchy for entity <FlipFlopD_EdgeTriggered_Salita> in library <work> (architecture <behavioral>).
  152.  
  153. Analyzing hierarchy for entity <RCAdd_Sub> in library <work> (architecture <structural>) with generics.
  154. N = 8
  155.  
  156. Analyzing hierarchy for entity <mux> in library <work> (architecture <dataflow>) with generics.
  157. N_signals = 2
  158. input_width = 8
  159.  
  160. Analyzing hierarchy for entity <counter_mod_N> in library <work> (architecture <behavioral>) with generics.
  161. count_max = 8
  162.  
  163. Analyzing hierarchy for entity <control_unit_robertson> in library <work> (architecture <Behavioral>).
  164.  
  165. Analyzing hierarchy for entity <flipflop_mux> in library <work> (architecture <structural>).
  166.  
  167. Analyzing hierarchy for entity <xor_generic> in library <work> (architecture <structural>) with generics.
  168. N = 8
  169.  
  170. Analyzing hierarchy for entity <RCA> in library <work> (architecture <structural>) with generics.
  171. N = 8
  172.  
  173. Analyzing hierarchy for entity <mux> in library <work> (architecture <dataflow>) with generics.
  174. N_signals = 2
  175. input_width = 1
  176.  
  177. Analyzing hierarchy for entity <FlipFlopD_EdgeTriggered_Salita> in library <work> (architecture <behavioral>).
  178.  
  179. Analyzing hierarchy for entity <xor_2> in library <work> (architecture <behavioral>).
  180.  
  181. Analyzing hierarchy for entity <full_adder> in library <work> (architecture <dataflow>).
  182.  
  183.  
  184. =========================================================================
  185. * HDL Analysis *
  186. =========================================================================
  187. Analyzing generic Entity <robertson> in library <work> (Architecture <structural>).
  188. N = 8
  189. WARNING:Xst:753 - "C:/Users/Alessandro/Desktop/ASE/robertson/robertson.vhd" line 191: Unconnected output port 'scan_out' of component 'shift_register'.
  190. WARNING:Xst:753 - "C:/Users/Alessandro/Desktop/ASE/robertson/robertson.vhd" line 211: Unconnected output port 'nQ' of component 'FlipFlopD_EdgeTriggered_Salita'.
  191. WARNING:Xst:753 - "C:/Users/Alessandro/Desktop/ASE/robertson/robertson.vhd" line 220: Unconnected output port 'carry_out' of component 'RCAdd_Sub'.
  192. WARNING:Xst:753 - "C:/Users/Alessandro/Desktop/ASE/robertson/robertson.vhd" line 220: Unconnected output port 'overflow' of component 'RCAdd_Sub'.
  193. WARNING:Xst:753 - "C:/Users/Alessandro/Desktop/ASE/robertson/robertson.vhd" line 235: Unconnected output port 'counter' of component 'counter_mod_N'.
  194. Entity <robertson> analyzed. Unit <robertson> generated.
  195.  
  196. Analyzing generic Entity <shift_register> in library <work> (Architecture <structural>).
  197. right_left_n_shift = '1'
  198. width = 8
  199. Entity <shift_register> analyzed. Unit <shift_register> generated.
  200.  
  201. Analyzing Entity <flipflop_mux> in library <work> (Architecture <structural>).
  202. WARNING:Xst:753 - "C:/Users/Alessandro/Desktop/ASE/shift_register/flipflop_mux.vhd" line 79: Unconnected output port 'nQ' of component 'FlipFlopD_EdgeTriggered_Salita'.
  203. Entity <flipflop_mux> analyzed. Unit <flipflop_mux> generated.
  204.  
  205. Analyzing generic Entity <mux.2> in library <work> (Architecture <dataflow>).
  206. N_signals = 2
  207. input_width = 1
  208. WARNING:Xst:1610 - "C:/Users/Alessandro/Desktop/ASE/mux-generic/mux.vhd" line 47: Width mismatch. <outputs> has a width of 1 bits but assigned expression is 2-bit wide.
  209. Entity <mux.2> analyzed. Unit <mux.2> generated.
  210.  
  211. Analyzing generic Entity <reg_clock> in library <work> (Architecture <behavioral>).
  212. N = 8
  213. Entity <reg_clock> analyzed. Unit <reg_clock> generated.
  214.  
  215. Analyzing Entity <FlipFlopD_EdgeTriggered_Salita> in library <work> (Architecture <behavioral>).
  216. Entity <FlipFlopD_EdgeTriggered_Salita> analyzed. Unit <FlipFlopD_EdgeTriggered_Salita> generated.
  217.  
  218. Analyzing generic Entity <RCAdd_Sub> in library <work> (Architecture <structural>).
  219. N = 8
  220. Entity <RCAdd_Sub> analyzed. Unit <RCAdd_Sub> generated.
  221.  
  222. Analyzing generic Entity <xor_generic> in library <work> (Architecture <structural>).
  223. N = 8
  224. Entity <xor_generic> analyzed. Unit <xor_generic> generated.
  225.  
  226. Analyzing Entity <xor_2> in library <work> (Architecture <behavioral>).
  227. Entity <xor_2> analyzed. Unit <xor_2> generated.
  228.  
  229. Analyzing generic Entity <RCA> in library <work> (Architecture <structural>).
  230. N = 8
  231. Entity <RCA> analyzed. Unit <RCA> generated.
  232.  
  233. Analyzing Entity <full_adder> in library <work> (Architecture <dataflow>).
  234. Entity <full_adder> analyzed. Unit <full_adder> generated.
  235.  
  236. Analyzing generic Entity <mux.1> in library <work> (Architecture <dataflow>).
  237. N_signals = 2
  238. input_width = 8
  239. WARNING:Xst:1610 - "C:/Users/Alessandro/Desktop/ASE/mux-generic/mux.vhd" line 47: Width mismatch. <outputs> has a width of 8 bits but assigned expression is 16-bit wide.
  240. Entity <mux.1> analyzed. Unit <mux.1> generated.
  241.  
  242. Analyzing generic Entity <counter_mod_N> in library <work> (Architecture <behavioral>).
  243. count_max = 8
  244. Entity <counter_mod_N> analyzed. Unit <counter_mod_N> generated.
  245.  
  246. Analyzing Entity <control_unit_robertson> in library <work> (Architecture <Behavioral>).
  247. Entity <control_unit_robertson> analyzed. Unit <control_unit_robertson> generated.
  248.  
  249.  
  250. =========================================================================
  251. * HDL Synthesis *
  252. =========================================================================
  253.  
  254. Performing bidirectional port resolution...
  255.  
  256. Synthesizing Unit <reg_clock>.
  257. Related source file is "C:/Users/Alessandro/Desktop/ASE/reg_clock/reg_clock.vhd".
  258. Found 8-bit register for signal <reg>.
  259. Summary:
  260. inferred 8 D-type flip-flop(s).
  261. Unit <reg_clock> synthesized.
  262.  
  263.  
  264. Synthesizing Unit <FlipFlopD_EdgeTriggered_Salita>.
  265. Related source file is "C:/Users/Alessandro/Desktop/ASE/Flip flop/D Edge triggered fronte di salita (behavioral)/FlipFlopD_EdgeTriggered_Salita.vhd".
  266. Found 1-bit register for signal <Q>.
  267. Found 1-bit register for signal <nQ>.
  268. Summary:
  269. inferred 2 D-type flip-flop(s).
  270. Unit <FlipFlopD_EdgeTriggered_Salita> synthesized.
  271.  
  272.  
  273. Synthesizing Unit <mux_1>.
  274. Related source file is "C:/Users/Alessandro/Desktop/ASE/mux-generic/mux.vhd".
  275. Found 1-bit adder carry out for signal <outputs$addsub0000> created at line 47.
  276. Summary:
  277. inferred 1 Adder/Subtractor(s).
  278. Unit <mux_1> synthesized.
  279.  
  280.  
  281. Synthesizing Unit <counter_mod_N>.
  282. Related source file is "C:/Users/Alessandro/Desktop/ASE/counter_mod_N/counter_mod_N.vhd".
  283. Found 3-bit up counter for signal <cont>.
  284. Found 3-bit comparator less for signal <cont$cmp_lt0000> created at line 66.
  285. Summary:
  286. inferred 1 Counter(s).
  287. inferred 1 Comparator(s).
  288. Unit <counter_mod_N> synthesized.
  289.  
  290.  
  291. Synthesizing Unit <control_unit_robertson>.
  292. Related source file is "C:/Users/Alessandro/Desktop/ASE/robertson/control_unit.vhd".
  293. Found finite state machine <FSM_0> for signal <current_state>.
  294. -----------------------------------------------------------------------
  295. | States | 7 |
  296. | Transitions | 10 |
  297. | Inputs | 3 |
  298. | Outputs | 10 |
  299. | Clock | clock (rising_edge) |
  300. | Reset | reset_n (negative) |
  301. | Reset type | asynchronous |
  302. | Reset State | idle |
  303. | Power Up State | idle |
  304. | Encoding | automatic |
  305. | Implementation | LUT |
  306. -----------------------------------------------------------------------
  307. Summary:
  308. inferred 1 Finite State Machine(s).
  309. Unit <control_unit_robertson> synthesized.
  310.  
  311.  
  312. Synthesizing Unit <mux_2>.
  313. Related source file is "C:/Users/Alessandro/Desktop/ASE/mux-generic/mux.vhd".
  314. Found 1-bit adder carry out for signal <outputs$addsub0000> created at line 47.
  315. Summary:
  316. inferred 1 Adder/Subtractor(s).
  317. Unit <mux_2> synthesized.
  318.  
  319.  
  320. Synthesizing Unit <xor_2>.
  321. Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/xor2.vhd".
  322. Found 1-bit xor2 for signal <s>.
  323. Unit <xor_2> synthesized.
  324.  
  325.  
  326. Synthesizing Unit <full_adder>.
  327. Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/full_adder.vhd".
  328. Found 1-bit xor2 for signal <s>.
  329. Found 1-bit xor2 for signal <c_out$xor0000> created at line 45.
  330. Unit <full_adder> synthesized.
  331.  
  332.  
  333. Synthesizing Unit <flipflop_mux>.
  334. Related source file is "C:/Users/Alessandro/Desktop/ASE/shift_register/flipflop_mux.vhd".
  335. Unit <flipflop_mux> synthesized.
  336.  
  337.  
  338. Synthesizing Unit <xor_generic>.
  339. Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/xor-generic.vhd".
  340. Unit <xor_generic> synthesized.
  341.  
  342.  
  343. Synthesizing Unit <RCA>.
  344. Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA-generic/RCA.vhd".
  345. Found 1-bit xor2 for signal <v>.
  346. Unit <RCA> synthesized.
  347.  
  348.  
  349. Synthesizing Unit <shift_register>.
  350. Related source file is "C:/Users/Alessandro/Desktop/ASE/shift_register/shift_register.vhd".
  351. Unit <shift_register> synthesized.
  352.  
  353.  
  354. Synthesizing Unit <RCAdd_Sub>.
  355. Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/RCAdd-Sub.vhd".
  356. WARNING:Xst:1780 - Signal <carry_temp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  357. Unit <RCAdd_Sub> synthesized.
  358.  
  359.  
  360. Synthesizing Unit <robertson>.
  361. Related source file is "C:/Users/Alessandro/Desktop/ASE/robertson/robertson.vhd".
  362. WARNING:Xst:1780 - Signal <m7> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  363. Unit <robertson> synthesized.
  364.  
  365.  
  366. =========================================================================
  367. HDL Synthesis Report
  368.  
  369. Macro Statistics
  370. # Adders/Subtractors : 17
  371. 1-bit adder carry out : 17
  372. # Counters : 1
  373. 3-bit up counter : 1
  374. # Registers : 35
  375. 1-bit register : 34
  376. 8-bit register : 1
  377. # Comparators : 1
  378. 3-bit comparator less : 1
  379. # Xors : 25
  380. 1-bit xor2 : 25
  381.  
  382. =========================================================================
  383.  
  384. =========================================================================
  385. * Advanced HDL Synthesis *
  386. =========================================================================
  387.  
  388. Analyzing FSM <FSM_0> for best encoding.
  389. Optimizing FSM <CU/current_state/FSM> on signal <current_state[1:7]> with one-hot encoding.
  390. --------------------------
  391. State | Encoding
  392. --------------------------
  393. idle | 0000001
  394. init | 0000010
  395. choice | 0000100
  396. rshift | 0001000
  397. add | 0010000
  398. sub | 0100000
  399. final_rshift | 1000000
  400. --------------------------
  401.  
  402. =========================================================================
  403. Advanced HDL Synthesis Report
  404.  
  405. Macro Statistics
  406. # FSMs : 1
  407. # Adders/Subtractors : 17
  408. 1-bit adder carry out : 17
  409. # Counters : 1
  410. 3-bit up counter : 1
  411. # Registers : 42
  412. Flip-Flops : 42
  413. # Comparators : 1
  414. 3-bit comparator less : 1
  415. # Xors : 25
  416. 1-bit xor2 : 25
  417.  
  418. =========================================================================
  419.  
  420. =========================================================================
  421. * Low Level Synthesis *
  422. =========================================================================
  423. WARNING:Xst:2677 - Node <shift_register[7].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  424. WARNING:Xst:2677 - Node <shift_register[6].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  425. WARNING:Xst:2677 - Node <shift_register[5].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  426. WARNING:Xst:2677 - Node <shift_register[4].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  427. WARNING:Xst:2677 - Node <shift_register[3].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  428. WARNING:Xst:2677 - Node <shift_register[2].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  429. WARNING:Xst:2677 - Node <shift_register[1].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  430. WARNING:Xst:2677 - Node <shift_register[0].right_shift.ffmux/ff/nQ> of sequential type is unconnected in block <shift_register>.
  431. WARNING:Xst:2677 - Node <F/nQ> of sequential type is unconnected in block <robertson>.
  432.  
  433. Optimizing unit <robertson> ...
  434.  
  435. Optimizing unit <reg_clock> ...
  436.  
  437. Optimizing unit <RCA> ...
  438.  
  439. Optimizing unit <shift_register> ...
  440.  
  441. Mapping all equations...
  442. Building and optimizing final netlist ...
  443. Found area constraint ratio of 100 (+ 5) on block robertson, actual ratio is 1.
  444.  
  445. Final Macro Processing ...
  446.  
  447. =========================================================================
  448. Final Register Report
  449.  
  450. Macro Statistics
  451. # Registers : 35
  452. Flip-Flops : 35
  453.  
  454. =========================================================================
  455.  
  456. =========================================================================
  457. * Partition Report *
  458. =========================================================================
  459.  
  460. Partition Implementation Status
  461. -------------------------------
  462.  
  463. No Partitions were found in this design.
  464.  
  465. -------------------------------
  466.  
  467. =========================================================================
  468. * Final Report *
  469. =========================================================================
  470. Final Results
  471. RTL Top Level Output File Name : robertson.ngr
  472. Top Level Output File Name : robertson
  473. Output Format : NGC
  474. Optimization Goal : Speed
  475. Keep Hierarchy : No
  476.  
  477. Design Statistics
  478. # IOs : 37
  479.  
  480. Cell Usage :
  481. # BELS : 81
  482. # INV : 2
  483. # LUT2 : 7
  484. # LUT2_D : 1
  485. # LUT2_L : 2
  486. # LUT3 : 16
  487. # LUT3_D : 1
  488. # LUT4 : 37
  489. # LUT4_D : 6
  490. # LUT4_L : 3
  491. # MUXF5 : 5
  492. # VCC : 1
  493. # FlipFlops/Latches : 35
  494. # FDC : 6
  495. # FDCE : 28
  496. # FDP : 1
  497. # Clock Buffers : 1
  498. # BUFGP : 1
  499. # IO Buffers : 36
  500. # IBUF : 18
  501. # OBUF : 18
  502. =========================================================================
  503.  
  504. Device utilization summary:
  505. ---------------------------
  506.  
  507. Selected Device : 3s250etq144-4
  508.  
  509. Number of Slices: 39 out of 2448 1%
  510. Number of Slice Flip Flops: 35 out of 4896 0%
  511. Number of 4 input LUTs: 75 out of 4896 1%
  512. Number of IOs: 37
  513. Number of bonded IOBs: 37 out of 108 34%
  514. Number of GCLKs: 1 out of 24 4%
  515.  
  516. ---------------------------
  517. Partition Resource Summary:
  518. ---------------------------
  519.  
  520. No Partitions were found in this design.
  521.  
  522. ---------------------------
  523.  
  524.  
  525. =========================================================================
  526. TIMING REPORT
  527.  
  528. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  529. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  530. GENERATED AFTER PLACE-and-ROUTE.
  531.  
  532. Clock Information:
  533. ------------------
  534. -----------------------------------+------------------------+-------+
  535. Clock Signal | Clock buffer(FF name) | Load |
  536. -----------------------------------+------------------------+-------+
  537. clock | BUFGP | 35 |
  538. -----------------------------------+------------------------+-------+
  539.  
  540. Asynchronous Control Signals Information:
  541. ----------------------------------------
  542. ---------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+
  543. Control Signal | Buffer(FF name) | Load |
  544. ---------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+
  545. CU/current_state_FSM_Acst_FSM_inv(Q_shift_register/shift_register[0].right_shift.ffmux/ff/reset_n_inv1_INV_0:O)| NONE(CU/current_state_FSM_FFd1) | 23 |
  546. A_shift_register/shift_register[0].right_shift.ffmux/ff/reset_n_inv(F/reset_n_inv1:O) | NONE(A_shift_register/shift_register[0].right_shift.ffmux/ff/Q)| 12 |
  547. ---------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+
  548.  
  549. Timing Summary:
  550. ---------------
  551. Speed Grade: -4
  552.  
  553. Minimum period: 7.591ns (Maximum Frequency: 131.735MHz)
  554. Minimum input arrival time before clock: 2.852ns
  555. Maximum output required time after clock: 4.846ns
  556. Maximum combinational path delay: 7.535ns
  557.  
  558. Timing Detail:
  559. --------------
  560. All values displayed in nanoseconds (ns)
  561.  
  562. =========================================================================
  563. Timing constraint: Default period analysis for Clock 'clock'
  564. Clock period: 7.591ns (frequency: 131.735MHz)
  565. Total number of paths / destination ports: 491 / 54
  566. -------------------------------------------------------------------------
  567. Delay: 7.591ns (Levels of Logic = 5)
  568. Source: Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q (FF)
  569. Destination: A_shift_register/shift_register[7].right_shift.ffmux/ff/Q (FF)
  570. Source Clock: clock rising
  571. Destination Clock: clock rising
  572.  
  573. Data Path: Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q to A_shift_register/shift_register[7].right_shift.ffmux/ff/Q
  574. Gate Net
  575. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  576. ---------------------------------------- ------------
  577. FDCE:C->Q 13 0.591 1.018 Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q (Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q)
  578. LUT4:I2->O 4 0.704 0.622 RCA_sub/xor_inst/inst[5].xor_inst/Mxor_s_Result1 (RCA_sub/temp<5>)
  579. LUT4:I2->O 2 0.704 0.482 RCA_sub/RCA_inst/f0_7[4].full_adder_instance/c_out1_SW0 (N23)
  580. LUT3:I2->O 1 0.704 0.420 RCA_sub/RCA_inst/f0_7[5].full_adder_instance/c_out1_SW0 (N29)
  581. MUXF5:S->O 1 0.739 0.595 A_shift_register/shift_register[7].right_shift.ffmux/mux_block/outputs_0_mux0000_SW0_SW0 (N38)
  582. LUT3:I0->O 1 0.704 0.000 A_shift_register/shift_register[7].right_shift.ffmux/mux_block/outputs_0_mux0000 (A_shift_register/shift_register[7].right_shift.ffmux/d_final)
  583. FDCE:D 0.308 A_shift_register/shift_register[7].right_shift.ffmux/ff/Q
  584. ----------------------------------------
  585. Total 7.591ns (4.454ns logic, 3.137ns route)
  586. (58.7% logic, 41.3% route)
  587.  
  588. =========================================================================
  589. Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
  590. Total number of paths / destination ports: 18 / 18
  591. -------------------------------------------------------------------------
  592. Offset: 2.852ns (Levels of Logic = 2)
  593. Source: start (PAD)
  594. Destination: CU/current_state_FSM_FFd7 (FF)
  595. Destination Clock: clock rising
  596.  
  597. Data Path: start to CU/current_state_FSM_FFd7
  598. Gate Net
  599. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  600. ---------------------------------------- ------------
  601. IBUF:I->O 2 1.218 0.622 start_IBUF (start_IBUF)
  602. LUT2:I0->O 1 0.704 0.000 CU/current_state_FSM_FFd6-In1 (CU/current_state_FSM_FFd6-In)
  603. FDC:D 0.308 CU/current_state_FSM_FFd6
  604. ----------------------------------------
  605. Total 2.852ns (2.230ns logic, 0.622ns route)
  606. (78.2% logic, 21.8% route)
  607.  
  608. =========================================================================
  609. Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  610. Total number of paths / destination ports: 17 / 17
  611. -------------------------------------------------------------------------
  612. Offset: 4.846ns (Levels of Logic = 1)
  613. Source: Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q (FF)
  614. Destination: result<0> (PAD)
  615. Source Clock: clock rising
  616.  
  617. Data Path: Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q to result<0>
  618. Gate Net
  619. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  620. ---------------------------------------- ------------
  621. FDCE:C->Q 13 0.591 0.983 Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q (Q_shift_register/shift_register[0].right_shift.ffmux/ff/Q)
  622. OBUF:I->O 3.272 result_0_OBUF (result<0>)
  623. ----------------------------------------
  624. Total 4.846ns (3.863ns logic, 0.983ns route)
  625. (79.7% logic, 20.3% route)
  626.  
  627. =========================================================================
  628. Timing constraint: Default path analysis
  629. Total number of paths / destination ports: 16 / 1
  630. -------------------------------------------------------------------------
  631. Delay: 7.535ns (Levels of Logic = 4)
  632. Source: X<7> (PAD)
  633. Destination: error (PAD)
  634.  
  635. Data Path: X<7> to error
  636. Gate Net
  637. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  638. ---------------------------------------- ------------
  639. IBUF:I->O 2 1.218 0.622 X_7_IBUF (X_7_IBUF)
  640. LUT4:I0->O 1 0.704 0.595 error_and000011 (error_and000011)
  641. LUT4:I0->O 1 0.704 0.420 error_and000074 (error_OBUF)
  642. OBUF:I->O 3.272 error_OBUF (error)
  643. ----------------------------------------
  644. Total 7.535ns (5.898ns logic, 1.637ns route)
  645. (78.3% logic, 21.7% route)
  646.  
  647. =========================================================================
  648.  
  649.  
  650. Total REAL time to Xst completion: 11.00 secs
  651. Total CPU time to Xst completion: 11.11 secs
  652.  
  653. -->
  654.  
  655. Total memory usage is 260524 kilobytes
  656.  
  657. Number of errors : 0 ( 0 filtered)
  658. Number of warnings : 19 ( 0 filtered)
  659. Number of infos : 0 ( 0 filtered)
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