`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.11.2019 15:47:44
// Design Name:
// Module Name: vga_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//

module vga_tb();
    reg clk = 0;
    wire hsync, vsync;
    wire [3:0] pix_r;
    wire [3:0] pix_g;
    wire [3:0] pix_b;
    reg [10:0] hcount;
    reg [9:0] vcount;

    vga_out uut (.clk(clk), .pix_r(pix_r), .pix_g(pix_g), .pix_b(pix_b), .hsync(hsync), .vsync(vsync));


    always #5 clk = ~clk;
   initial begin
/*
   $display("hcount: %d", hcount);
   $display("vcount: %d", vcount);

   #5 assign pix_r = 4'hF;
   #5 assign pix_g = 4'hF;
   #5 assign pix_b = 4'hF;
*/
    //$finish;
end



        endmodule