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  1. module verificator_main_tb();
  2.  
  3.     logic clk, rst, clk_out, rdwr, control, data_counter_flag;
  4.     logic [31:0] error_counter, data_aquired, data, slave_error, data_counter;
  5.     tri [31:0] data_line;
  6.     logic [15:0] state;
  7.    
  8.     verificator dut(clk, rst, slave_error, data_line, clk_out, error_counter, rdwr);
  9.    
  10.     verificator_slave dut1(clk, clk_out, rst, rdwr, data_line, slave_error);
  11.    
  12.    
  13.     always begin
  14.         clk = 1;
  15.         #5;
  16.         clk = 0;
  17.         #5;
  18.     end
  19.    
  20.     initial begin
  21.         #5;
  22.         rst = 1;
  23.         #5;
  24.         rst = 0;
  25.     end
  26.  
  27. endmodule
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