module verificator_main_tb();

    logic clk, rst, clk_out, rdwr, control, data_counter_flag;
    logic [31:0] error_counter, data_aquired, data, slave_error, data_counter;
    tri [31:0] data_line;
    logic [15:0] state;

    verificator dut(clk, rst, slave_error, data_line, clk_out, error_counter, rdwr);

    verificator_slave dut1(clk, clk_out, rst, rdwr, data_line, slave_error);


    always begin
        clk = 1;
        #5;
        clk = 0;
        #5;
    end

    initial begin
        #5;
        rst = 1;
        #5;
        rst = 0;
    end

endmodule