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Jan 8th, 2020
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  1. diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py
  2. index fdb48c4..f9883e1 100755
  3. --- a/litex_boards/official/targets/nexys4ddr.py
  4. +++ b/litex_boards/official/targets/nexys4ddr.py
  5. @@ -19,6 +19,12 @@ from litedram.phy import s7ddrphy
  6.  from liteeth.phy.rmii import LiteEthPHYRMII
  7.  from liteeth.mac import LiteEthMAC
  8.  
  9. +from litesdcard.phy import SDPHY
  10. +from litesdcard.clocker import SDClockerS7
  11. +from litesdcard.core import SDCore
  12. +from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
  13. +from litex.soc.cores.timer import Timer
  14. +
  15.  # CRG ----------------------------------------------------------------------------------------------
  16.  
  17.  class _CRG(Module):
  18. @@ -98,6 +104,51 @@ class EthernetSoC(BaseSoC):
  19.              self.ethphy.crg.cd_eth_rx.clk,
  20.              self.ethphy.crg.cd_eth_tx.clk)
  21.  
  22. +# SdSoC -----------------------------------------------------------------------------------------
  23. +
  24. +class SdSoC(EthernetSoC):
  25. +    csr_map = {
  26. +        "sdclk":          20,
  27. +        "sdphy":          21,
  28. +        "sdcore":         22,
  29. +        "sdtimer":        23,
  30. +        "sdemulator":     24,
  31. +        "bist_generator": 25,
  32. +        "bist_checker":   26,
  33. +        "analyzer":       30
  34. +    }
  35. +    csr_map.update(EthernetSoC.csr_map)
  36. +
  37. +    def __init__(self, **kwargs):
  38. +        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
  39. +
  40. +        # SDcard
  41. +        sdcard_pads = self.platform.request("sdcard")
  42. +        self.submodules.sdclk = SDClockerS7()
  43. +        self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device)
  44. +        self.submodules.sdcore = SDCore(self.sdphy)
  45. +        self.submodules.sdtimer = Timer()
  46. +
  47. +        self.submodules.bist_generator = BISTBlockGenerator(random=True)
  48. +        self.submodules.bist_checker = BISTBlockChecker(random=True)
  49. +
  50. +        self.comb += [
  51. +            self.sdcore.source.connect(self.bist_checker.sink),
  52. +            self.bist_generator.source.connect(self.sdcore.sink)
  53. +        ]
  54. +
  55. +        self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.clk_freq)
  56. +        self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/self.clk_freq)
  57. +        self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/self.clk_freq)
  58. +
  59. +        self.crg.cd_sys.clk.attr.add("keep")
  60. +        self.sdclk.cd_sd.clk.attr.add("keep")
  61. +        self.sdclk.cd_sd_fb.clk.attr.add("keep")
  62. +        self.platform.add_false_path_constraints(
  63. +            self.crg.cd_sys.clk,
  64. +            self.sdclk.cd_sd.clk,
  65. +            self.sdclk.cd_sd_fb.clk)
  66. +
  67.  
  68.  # Build --------------------------------------------------------------------------------------------
  69.  
  70. @@ -111,7 +162,7 @@ def main():
  71.                          help="enable Ethernet support")
  72.      args = parser.parse_args()
  73.  
  74. -    cls = EthernetSoC if args.with_ethernet else BaseSoC
  75. +    cls = EthernetSoC if args.with_ethernet else SdSoC
  76.      soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
  77.      builder = Builder(soc, **builder_argdict(args))
  78.      builder.build()
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