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- diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py
- index fdb48c4..f9883e1 100755
- --- a/litex_boards/official/targets/nexys4ddr.py
- +++ b/litex_boards/official/targets/nexys4ddr.py
- @@ -19,6 +19,12 @@ from litedram.phy import s7ddrphy
- from liteeth.phy.rmii import LiteEthPHYRMII
- from liteeth.mac import LiteEthMAC
- +from litesdcard.phy import SDPHY
- +from litesdcard.clocker import SDClockerS7
- +from litesdcard.core import SDCore
- +from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
- +from litex.soc.cores.timer import Timer
- +
- # CRG ----------------------------------------------------------------------------------------------
- class _CRG(Module):
- @@ -98,6 +104,51 @@ class EthernetSoC(BaseSoC):
- self.ethphy.crg.cd_eth_rx.clk,
- self.ethphy.crg.cd_eth_tx.clk)
- +# SdSoC -----------------------------------------------------------------------------------------
- +
- +class SdSoC(EthernetSoC):
- + csr_map = {
- + "sdclk": 20,
- + "sdphy": 21,
- + "sdcore": 22,
- + "sdtimer": 23,
- + "sdemulator": 24,
- + "bist_generator": 25,
- + "bist_checker": 26,
- + "analyzer": 30
- + }
- + csr_map.update(EthernetSoC.csr_map)
- +
- + def __init__(self, **kwargs):
- + BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
- +
- + # SDcard
- + sdcard_pads = self.platform.request("sdcard")
- + self.submodules.sdclk = SDClockerS7()
- + self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device)
- + self.submodules.sdcore = SDCore(self.sdphy)
- + self.submodules.sdtimer = Timer()
- +
- + self.submodules.bist_generator = BISTBlockGenerator(random=True)
- + self.submodules.bist_checker = BISTBlockChecker(random=True)
- +
- + self.comb += [
- + self.sdcore.source.connect(self.bist_checker.sink),
- + self.bist_generator.source.connect(self.sdcore.sink)
- + ]
- +
- + self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.clk_freq)
- + self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/self.clk_freq)
- + self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/self.clk_freq)
- +
- + self.crg.cd_sys.clk.attr.add("keep")
- + self.sdclk.cd_sd.clk.attr.add("keep")
- + self.sdclk.cd_sd_fb.clk.attr.add("keep")
- + self.platform.add_false_path_constraints(
- + self.crg.cd_sys.clk,
- + self.sdclk.cd_sd.clk,
- + self.sdclk.cd_sd_fb.clk)
- +
- # Build --------------------------------------------------------------------------------------------
- @@ -111,7 +162,7 @@ def main():
- help="enable Ethernet support")
- args = parser.parse_args()
- - cls = EthernetSoC if args.with_ethernet else BaseSoC
- + cls = EthernetSoC if args.with_ethernet else SdSoC
- soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
- builder = Builder(soc, **builder_argdict(args))
- builder.build()
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