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CS8409 inf section

lelik76
Dec 5th, 2018
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  1. hardware id:
  2. HDAUDIO\FUNC_01&VEN_1013&DEV_8409&SUBSYS_106B1000&REV_1001
  3. HDAUDIO\FUNC_01&VEN_1013&DEV_8409&SUBSYS_106B1000
  4.  
  5. HdAudioFunctionDriver.CS8409_106B1000.DeviceDesc = "Cirrus Logic CS8409 (AB 16)"
  6.  
  7. ;; quad APO (AB 16)
  8. [HDAudio.Cirrus_CONF_0911]
  9. Include=hdaudio.inf
  10. Needs=HdAudOEM.CopyFiles, HdAudOEM.AddReg, CSHDA.Conf
  11. DelReg=HDAudio.Cirrus.LFDParams.DelReg
  12. DelReg=HDAudio.Cirrus.PCOVs.DelReg
  13. AddReg=CONF_09xx.PinConfigOverride, CONF_0910.PinConfigOverride, CONF_0910.InitVerbs
  14. AddReg=CONF_0900.Gpio, CONF_0910.Gpio, CONF_0900.TXRX, CONF_09xx.I2C, CONF_0910.I2C
  15. AddReg=CONF_0911.APOParams, CONF_0911.MicAPOParams
  16. AddReg=SettingsCS8409Exit, SettingsNoIdlePowerdown
  17.  
  18. [HDAudio.Cirrus_CONF_0911.Interfaces]
  19. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eSpeakerTopo%, HDAudio.Cirrus.ApoQuadTopo
  20. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eSpeakerTopo%, HDAudio.Cirrus.ApoQuadTopo
  21. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eHeadphoneTopo%, HDAudio.Cirrus.NoApoHPTopo
  22. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eHeadphoneTopo%, HDAudio.Cirrus.NoApoHPTopo
  23.  
  24. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eMicInTopo%, HDAudio.Cirrus.HSInTopo
  25. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eMicInTopo%, HDAudio.Cirrus.HSInTopo
  26. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eMicIn2Topo%, HDAudio.Cirrus.MicApoTopo
  27. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eMicIn2Topo%, HDAudio.Cirrus.MicApoTopo
  28.  
  29. ;;
  30. ;; All EP\\0 entries in the same grouping
  31. ;;
  32. ;; Set default format to 48kHz, 24-bit, Quad
  33. [OEMSettingsOverrideQuad.AddReg]
  34. HKR,"EP\\0", %PKEY_AudioEndpoint_Association%,,%KSNODETYPE_ANY%
  35. HKR,"EP\\0", %PKEY_AudioEngine_OEMFormat%, %REG_BINARY%, 41,00,00,00,28,00,00,00,FE,FF,04,00,80,BB,00,00,00,B8,0B,00,10,00,20,00,16,00,18,00,33,00,00,00,01,00,00,00,00,00,10,00,80,00,00,AA,00,38,9B,71
  36.  
  37. HKLM,"Software\\Cirrus\\APO\\FilterAPO","APOProcessMode",%REG_DWORD%,0x2 ; quad (FL/FR - woofers, RL/RR - tweeters)
  38. HKLM,"Software\\Cirrus\\APO\\FilterAPO","APOWorkAround1",%REG_DWORD%,0x0
  39. HKLM,"Software\\Cirrus\\APO\\FilterAPO","APOWorkAround1DisableMuteControl",%REG_DWORD%,0x0
  40.  
  41. ;;
  42. ;; All EP\\0 entries in the same grouping
  43. ;;
  44. ;; Set default format to 48kHz, 24-bit, Stereo
  45. [OEMSettingsOverrideStereo.AddReg]
  46. HKR,"EP\\0", %PKEY_AudioEndpoint_Association%,,%KSNODETYPE_ANY%
  47. HKR,"EP\\0", %PKEY_AudioEngine_OEMFormat%, %REG_BINARY%, 41,00,C8,70,28,00,00,00,FE,FF,02,00,80,BB,00,00,00,DC,05,00,08,00,20,00,16,00,18,00,03,00,00,00,01,00,00,00,00,00,10,00,80,00,00,AA,00,38,9B,71
  48.  
  49.  
  50. [CONF_09xx.PinConfigOverride]
  51. ;; pin config overrides for CONF_09xx (SPKR)
  52. HKR,cs420x,n24PinConfig, %REG_DWORD%, 0x90100080 ;; TX1.A: fixed int SPKR unkn unkn 8h 0h (FL/FR)
  53. HKR,cs420x,n25PinConfig, %REG_DWORD%, 0x90100082 ;; TX1.B: fixed int SPKR unkn unkn 8h 2h (RL/RR)
  54.  
  55. [CONF_0910.PinConfigOverride]
  56. ;; pin config overrides for CONF_0910 (HP, HS, DM2)
  57. HKR,cs420x,n2CPinConfig, %REG_DWORD%, 0x012B20F0 ;; TX2.A: jack prim/rear HP combo gray Fh 0h
  58. HKR,cs420x,n3CPinConfig, %REG_DWORD%, 0x01AB2050 ;; RX2.A: jack prim/rear MI combo gray 5h 0h
  59. HKR,cs420x,n45PinConfig, %REG_DWORD%, 0x90A00070 ;; DM2: fixed int MI unkn unkn 7h 0h
  60.  
  61. [CONF_0910.InitVerbs]
  62. HKR,cs420x,InitVerbs, %REG_BINARY%,\ ;
  63. 00,05,17,00,\ ; AFG: PS-Set = D0
  64. 01,03,77,04,\ ; VPW: proc on
  65. 00,00,75,04, 08,B0,74,04,\ ; CIR=00h, coeff=B008h (+PLL1/2_EN, +I2C_EN)
  66. 01,00,75,04, 06,00,74,04,\ ; CIR=01h, coeff=0006h (ASP1/2_EN = 0, ASP1/2_STP = 1)
  67. 02,00,75,04, 80,0A,74,04,\ ; CIR=02h, coeff=0A80h (ASP1/2_BUS_IDLE = 10, +GPIO_I2C)
  68. 19,00,75,04, 00,08,74,04,\ ; CIR=19h, coeff=0800h (ASP1.A: TX.LAP = 0, TX.LSZ = 24 bits, TX.LCS = 0)
  69. 1A,00,75,04, 20,08,74,04,\ ; CIR=1Ah, coeff=0820h (ASP1.A: TX.RAP = 0, TX.RSZ = 24 bits, TX.RCS = 32)
  70. 1B,00,75,04, 40,08,74,04,\ ; CIR=1Bh, coeff=0840h (ASP1.B: TX.LAP = 0, TX.LSZ = 24 bits, TX.LCS = 64)
  71. 1C,00,75,04, 60,08,74,04,\ ; CIR=1Ch, coeff=0860h (ASP1.B: TX.RAP = 0, TX.RSZ = 24 bits, TX.RCS = 96)
  72. 29,00,75,04, 00,08,74,04,\ ; CIR=29h, coeff=0800h (ASP2.A: TX.LAP = 0, TX.LSZ = 24 bits, TX.LCS = 0)
  73. 2A,00,75,04, 20,08,74,04,\ ; CIR=2Ah, coeff=0820h (ASP2.A: TX.RAP = 0, TX.RSZ = 24 bits, TX.RCS = 32)
  74. 49,00,75,04, 00,08,74,04,\ ; CIR=49h, coeff=0800h (ASP2.A: RX.LAP = 0, RX.LSZ = 24 bits, RX.LCS = 0)
  75. 4A,00,75,04, 00,08,74,04,\ ; CIR=4Ah, coeff=0800h (ASP2.A: RX.RAP = 0, RX.RSZ = 24 bits, RX.RCS = 0)
  76. 03,00,75,04, 00,80,74,04,\ ; CIR=03h, coeff=8000h (ASP1: LCHI = 00h)
  77. 04,00,75,04, 7F,28,74,04,\ ; CIR=04h, coeff=287Fh (ASP1: MC/SC_SRCSEL = PLL1, LCPR = 7Fh)
  78. 05,00,75,04, 5B,0A,74,04,\ ; CIR=05h, coeff=0A5Bh (ASP1: MCEN = 1, MCDIV = 1:4, FSD = 010, SCPOL_IN/OUT = 1, SCDIV = 1:8)
  79. 06,00,75,04, 00,80,74,04,\ ; CIR=06h, coeff=8000h (ASP2: LCHI = 00h)
  80. 07,00,75,04, FF,28,74,04,\ ; CIR=07h, coeff=28FFh (ASP2: MC/SC_SRCSEL = PLL1, LCPR = FFh)
  81. 08,00,75,04, 62,00,74,04,\ ; CIR=08h, coeff=0062h (ASP2: MCEN = 0, FSD = 011, SCPOL_IN/OUT = 0, SCDIV = 1:4)
  82. 09,00,75,04, 43,00,74,04,\ ; CIR=09h, coeff=0043h (DMIC2_MO = 01b, DMIC1/2_SR = 1)
  83. 01,00,75,04, 66,00,74,04,\ ; CIR=01h, coeff=0066h (ASP1/2_EN = 1, ASP1/2_STP = 1)
  84. 00,00,75,04, 08,90,74,04,\ ; CIR=00h, coeff=9008h (-PLL2_EN)
  85. 82,00,75,04, 02,FD,74,04,\ ; CIR=82h, coeff=FD02h (ASP1/2_xxx_EN = 1, ASP2_MCLK_EN = 0, DMIC2_SCL_EN = 1)
  86. C0,00,75,04, 99,99,74,04,\ ; CIR=C0h, coeff=9999h (test mode on)
  87. C5,00,75,04, 00,00,74,04,\ ; CIR=C5h, coeff=0000h [0004h] (GPIO hysteresis = 30 us)
  88. C0,00,75,04, 00,00,74,04 ; CIR=C0h, coeff=0000h (test mode off)
  89.  
  90.  
  91. [SettingsCS8409Exit]
  92. HKR,cs420x,ExitVerbs, %REG_BINARY%,\ ;
  93. 00,05,17,00,\ ; AFG: PS-Set = D0
  94. 01,00,75,04, 00,00,74,04,\ ; CIR=01h, coeff=0000h (ASP1/2_EN = 0)
  95. 82,00,75,04, 00,00,74,04,\ ; CIR=82h, coeff=0000h (ASP1/2_xxx_EN = 0, DMIC1/2_SCL_EN = 0)
  96. 03,00,75,04, 00,80,74,04,\ ; CIR=03h, coeff=8000h (ASP1: LCHI = 00h)
  97. 04,00,75,04, 01,28,74,04,\ ; CIR=04h, coeff=2801h (ASP1: MC/SC_SRCSEL = PLL1, LCPR = 01h)
  98. 06,00,75,04, 00,80,74,04,\ ; CIR=06h, coeff=8000h (ASP2: LCHI = 00h)
  99. 07,00,75,04, 01,28,74,04,\ ; CIR=07h, coeff=2801h (ASP2: MC/SC_SRCSEL = PLL1, LCPR = 01h)
  100. 65,00,75,04, 00,00,74,04,\ ; CIR=65h, coeff=0000h (EQ1/2_EN = 0000)
  101. 00,03,77,04,\ ; VPW: proc off
  102. 03,05,17,00 ; AFG: PS-Set = D3
  103.  
  104.  
  105. [CONF_0900.Gpio]
  106. ; GPIO0 is an input (from 'L83 INT#)
  107. HKR,cs420x,Gpio1ExtAmpCfg, %REG_BINARY%, 01,00,00,01 ; GPIO1 is an output controlled by AFG PS-Set (to 'L83 RESET#)
  108.  
  109. [CONF_0910.Gpio]
  110. HKR,cs420x,Gpio4ExtAmpCfg, %REG_BINARY%, 01,00,00,01 ; GPIO4 is an output controlled by AFG PS-Set (to amp SDZ)
  111. ; GPIO5 is an input (from amp FAULTZ)
  112. [CONF_0900.TXRX]
  113. HKR,cs420x,n01SuppBitsRates, %REG_DWORD%, 0x000A0040 ; AFG: override rate caps: -B32, -R9, -R6..R1
  114. ;SPKR
  115. HKR,cs420x,n02WidgetCaps, %REG_DWORD%, 0x00060401 ; TX1.A: override widget caps: +PC
  116. HKR,cs420x,n03WidgetCaps, %REG_DWORD%, 0x00060401 ; TX1.B: override widget caps: +PC
  117. ;HP
  118. HKR,cs420x,n2CWidgetCaps, %REG_DWORD%, 0x00400181 ; TX2.A: override widget caps: +UC
  119. HKR,cs420x,n2CPinCaps, %REG_DWORD%, 0x0000001C ; TX2.A: override pin caps: +HDC, +PDC
  120. HKR,cs420x,n2CJackDetectL83, %REG_DWORD%, 0x00086490 ; TX2.A: HP jack detect with 1000 ms debounce on TS (addr=90h)
  121. HKR,cs420x,n2CURHysteresis, %REG_BINARY%, 01 ; TX2.A: enable hysteresis on UR target widget
  122. ;HS
  123. HKR,cs420x,n1AWidgetCaps, %REG_DWORD%, 0x0016010B ; RX2.A: override widget caps: +APO, +IAP
  124. HKR,cs420x,n1AInAmpCaps, %REG_DWORD%, 0x80033F33 ; RX2.A: override in amp caps: MC=1, SS=03h, NOS=3Fh, OFST=33h
  125. HKR,cs420x,n1AMapAdcVolL83, %REG_DWORD%, 0x00023C90 ; RX2.A: map input amp control from CW (NID=1A) and PW (NID=3C) to 'L83 ADC (addr=90h)
  126. HKR,cs420x,n3CWidgetCaps, %REG_DWORD%, 0x0040008B ; RX2.A: override widget caps: +UC, +APO, +IAP
  127. HKR,cs420x,n3CPinCaps, %REG_DWORD%, 0x00000024 ; RX2.A: override pin caps: +PDC
  128. HKR,cs420x,n3CInAmpCaps, %REG_DWORD%, 0x004F0101 ; RX2.A: override in amp caps: MC=0, SS=4Fh, NOS=01h, OFST=01h
  129. HKR,cs420x,n3CHSTypeDetectL83, %REG_DWORD%, 0x1214C790 ; RX2.A: HS type detect with most sub-features (addr=90h), no Mikey button detect
  130. HKR,cs420x,n3CURHysteresis, %REG_BINARY%, 01 ; RX2.A: enable hysteresis on UR target widget
  131. ;DMIC
  132. HKR,cs420x,n44InAmpCaps, %REG_DWORD%, 0x00270202 ; DMIC1: override in amp caps: MC=0, SS=27h, NOS=02h, OFST=02h
  133. HKR,cs420x,n45InAmpCaps, %REG_DWORD%, 0x00270202 ; DMIC2: override in amp caps: MC=0, SS=27h, NOS=02h, OFST=02h
  134.  
  135.  
  136. [CONF_09xx.I2C]
  137. HKR,cs420x,I2CSpeedMode, %REG_DWORD%, 01
  138. HKR,cs420x,I2CPolledMode, %REG_DWORD%, 01
  139. HKR,cs420x,I2CQuickMode, %REG_DWORD%, 01
  140. HKR,cs420x,I2CBusClear, %REG_DWORD%, 06
  141.  
  142. HKR,cs420x,I2CSlave90Config, %REG_DWORD%, 0x01002090 ; sa7p, INT# via GPIO0
  143.  
  144. HKR,cs420x,InitI2C, %REG_BINARY%, 01,90,3A,00,10,10,B0,00,1D,01,00,02,06,00,11,07,01,00,10,09,02,07,03,\
  145. 00,12,01,00,08,13,05,FF,06,00,07,20,02,0D,00,2A,02,02,03,00,04,00,05,02,06,00,07,20,08,02,09,00,0A,80,0B,02,0C,00,0D,A0,01,0C,\
  146. 00,29,02,01,03,02,04,00,05,00,01,01,00,11,01,0A,02,84,00,23,01,00,03,00,02,3F,00,20,01,03,\
  147. 00,1B,75,B6,73,C2,00,11,29,01,21,F3,03,20,05,00,12,00,13,80,00,1C,03,C0
  148. HKR,cs420x,n0AStreamStartI2C, %REG_BINARY%, 01,90,02,00,11,01,02
  149. HKR,cs420x,n0AStreamStopI2C, %REG_BINARY%, 01,90,02,00,11,01,0A
  150.  
  151. [CONF_0910.I2C]
  152. ;; requires CONF_09xx.I2C
  153. HKR,cs420x,I2CSlaveD8Config, %REG_DWORD%, 0x510040D8 ; sa8, INT# via GPIO5
  154. HKR,cs420x,I2CSlaveDAConfig, %REG_DWORD%, 0x510040DA ; sa8, INT# via GPIO5
  155. HKR,cs420x,I2CSlaveDCConfig, %REG_DWORD%, 0x510040DC ; sa8, INT# via GPIO5
  156. HKR,cs420x,I2CSlaveDEConfig, %REG_DWORD%, 0x510040DE ; sa8, INT# via GPIO5
  157.  
  158. HKR,cs420x,n02PwrUpI2C, %REG_BINARY%, 04,D8,DA,DC,DE,06,01,FF,02,44,04,CF,06,55,08,10,13,00
  159. HKR,cs420x,n03PwrUpI2C, %REG_BINARY%, 01,D8,01,03,82,01,DA,01,03,80,01,DC,01,03,83,01,DE,01,03,81
  160. HKR,cs420x,n02StreamStartI2C, %REG_BINARY%, 04,D8,DA,DC,DE,01,01,FD
  161. HKR,cs420x,n02StreamStopI2C, %REG_BINARY%, 04,D8,DA,DC,DE,01,01,FF
  162. HKR,cs420x,n23PwrUpI2C, %REG_BINARY%, 01,90,02,00,1B,73,E2
  163.  
  164.  
  165. [SettingsNoIdlePowerdown] ; prevents the codec from entering D3 when idle
  166. HKR,PowerSettings,PerformanceIdleTime, %REG_BINARY%, 00, 00, 00, 00
  167. HKR,PowerSettings,ConservationIdleTime,%REG_BINARY%, 00, 00, 00, 00
  168.  
  169.  
  170. [CONF_0911.APOParams]
  171. ;; AB 16
  172. ;; woofer: LPF + LPF + 6-ch PEQ
  173. ;; tweeter: 6-ch PEQ
  174. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\0", "Type", %REG_DWORD%, 0
  175. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\1", "Type", %REG_DWORD%, 0
  176. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\2", "Type", %REG_DWORD%, 1
  177. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\2", "f0", %REG_DWORD%, 800
  178. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\2", "Q", %REG_DWORD%, 70
  179. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\3", "Type", %REG_DWORD%, 1
  180. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\3", "f0", %REG_DWORD%, 800
  181. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\3", "Q", %REG_DWORD%, 70
  182. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\4", "Type", %REG_DWORD%, 6
  183. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\4", "f0", %REG_DWORD%, 1320
  184. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\4", "GaindB", %REG_DWORD%, 1722
  185. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\4", "Q", %REG_DWORD%, 62
  186. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\5", "Type", %REG_DWORD%, 6
  187. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\5", "f0", %REG_DWORD%, 210
  188. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\5", "GaindB", %REG_DWORD%, -1442
  189. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\5", "Q", %REG_DWORD%, 84
  190. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\6", "Type", %REG_DWORD%, 6
  191. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\6", "f0", %REG_DWORD%, 1663
  192. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\6", "GaindB", %REG_DWORD%, 1052
  193. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\6", "Q", %REG_DWORD%, 23
  194. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\7", "Type", %REG_DWORD%, 6
  195. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\7", "f0", %REG_DWORD%, 2500
  196. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\7", "GaindB", %REG_DWORD%, -1971
  197. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\7", "Q", %REG_DWORD%, 29
  198. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\8", "Type", %REG_DWORD%, 6
  199. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\8", "f0", %REG_DWORD%, 604
  200. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\8", "GaindB", %REG_DWORD%, -763
  201. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\8", "Q", %REG_DWORD%, 33
  202. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\9", "Type", %REG_DWORD%, 6
  203. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\9", "f0", %REG_DWORD%, 345
  204. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\9", "GaindB", %REG_DWORD%, -900
  205. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\0\\9", "Q", %REG_DWORD%, 46
  206.  
  207. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\0", "Type", %REG_DWORD%, 0
  208. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\1", "Type", %REG_DWORD%, 0
  209. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\2", "Type", %REG_DWORD%, 6
  210. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\2", "f0", %REG_DWORD%, 1031
  211. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\2", "GaindB", %REG_DWORD%, -1767
  212. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\2", "Q", %REG_DWORD%, 36
  213. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\3", "Type", %REG_DWORD%, 6
  214. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\3", "f0", %REG_DWORD%, 1890
  215. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\3", "GaindB", %REG_DWORD%, 1148
  216. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\3", "Q", %REG_DWORD%, 29
  217. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\4", "Type", %REG_DWORD%, 6
  218. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\4", "f0", %REG_DWORD%, 3440
  219. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\4", "GaindB", %REG_DWORD%, -781
  220. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\4", "Q", %REG_DWORD%, 54
  221. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\5", "Type", %REG_DWORD%, 6
  222. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\5", "f0", %REG_DWORD%, 1180
  223. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\5", "GaindB", %REG_DWORD%, -662
  224. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\5", "Q", %REG_DWORD%, 14
  225. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\6", "Type", %REG_DWORD%, 6
  226. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\6", "f0", %REG_DWORD%, 1637
  227. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\6", "GaindB", %REG_DWORD%, 516
  228. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\6", "Q", %REG_DWORD%, 27
  229. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\7", "Type", %REG_DWORD%, 6
  230. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\7", "f0", %REG_DWORD%, 4883
  231. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\7", "GaindB", %REG_DWORD%, 341
  232. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\1\\7", "Q", %REG_DWORD%, 32
  233.  
  234. [CONF_0911.MicAPOParams]
  235. ;; AB 16
  236. ;; int. mic: HPF + HPF + NF + 2-ch PEQ
  237. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\0", "Type", %REG_DWORD%, 2
  238. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\0", "f0", %REG_DWORD%, 80
  239. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\0", "Q", %REG_DWORD%, 71
  240. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\1", "Type", %REG_DWORD%, 2
  241. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\1", "f0", %REG_DWORD%, 80
  242. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\1", "Q", %REG_DWORD%, 71
  243. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\2", "Type", %REG_DWORD%, 5
  244. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\2", "f0", %REG_DWORD%, 120
  245. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\2", "Q", %REG_DWORD%, 14
  246. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\3", "Type", %REG_DWORD%, 6
  247. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\3", "f0", %REG_DWORD%, 2000
  248. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\3", "GaindB", %REG_DWORD%, -300
  249. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\3", "Q", %REG_DWORD%, 137
  250. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\4", "Type", %REG_DWORD%, 6
  251. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\4", "f0", %REG_DWORD%, 10000
  252. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\4", "GaindB", %REG_DWORD%, -800
  253. HKLM,"Software\\Cirrus\\APO\\FilterAPO\\IntMic\\4\\4", "Q", %REG_DWORD%, 102
  254.  
  255. [HDAudio.Cirrus_CONF_0911.Interfaces]
  256. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eSpeakerTopo%, HDAudio.Cirrus.ApoQuadTopo
  257. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eSpeakerTopo%, HDAudio.Cirrus.ApoQuadTopo
  258. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eHeadphoneTopo%, HDAudio.Cirrus.NoApoHPTopo
  259. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eHeadphoneTopo%, HDAudio.Cirrus.NoApoHPTopo
  260.  
  261. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eMicInTopo%, HDAudio.Cirrus.HSInTopo
  262. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eMicInTopo%, HDAudio.Cirrus.HSInTopo
  263. AddInterface=%KSCATEGORY_AUDIO%, %KSNAME_eMicIn2Topo%, HDAudio.Cirrus.MicApoTopo
  264. AddInterface=%KSCATEGORY_TOPOLOGY%,%KSNAME_eMicIn2Topo%, HDAudio.Cirrus.MicApoTopo
  265.  
  266. [HDAudio.Cirrus.ApoQuadTopo]
  267. DelReg = HDAudio.Cirrus.APOParams.DelReg
  268. AddReg = HDAudio.Cirrus.ApoQuadTopo.AddReg, OEMSettingsOverrideQuad.AddReg, CirrusSysFx.AddReg
  269.  
  270. [HDAudio.Cirrus.NoApoHPTopo]
  271. AddReg = HDAudio.Cirrus.NoApoHPTopo.AddReg, OEMSettingsOverrideStereo.AddReg, MSSysFx.AddReg
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