module_48kHz

module module_48kHz(
    clock,
    reset,
    start,
    ready,
    Ks,
    Kd,
    clken48kHz,
    clken192kHz,
    left,
    right,
    interpolated_LpR,
    interpolated_LmR
);

parameter M = 18;
parameter N = 4;

input clock;
input reset;
input start;
input ready;
input clken48kHz;
input clken192kHz;

input [3:0] Ks;
input [3:0] Kd;

input signed [17:0] left;
input signed [17:0] right;

reg signed [17:0] LpR;
reg signed [17:0] LmR;

wire signed[22:0] LpR_Ks;
wire signed[22:0] LmR_Kd;

reg signed [17:0] LpR_Ks_18bit;
reg signed [17:0] LmR_Kd_18bit;

output reg signed [17:0] interpolated_LpR;
output reg signed [17:0] interpolated_LmR;

always @*
    begin
        LpR <= left + right;
        LmR <= left - right;
    end

seqmultNM #( // definition of parameters
.N( 5 ), // parameter N = number of bits of the multiplier
.M( 18 ) // parameter M = numbero of bits of the multiplicand
 )
seqmult_LpR // instance name
(
 .clock( clock ), // Master clock
 .reset( reset ), // Master reset, synchronous and active high
 .start( start ), // Set to 1 during one clock cycle to start the multiplication
 .ready( ready ), // Set to 1 when the multiplier is ready to accept a new start
 .A( LpR ), // Multiplicand, signed M bits
 .B( {1'b0, Ks} ), // Multiplier, signed N bits
 .R( LpR_Ks ) // Result, signed M+N bits
 );

 seqmultNM #( // definition of parameters
.N( 5 ), // parameter N = number of bits of the multiplier
.M( 18 ) // parameter M = numbero of bits of the multiplicand
 )
seqmult_LmR // instance name
(
 .clock( clock ), // Master clock
 .reset( reset ), // Master reset, synchronous and active high
 .start( start ), // Set to 1 during one clock cycle to start the multiplication
 .ready( ready ), // Set to 1 when the multiplier is ready to accept a new start
 .A( LmR ), // Multiplicand, signed M bits
 .B( {1'b0, Kd} ), // Multiplier, signed N bits
 .R( LpR_Ks ) // Result, signed M+N bits
 );

interpol4x
interpol4x_1(
 .clock( clock ), // Master clock
 .reset( reset ), // Master reset, synchronous active high
 .clkenin( clken48kHz ), // Input clock enable
 .clken4x( clken192kHz ), // Output clock enable (4X the input enable)
 .xkin( LpR_Ks ), // Input signal, 18 bit signed
 .ykout( interpolated_LpR ) // Output signal, 18 bit signed
 );

interpol4x
interpol4x_2(
 .clock( clock ), // Master clock
 .reset( reset ), // Master reset, synchronous active high
 .clkenin( clken48kHz ), // Input clock enable
 .clken4x( clken192kHz ), // Output clock enable (4X the input enable)
 .xkin( LmR_Kd ), // Input signal, 18 bit signed
 .ykout( interpolated_LmR ) // Output signal, 18 bit signed
 );

 always @(posedge clock)
 begin
    if (start)
    begin
        LpR_Ks_18bit <= LpR_Ks >>> 5;
        LmR_Kd_18bit <= LmR_Kd >>> 5;
    end
 end

 endmodule