`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/22/2023 04:13:05 PM
// Design Name:
// Module Name: Tx_FSM
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Tx_FSM(
    input CLK50MHZ,
    input n_rst,
    input Tx_En,
    input baud_tick,
    input [7:0] TxD,
    input D_num,
    input S_num,
    input [1:0] par_scheme,
    output reg TxD_out,
    output reg Tx_Done,
    output reg [5:0] state,
    output reg [2:0] bit_no
    );

    reg [5:0] state, next_state;
    integer bit_no, bit_no_next, ones_count, ones_count_next;

    parameter   init =      6'b000001,
                start_bit = 6'b000010,
                data_bit =  6'b000100,
                par_bit =   6'b001000,
                stop_bit =  6'b010000,
                done =      6'b100000;

    always@(posedge CLK50MHZ or negedge n_rst) begin
        if(!n_rst) begin
            state <= init;
        end
        else if(baud_tick) begin
            state <= next_state;
        end
        else begin
            state <= state;
        end
    end

    always@(posedge CLK50MHZ or negedge n_rst) begin
        if(!n_rst) begin
            bit_no <= 0;
            ones_count <= 0;
        end
        else if(baud_tick) begin
            bit_no <= bit_no_next;
            ones_count <= ones_count_next;
        end
        else begin
            bit_no <= bit_no;
            ones_count <= ones_count;
        end
    end

    always@(*) begin: next_state_logic
        case(state)
            init: begin
                bit_no_next = 0;
                // The Tx_En is going to be something like FIFO_Full or TF_read or something. Just some way to tell the FSM
                // that it is an appropriate time to read from the FIFO.
                ones_count_next = 0;
                if(Tx_En) next_state = start_bit;
                else next_state = init;
            end
            start_bit: begin
                next_state = data_bit;
                bit_no_next = 0;
                ones_count_next = ones_count;
            end
            data_bit: begin
                bit_no_next = bit_no + 1;
                if(bit_no+1 == 7+D_num) next_state = par_bit;
                else next_state = data_bit;
                if(TxD) ones_count_next = ones_count + 1;
                else ones_count_next = ones_count;
            end
            par_bit: begin
                bit_no_next = 0; // Reset the bit no counter for the stop bits.
                next_state = stop_bit;
                ones_count_next = ones_count;
            end
            stop_bit: begin
                bit_no_next = bit_no + 1;
                ones_count_next = ones_count;
                if(bit_no+1 == 1+S_num) next_state = done;
                else next_state = stop_bit;
            end
            done: begin
                ones_count_next = ones_count;
                bit_no_next = 0;
                next_state = init;
            end
            default: begin
                next_state = init;
                ones_count_next = 0;
                bit_no_next = 0;
            end
        endcase
    end

    always@(state) begin: output_logic
        case(state)
            init: begin
                TxD_out = 1'b1;
                Tx_Done = 1'b0;
            end
            start_bit: begin
                TxD_out = 1'b0;
                Tx_Done = 1'b0;
            end
            data_bit: begin
                TxD_out = TxD[bit_no];
                Tx_Done = 1'b0;
            end
            par_bit: begin
                //00 no parity, 01 odd parity, 10 even parity, 11 invalid
                Tx_Done = 1'b0;
                if(par_scheme == 2'b00) TxD_out = 1'b0;
                else if (par_scheme == 2'b01) begin
                    if(ones_count%2) TxD_out = 1'b0;
                    else TxD_out = 1'b1;
                end
                else if (par_scheme == 2'b10) begin
                    if(ones_count%2) TxD_out = 1'b1;
                    else TxD_out = 1'b0;
                end
                else TxD_out = 1'b0;
            end
            stop_bit: begin
                TxD_out = 1'b1;
                Tx_Done = 1'b0;
            end
            done: begin
                TxD_out = 1'b1;
                Tx_Done = 1'b1;
            end
            default: begin
                TxD_out = 1'b1;
                Tx_Done = 1'b0;
            end
        endcase
    end
endmodule