module FSMs(opcode, param1, param2, reset, clock, pc_increment, pc_memoryaddress, memory_read, memory_write, ir_load, register_in, register_out, mdr_load, alu_out, register_select, alu_select);

input [7:0] opcode;
input [3:0] param1, param2;
input reset, clock;

output pc_increment, pc_memoryaddress, memory_read, memory_write, ir_load, register_select, register_in, register_out, mdr_load, alu_select, alu_out;
output [2:0] register_select, alu_select;

reg [2:0] clear, present_state, next_state;

assign start = 3'b100, s0 = 3'b001, s1 = 3'b010, s2 = 3'b011;

always @(posedge clock or posedge reset)
begin
   if(reset)
      present_state <= start;
   else
      present_state <= next_state;
end

always @(present_state or posedge clock)
   case (present_state)
    clear: next_state <= s0;

    s0: next_state <= s1;
    s1: next_state <= s2;
   endcase

always @(posedge clock)
   case(present_state)
    clear:
    begin
      pc_increment = 0;
      pc_memoryaddress = 0;
      memory_read = 0;
      memory_write = 0;
      ir_load = 0;
      register_select = 0;
      register_in = 0;
      register_out = 0;
      mdr_load = 0;
      alu_out = 0;
    end

    s0:
    begin
      pc_increment = 1;
      pc_memoryaddress = 1;
      memory_read = 1;
      memory_write = 0;
      ir_load = 1;
      register_select = 0;
      register_in = 0;
      register_out = 0;
      mdr_load = 0;
      alu_out = 0;
    end

    s1:
    begin
      case(opcode)
        8'b0001XXXX:
        begin
          pc_increment = 0;
          pc_memoryaddress = 1;
          memory_read = 1;
          memory_write = 0;
          ir_load = 1;
          register_select = 0;
          register_in = 0;
          register_out = 0;
          mdr_load = 0;
          alu_out = 0;
        end

        8'b00100000:
        begin
          pc_increment = 1;
          pc_memoryaddress = 1;
          memory_read = 1;
          memory_write = 0;
          ir_load = 1;
          register_select = 0;
          register_in = 0;
          register_out = 0;
          mdr_load = 0;
          alu_out = 0;
        end
      endcase
    end

    s2:
    begin
      pc_increment = 1;
      pc_memoryaddress = 1;
      memory_read = 1;
      memory_write = 0;
      ir_load = 1;
      register_select = 0;
      register_in = 0;
      register_out = 0;
      mdr_load = 0;
      alu_out = 0;
    end
  endcase
endmodule