4-bit Register in VeriLog

module FourBitReg(a0, a1, a2, a3, clk, nreset, q0, q1, q2, q3);
  input a0, a1, a2,a3;
  input nreset, clk;
  output q0, q1, q2, q3;


  Dflipflop Q0(a0, clk, nreset, q0);
  Dflipflop Q1(a1, clk, nreset, q1);
  Dflipflop Q2(a2, clk, nreset, q2);
  Dflipflop Q3(a3, clk, nreset, q3);

endmodule



module FourBitReg_tb;
  reg a0, a1, a2, a3;
  reg clk, nreset;
  wire q0, q1, q2, q3;

  reg[3:0] counter;
  reg[3:0] in;
  FourBitReg Register(a0, a1, a2, a3,clk, nreset, q0, q1, q2, q3);

  initial begin
  a0 = 1'b0; a1 = 1'b0; a2=1'b0; a3 = 1'b0;
  clk = 1'b0; nreset = 1'b1;

  $monitor("a0a1a2a3 = %b%b%b%b, clk=%b, nreset=%b, q0q1q2q3=%b%b%b%b",
            a0, a1, a2, a3, clk, nreset, q0, q1, q2, q3);
  end
  initial begin
  for(counter =0; counter < 4'b1000; counter = counter + 1'b1) begin
    in = $random%8;
    a0 = in[0];
    a1 = in[1];
    a2 = in[2];
    a3 = in[3];
    #10;
    if(counter == 3'b011)begin
      nreset = 0;
    end

  end

  $finish;

  end
  always begin
  #10
  clk = ~clk;
  end
endmodule