RAM:FFFFFFC0017E8320 var_s0          =  0
RAM:FFFFFFC0017E8320 var_s10         =  0x10
RAM:FFFFFFC0017E8320 var_s20         =  0x20
RAM:FFFFFFC0017E8320
RAM:FFFFFFC0017E8320                 STP             X29, X30, [SP,#-0x30+var_s0]!
RAM:FFFFFFC0017E8324                 MOV             X29, SP
RAM:FFFFFFC0017E8328                 STP             X19, X20, [SP,#var_s10]
RAM:FFFFFFC0017E832C                 STP             X21, X22, [SP,#var_s20]
RAM:FFFFFFC0017E8330                 ADRP            X20, #qword_FFFFFFC0026A0478@PAGE
RAM:FFFFFFC0017E8334                 UXTB            W21, W0
RAM:FFFFFFC0017E8338                 MOV             X0, X30
RAM:FFFFFFC0017E833C                 MOV             W19, #8
RAM:FFFFFFC0017E8340                 BL              nullsub_1
RAM:FFFFFFC0017E8344                 LDR             X1, [X20,#qword_FFFFFFC0026A0478@PAGEOFF]
RAM:FFFFFFC0017E8348                 MOV             W0, #1
RAM:FFFFFFC0017E834C                 BLR             X1
RAM:FFFFFFC0017E8350                 ADRP            X0, #byte_FFFFFFC001E23358@PAGE
RAM:FFFFFFC0017E8354                 ADD             X0, X0, #byte_FFFFFFC001E23358@PAGEOFF
RAM:FFFFFFC0017E8358                 BL              sub_FFFFFFC001AC846C
RAM:FFFFFFC0017E835C                 B               loc_FFFFFFC0017E8384
RAM:FFFFFFC0017E8360 ; ---------------------------------------------------------------------------
RAM:FFFFFFC0017E8360
RAM:FFFFFFC0017E8360 loc_FFFFFFC0017E8360                    ; CODE XREF: sub_FFFFFFC0017E8320+78↓j
RAM:FFFFFFC0017E8360                 LDR             X1, [X22,#(qword_FFFFFFC0026A0480 - 0xFFFFFFC0026A0478)]
RAM:FFFFFFC0017E8364                 SUB             W19, W19, #1
RAM:FFFFFFC0017E8368                 LSR             W21, W21, #1
RAM:FFFFFFC0017E836C                 UXTB            W19, W19
RAM:FFFFFFC0017E8370                 BLR             X1
RAM:FFFFFFC0017E8374                 LDR             X1, [X20,#qword_FFFFFFC0026A0478@PAGEOFF]
RAM:FFFFFFC0017E8378                 MOV             W0, #1
RAM:FFFFFFC0017E837C                 BLR             X1
RAM:FFFFFFC0017E8380                 CBZ             W19, loc_FFFFFFC0017E83C4
RAM:FFFFFFC0017E8384
RAM:FFFFFFC0017E8384 loc_FFFFFFC0017E8384                    ; CODE XREF: sub_FFFFFFC0017E8320+3C↑j
RAM:FFFFFFC0017E8384                                         ; sub_FFFFFFC0017E8320+A0↓j
RAM:FFFFFFC0017E8384                 LDR             X1, [X20,#qword_FFFFFFC0026A0478@PAGEOFF]
RAM:FFFFFFC0017E8388                 MOV             W0, #0
RAM:FFFFFFC0017E838C                 ADD             X22, X20, #qword_FFFFFFC0026A0478@PAGEOFF
RAM:FFFFFFC0017E8390                 BLR             X1
RAM:FFFFFFC0017E8394                 MOV             W0, #1
RAM:FFFFFFC0017E8398                 TBNZ            W21, #0, loc_FFFFFFC0017E8360
RAM:FFFFFFC0017E839C                 LDR             X1, [X22,#(qword_FFFFFFC0026A0480 - 0xFFFFFFC0026A0478)]
RAM:FFFFFFC0017E83A0                 MOV             W0, #0
RAM:FFFFFFC0017E83A4                 SUB             W19, W19, #1
RAM:FFFFFFC0017E83A8                 LSR             W21, W21, #1
RAM:FFFFFFC0017E83AC                 BLR             X1
RAM:FFFFFFC0017E83B0                 UXTB            W19, W19
RAM:FFFFFFC0017E83B4                 LDR             X1, [X20,#qword_FFFFFFC0026A0478@PAGEOFF]
RAM:FFFFFFC0017E83B8                 MOV             W0, #1
RAM:FFFFFFC0017E83BC                 BLR             X1
RAM:FFFFFFC0017E83C0                 CBNZ            W19, loc_FFFFFFC0017E8384
RAM:FFFFFFC0017E83C4
RAM:FFFFFFC0017E83C4 loc_FFFFFFC0017E83C4                    ; CODE XREF: sub_FFFFFFC0017E8320+60↑j
RAM:FFFFFFC0017E83C4                 LDP             X19, X20, [SP,#var_s10]
RAM:FFFFFFC0017E83C8                 LDP             X21, X22, [SP,#var_s20]
RAM:FFFFFFC0017E83CC                 LDP             X29, X30, [SP+var_s0],#0x30
RAM:FFFFFFC0017E83D0                 RET