module flip_flop_cu_reset_sincron(
    input  clk_i,
    input rst_n_i,
    input  d_i,
    output reg q_o
);

always @(posedge clk_i) begin
    if(rst_n_i == 0)
        q_o <= 0;
    else
        q_o <= d_i;
end

endmodule

__________________

module flip_flop_cu_reset_sincron_tb;

reg clk_tb;
reg rst_n_tb;
reg d_tb;
wire q_tb;

flip_flop_cu_reset_sincron DUT(
.clk_i(clk_tb),
.rst_n_i(rst_n_tb),
.d_i(d_tb),
.q_o(q_tb)
);

initial begin
    clk_tb = 0;
    forever #5 clk_tb  = ~clk_tb;
end

initial begin
    rst_n_tb = 1;
#2  rst_n_tb = 0;
#10 rst_n_tb = 1;
end

initial begin
    d_tb = 0;
@(posedge clk_tb);
#3 d_tb = 1;
// wait 2 clk_tb cylces
@(posedge clk_tb);
@(posedge clk_tb);
// wait 2 clk_tb cylces
// repeat(2) @(posedge clk_tb);
#3 d_tb = 0;
repeat(3) @(posedge clk_tb);
#9  d_tb = 1;
#2  d_tb = 0;
repeat(2) @(posedge clk_tb);
$stop;
end
endmodule

__________________________

module shift_register_3_stagii(
    input  clk_i,
    input  d_i,
    output q_o
);

reg q1,q2,q3;

always @(posedge clk_i) begin
    q1 <= d_i;
    q2 <= q1;
    q3 <= q2;
end

assign q_o = q3;

endmodule
__________________________

module shift_register_3_stagii_tb;

reg clk_tb;
reg d_tb;
wire q_tb;

shift_register_3_stagii DUT(
.clk_i(clk_tb),
.d_i(d_tb),
.q_o(q_tb)
);

initial begin
    clk_tb = 0;
    forever #5 clk_tb  = ~clk_tb;
end

initial begin
    d_tb = 0;
@(posedge clk_tb);
#3 d_tb = 1;
// wait 2 clk_tb cylces
@(posedge clk_tb);
@(posedge clk_tb);
// wait 2 clk_tb cylces
// repeat(2) @(posedge clk_tb);
#3 d_tb = 0;
repeat(3) @(posedge clk_tb);
#9  d_tb = 1;
#2  d_tb = 0;
repeat(5) @(posedge clk_tb);
$stop;
end
endmodule
________________________

module counter(
    input clk_i,
    input rst_n_i,
    input cen_i,
    output [3:0] cnt_o
);

reg [3:0] cnt_reg;
reg [3:0] cnt_w;

always @(posedge clk_i) begin
  if (rst_n_i == 0) begin
    cnt_reg <= 0;
  end else begin
    if(cen_i == 1) begin
      cnt_reg <= cnt_w;
    end
  end
end

always @(cnt_reg) begin
  cnt_w = cnt_reg + 1;
end

assign cnt_o = cnt_reg;

endmodule
______________________________

module counter_tb;

reg clk_tb;
reg rst_n_tb;
reg cen_tb;
wire [3:0] cnt_tb;

counter counter_inst(.clk_i(clk_tb),.rst_n_i(rst_n_tb),.cen_i(cen_tb),.cnt_o(cnt_tb));

initial begin
    clk_tb = 0;
    forever #5 clk_tb = ~clk_tb;
end

initial begin
    rst_n_tb = 0;
repeat (6) @(posedge clk_tb);
    rst_n_tb = 1;
end

initial begin
    cen_tb = 0;
repeat (4) @(posedge clk_tb);
    cen_tb = 1;
repeat (20) @(posedge clk_tb);
    $stop;
end

endmodule
______________________________

module counter_v2(
    input clk_i,
    input rst_n_i,
    input load_i,
    input [3:0] target_i,
    input cen_i,
    input cnt_up_i,
    output [3:0] cnt_o
);

reg [3:0] cnt_reg;
reg [3:0] cnt_w;

always @(posedge clk_i) begin
  if (rst_n_i == 0) begin
    cnt_reg <= 0;
  end else begin
    cnt_reg <= cnt_w;
  end
end

always @(*) begin
  if (load_i == 1) begin
    cnt_w = target_i;
  end else begin
    if(cen_i == 1) begin
      if(cnt_up_i == 1) begin
        cnt_w = cnt_reg + 1;
      end else begin
        cnt_w = cnt_reg - 1;
      end
    end else begin
      cnt_w = cnt_reg;
    end
  end
end
assign cnt_o = cnt_reg;
endmodule
________________________________

module counter_v2_tb;
reg clk_tb;
reg rst_n_tb;
reg cen_tb;
reg load_tb;
reg cnt_up_tb;
reg  [3:0] target_tb;
wire [3:0] cnt_o;

counter_v2 counter_v2_inst(
    .clk_i(clk_tb),
    .load_i(load_tb),
    .target_i(target_tb),
    .cnt_up_i(cnt_up_tb),
    .rst_n_i(rst_n_tb),
    .cen_i(cen_tb),
    .cnt_o(cnt_o)
);
initial begin
    clk_tb = 0;
    forever #5 clk_tb = ~clk_tb;
end

initial begin
    rst_n_tb = 0;
repeat (6) @(posedge clk_tb);
    rst_n_tb = 1;
end
initial begin
    cen_tb = 0;
repeat (4) @(posedge clk_tb);
    cen_tb = 1;
repeat (11) @(posedge clk_tb);
    cen_tb = 0;
end
initial begin
    load_tb   = 0;
    target_tb = 0;
repeat (10) @(posedge clk_tb);
    load_tb   =  1;
    target_tb = 10;
repeat ( 2) @(posedge clk_tb);
    load_tb   =  0;
repeat (10) @(posedge clk_tb);
    $stop;
end
initial begin
    cnt_up_tb = 1;
repeat (8) @(posedge clk_tb);
    cnt_up_tb = 0;
end


endmodule
______________________________

module pwm(
    input clk_i,
    input rst_n_i,
    input [3:0] Tp_i,
    input [3:0] Tw_i,
    output reg pwm_o
);
reg [3:0] cnt_reg;

always @(posedge clk_i) begin
  if (rst_n_i == 0) begin
    cnt_reg <= 0;
  end else if(cnt_reg == Tw_i) begin
    cnt_reg <= 0;
  end else begin
    cnt_reg <= cnt_reg+1;
  end
end

always @(*) begin
    if(cnt_reg < Tp_i) begin
      pwm_o = 1;
    end else begin
      pwm_o = 0;
    end
end
endmodule
________________________

module pwm_tb;
reg clk_tb;
reg rst_n_tb;
reg [3:0] Tp_tb;
reg [3:0] Tw_tb;
wire  pwm_o;

pwm DUT(
    .clk_i(clk_tb),
    .rst_n_i(rst_n_tb),
    .Tp_i(Tp_tb),
    .Tw_i(Tw_tb),
    .pwm_o(pwm_o)
);
initial begin
    clk_tb = 0;
    forever #5 clk_tb = ~clk_tb;
end
initial begin
    rst_n_tb = 0;
repeat (6) @(posedge clk_tb);
    rst_n_tb = 1;
end
initial begin
    Tp_tb = 3;
    Tw_tb = 7;
repeat (50) @(posedge clk_tb);
    $stop;
end
endmodule
_____________________________
module RAM_single_port
#(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 16
)(
    input  clk_i,
    input  [ADDR_WIDTH-1:0]addr_i,
    input  read_write_i,
    input  [DATA_WIDTH-1:0]data_i,
    output [DATA_WIDTH-1:0]data_o
);

reg [DATA_WIDTH-1:0] RAM_mem[0:2**ADDR_WIDTH-1];

always @(posedge clk_i) begin
    if(read_write_i == 1)
        RAM_mem[addr_i] <= data_i;
end

assign data_o = RAM_mem[addr_i];
endmodule
__________________________
module RAM_single_port_tb;

parameter ADDR_WIDTH_tb = 4;
parameter DATA_WIDTH_tb = 8;

reg  clk_stim;
reg  [ADDR_WIDTH_tb-1:0]addr_stim;

reg  read_write_stim;
reg  [DATA_WIDTH_tb-1:0]data_i_stim;
wire [DATA_WIDTH_tb-1:0]data_o_mon;

// module instatiation
RAM_single_port #(
    .ADDR_WIDTH(ADDR_WIDTH_tb),
    .DATA_WIDTH(DATA_WIDTH_tb)
) RAM_single_port_inst(
    .clk_i(clk_stim),
    .addr_i(addr_stim),
    .read_write_i(read_write_stim),
    .data_i(data_i_stim),
    .data_o(data_o_mon)
);

initial begin
 $readmemh("RAM.txt", RAM_single_port_inst.RAM_mem);
end

// clock generator
initial begin
    clk_stim = 0;
    forever #5 clk_stim = ~clk_stim;
end

task write_RAM;
    input [ADDR_WIDTH_tb-1:0] addr_i;
    input [DATA_WIDTH_tb-1:0] data_i;
    begin
        read_write_stim = 1;
        addr_stim       = addr_i;
        data_i_stim     = data_i;
        @(posedge clk_stim);
    end
endtask

task read_RAM;
    input [ADDR_WIDTH_tb-1:0] addr_i;
    begin
        read_write_stim = 0;
        addr_stim       = addr_i;
        @(posedge clk_stim);
    end
endtask

initial begin
    read_write_stim = 0;
    repeat (2) @(posedge clk_stim);
    write_RAM(4'h1,8'hAA);
    write_RAM(4'h2,8'h55);
    write_RAM(4'h3,8'h77);
    read_RAM(4'h1);
    read_RAM(4'h2);
    read_RAM(4'h3);
    $stop;
end

endmodule
______________________________-

module fsm(
    input  clock,
    input  reset,
    input  in,
    output reg detectOk,
    output reg detectFail
);

localparam S0 = 2'b00;
localparam S1 = 2'b01;
localparam E  = 2'b10;

reg [1:0] state_now;
reg [1:0] state_next;

// state register
always @(posedge clock) begin
    if (reset == 1) begin
        state_now <= S0;
    end else begin
	state_now <= state_next;
    end
end

always @(*) begin
    //state_next = state_now;
    case (state_now)
        S0: if (in == 1) state_next = S1;
	       else      state_next = S0;

        S1: if (in == 0) state_next = E;
	       else      state_next = S1;

        E: state_next = E; // do nothing
        default: state_next = S0;
    endcase
end

always @(*) begin
detectOk = (state_now == S0) || (state_now == S1);
detectFail = (state_now == E);
end

endmodule
_____________________________________
module fsm_tb;

reg  clock;
reg  reset;
reg  in;
wire detectOk;
wire detectFail;

initial begin
    clock = 0;
    forever #1 clock = ~clock;
end

initial begin
        in = 0;
        reset = 0;
    #2  reset = 1;
    #2  reset = 0;
    #6  in = 1;
    #10 in = 0;
    #10 $stop();
end

fsm DUT(
    .clock(clock),
    .reset(reset),
    .in(in),
    .detectOk(detectOk),
    .detectFail(detectFail)
);

endmodule

________________________________
module cioco_cmos(
    input  clock,
    input  reset,
    input load50bani,
    input load1leu,
    output reg ack50bani,
    output reg ack1leu,
    output reg productDelivered
);

localparam S_0B   = 6'b000001;
localparam S_50B  = 6'b000010;
localparam S_100B = 6'b000100;
localparam S_150B = 6'b001000;
localparam S_200B = 6'b010000;
localparam S_250B = 6'b100000;

reg [5:0] state_now;
reg [5:0] state_next;

// state register
always @(posedge clock) begin
    if (reset == 1) begin
        state_now <= S_0B;
    end else begin
	state_now <= state_next;
    end
end

// CLC input
always @(*) begin
    state_next = state_now;
    case (state_now)
        S_0B:
	    if (load50bani == 1) state_next = S_50B;
	    else
	    if (load1leu   == 1) state_next = S_100B;
        S_50B:
	    if (load50bani == 1) state_next = S_100B;
	    else
	    if (load1leu   == 1) state_next = S_150B;
        S_100B:
	    if (load50bani == 1) state_next = S_150B;
	    else
	    if (load1leu   == 1) state_next = S_200B;
        S_150B:
	    if (load50bani == 1) state_next = S_200B;
	    else
	    if (load1leu   == 1) state_next = S_250B;
        S_200B:
	    if (load50bani == 1) state_next = S_250B;
	    else
	    if (load1leu   == 1) state_next = S_250B;
        S_250B: state_next  = S_0B;

        default: state_next = S_0B;
    endcase
end

//CLC out
always @(*) begin
    productDelivered = (state_now == S_250B);
end
always @(posedge clock) begin
    if (reset == 1) begin
        ack50bani <= 0;
	ack1leu   <= 0;
    end else begin
	if(load50bani == 1) begin
    	    ack50bani <= 1;
    	    ack1leu   <= 0;
	end
        else if(load1leu == 1) begin
	    ack50bani <= 0;
    	    ack1leu   <= 1;
	end
    end
end
endmodule
_________________________________________
module cioco_cmos_tb;

reg  clock;
reg  reset;
reg  load50bani;
reg  load1leu;
wire ack50bani;
wire ack1leu;
wire productDelivered;

initial begin
    clock = 0;
    forever #1 clock = ~clock;
end

initial begin
                       reset = 0;
    @(posedge clock);  reset = 1;
    @(posedge clock);  reset = 0;
end

initial begin
    load50bani = 0;
    load1leu   = 0;
    repeat(5) @(posedge clock);

    load50bani = 1; @(posedge clock); load50bani = 0; @(posedge clock);
    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);
    load50bani = 1; @(posedge clock); load50bani = 0; @(posedge clock);
    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);

    @(posedge clock);

    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);
    load50bani = 1; @(posedge clock); load50bani = 0; @(posedge clock);
    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);

    @(posedge clock);

    load50bani = 1; @(posedge clock); load50bani = 0; @(posedge clock);
    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);
    load50bani = 1; @(posedge clock); load50bani = 0; @(posedge clock);
    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);

    @(posedge clock);

    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);
    load50bani = 1; @(posedge clock); load50bani = 0; @(posedge clock);
    load1leu   = 1; @(posedge clock); load1leu   = 0; @(posedge clock);

    repeat(10) @(posedge clock);
    $stop;
end

cioco_cmos DUT(
    .clock(clock),
    .reset(reset),
    .load50bani(load50bani),
    .load1leu(load1leu),
    .ack50bani(ack50bani),
    .ack1leu(ack1leu),
    .productDelivered(productDelivered)
);

endmodule
__________________________________________

module mux
(
	input [3:0] in0,
	input [3:0] in1,
	input sel,
	output reg [3:0] out
);

always @(*)
	begin
		if (sel==0)
			out = in0;
		if (sel==1)
			out = in1;
	end

endmodule
______________________________________
module transcoder
(
	input [3:0] in0,
	output reg [6:0] out
);

always @(*)
	begin
		case(in0)
			0: out = 7'b0000001;
			1: out = 7'b1001111;
			2: out = 7'b0010010;
			3: out = 7'b0000110;
			4: out = 7'b1001100;
			5: out = 7'b0100100;
			6: out = 7'b1100000;
			7: out = 7'b0001111;
			8: out = 7'b0000000;
			9: out = 7'b0000100;
			10: out = 7'b0001000;
			11: out = 7'b1100000;
			12: out = 7'b0110001;
			13: out = 7'b1000010;
			14: out = 7'b0010000;
			15: out = 7'b0111000;
		endcase
	end

endmodule
___________________________________
module RAM_dual_port
#(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 16
)(
    input  clk_i,
    input  [ADDR_WIDTH-1:0]addr_read_i,
    input  [ADDR_WIDTH-1:0]addr_write_i,
    input  read_write_i,
    input  [DATA_WIDTH-1:0]data_i,
    output reg [DATA_WIDTH-1:0]data_o
);

reg [DATA_WIDTH-1:0] RAM_mem[0:2**ADDR_WIDTH-1];

always @(posedge clk_i) begin
    if(read_write_i == 1)
        RAM_mem[addr_write_i] <= data_i;
end

always @(posedge clk_i) begin
    data_o <= RAM_mem[addr_read_i];
end

endmodule
____________________________________
module RAM_dual_port_tb;

parameter ADDR_WIDTH_tb = 4;
parameter DATA_WIDTH_tb = 8;

reg  clk_stim;
reg  [ADDR_WIDTH_tb-1:0]addr_read_stim;
reg  [ADDR_WIDTH_tb-1:0]addr_write_stim;
reg  read_write_stim;
reg  [DATA_WIDTH_tb-1:0]data_i_stim;
wire [DATA_WIDTH_tb-1:0]data_o_mon;

task write_RAM;
    input [ADDR_WIDTH_tb-1:0] addr_i;
    input [DATA_WIDTH_tb-1:0] data_i;
    begin
        read_write_stim = 1;
        addr_write_stim = addr_i;
        data_i_stim     = data_i;
        @(posedge clk_stim);
    end
endtask

task read_RAM;
    input [ADDR_WIDTH_tb-1:0] addr_i;
    begin
        read_write_stim = 0;
        addr_read_stim = addr_i;
        @(posedge clk_stim);
    end
endtask

RAM_dual_port #(
    .ADDR_WIDTH(ADDR_WIDTH_tb),
    .DATA_WIDTH(DATA_WIDTH_tb)
) RAM_dual_port_inst(
    .clk_i(clk_stim),
    .addr_read_i(addr_read_stim),
    .addr_write_i(addr_write_stim),
    .read_write_i(read_write_stim),
    .data_i(data_i_stim),
    .data_o(data_o_mon)
);

initial begin
 $readmemh("RAM.txt", RAM_dual_port_inst.RAM_mem);
end

initial begin
    clk_stim = 0;
    forever #5 clk_stim = ~clk_stim;
end

initial begin
    read_write_stim = 0;
    repeat (2) @(posedge clk_stim);
    write_RAM(4'h1,8'hAA);
    write_RAM(4'h2,8'h55);
    write_RAM(4'h3,8'h77);
    read_RAM(4'h1);
    read_RAM(4'h2);
    read_RAM(4'h3);
    $stop;
end

endmodule
_____________________________
module or_gate(
    input  wire a,
    input  wire b,
    output wire c
);

assign c = a | b;

endmodule
____________________
module inv_gate(
    input  a,
    output b
);

assign b = ~a;

endmodule
____________________
module and_gate(
    input  wire a,
    input  wire b,
    output wire c
);

assign c = a & b;

endmodule