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  1. module count(
  2.   input wire reset,
  3.   input wire clk,
  4.   output reg [5:0]counter
  5. );
  6. always @(posedge clk or posedge reset)
  7.   if(reset)
  8.     counter <= 6'd0;
  9.   else
  10.     counter <= counter + 1'd1;
  11. endmodule
  12.  
  13.  
  14. module decoder(
  15.   input wire [2:0]in,
  16.   output reg [7:0]out
  17. );
  18.  
  19. always @*
  20. begin
  21.   case(in)
  22.    3'd0: out=8'b00000001;
  23.    3'd1: out=8'b00000010;
  24.    3'd2: out=8'b00000100;
  25.    3'd3: out=8'b00001000;
  26.    3'd4: out=8'b00010000;
  27.    3'd5: out=8'b00100000;
  28.    3'd6: out=8'b01000000;
  29.    3'd7: out=8'b10000000;
  30.   endcase
  31. end
  32. endmodule
  33.  
  34. module selector(
  35.   input wire [5:0]sig,
  36.   input wire [7:0]sel,
  37.   input wire sig1,
  38.   output reg out
  39. );
  40.  
  41. always @*
  42. begin
  43. case(sel)            // 2 4 8  F
  44.    default: out=sig1;// 0 0 0  1
  45.    3'd1: out=sig[0]; // 1 0 0  2
  46.    3'd2: out=sig[1]; // 0 1 0  4
  47.    3'd3: out=sig[2]; // 1 1 0  8
  48.    3'd4: out=sig[2]; // 0 0 1  8
  49.    3'd5: out=sig[3]; // 1 0 1  16
  50.    3'd6: out=sig[4]; // 0 1 1  32
  51.    3'd7: out=sig[5]; // 1 1 1  64
  52.   endcase
  53. end
  54. endmodule
  55.  
  56. module zadanie(
  57.   input wire [2:0]incont,
  58.   input wire clk,
  59.   input wire reset,
  60.   output wire signal
  61. );
  62. wire [5:0]c,
  63. wire [7:0]d;
  64. count(.clk (clk) , .reset (reset), .counter (c));
  65. decoder(.in (incont), .out (d));
  66. selector(.sig (c), .sel (d), .sig1 (clk), .out(signal));
  67. endmodule
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