-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors.  Please refer to the
-- applicable agreement for further details.

-- PROGRAM		"Quartus II"
-- VERSION		"Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition"
-- CREATED ON		"Tue Apr 10 13:36:47 2012"

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY cw2 IS
	PORT
	(
		clk :  IN  STD_LOGIC;
		clrn :  IN  STD_LOGIC;
		sclr :  IN  STD_LOGIC;
		x1 :  IN  STD_LOGIC;
		x2 :  IN  STD_LOGIC;
		ld :  IN  STD_LOGIC;
		mo1 :  OUT  STD_LOGIC;
		mo0 :  OUT  STD_LOGIC;
		L :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
		me :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);
		R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
		ST :  OUT  STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END cw2;

ARCHITECTURE bdf_type OF cw2 IS

COMPONENT automat
	PORT(clk : IN STD_LOGIC;
		 clrn : IN STD_LOGIC;
		 sclr : IN STD_LOGIC;
		 x1 : IN STD_LOGIC;
		 x2 : IN STD_LOGIC;
		 c : OUT STD_LOGIC;
		 mo1 : OUT STD_LOGIC;
		 mo0 : OUT STD_LOGIC;
		 me : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
		 ST : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
	);
END COMPONENT;

COMPONENT licz_rej
	PORT(clk : IN STD_LOGIC;
		 clrn : IN STD_LOGIC;
		 sclr : IN STD_LOGIC;
		 cnt : IN STD_LOGIC;
		 ld : IN STD_LOGIC;
		 L : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;

SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;


BEGIN



b2v_inst : automat
PORT MAP(clk => clk,
		 clrn => clrn,
		 sclr => sclr,
		 x1 => x1,
		 x2 => x2,
		 c => SYNTHESIZED_WIRE_0,
		 mo1 => mo1,
		 mo0 => mo0,
		 me => me,
		 ST => ST);


b2v_inst1 : licz_rej
PORT MAP(clk => clk,
		 clrn => clrn,
		 sclr => sclr,
		 cnt => SYNTHESIZED_WIRE_0,
		 ld => ld,
		 L => L,
		 R => R);


END bdf_type;








-------------------------------------------------
-- Uruchomienie na płytce DE1: dodanie komponentu do jednostki zawierającej przypisanie wyprowadzeń do
-- sygnałów z przełączników i diod.
-- Set As Top-Level Entity na plik za_de1.vhd.
-- W komentarzach znajduje się opis przypisania sygnałów do przełączników, diod i wyświetlaczy.
-- 		// KONKRETYZACJA/PRZYTOCZENIE KOMPONENTU //
-------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity za_de1 is
port(
SW : in std_logic_vector(9 downto 0); --sygnaly z przycisków SW[9],...,SW[0] płytki DE1
KEY : in std_logic_vector(3 downto 0); -- sygnaly z przyciskow KEY[3],...,KEY[0]
-------------------------------------------------------------
-- deklaracja wyprowadzen do podłączenia z diodami
-- LEDR oraz wyświetlaczami siedmiosegmentowymi.
-------------------------------------------------------------
LEDG : out std_logic_vector(7 downto 0); -- sterowanie diodami zielonymi
LEDR : out std_logic_vector(9 downto 0); -- sterowanie diodami czerwonymi
HEX0, HEX1, HEX2, HEX3 : out std_logic_vector(0 to 6); -- serowanie wy�wietlaczami siedmiosegmentowymi
-----------------------------------------------------------------
-- Przypisanie pozostałych sygnałów
-----------------------------------------------------------------
JP10: out std_logic_vector(7 downto 0)

);
end entity;

architecture arch of za_de1 is
-----------------------------------------
-- DOMYŚLNE PRZYPISANIA WYPROWADZEŃ
-----------------------------------------
attribute chip_pin : string;
	-------------------------------------
	-- SYGNAŁY WEJŚCIOWE
	-------------------------------------
attribute chip_pin of SW : signal is "L2, M1, M2, U11, U12, W12, V12, M22, L21, L22"; --SW[9]-SW[0]	-------------------------------------
attribute chip_pin of KEY : signal is "T21, T22, R21, R22";
	-- SYGNAŁY WYJSCIOWE:
	-- NIE MODYFIKOWAĆ PRZYPISAN!
	-------------------------------------
attribute chip_pin of LEDG : signal is "Y21, Y22, W21, W22, V21, V22, U21, U22";
attribute chip_pin of LEDR : signal is "R17, R18, U18, Y18, V19, T18, Y19, U19, R19, R20"; --diody LED czerwone
attribute chip_pin of HEX0 : signal is "J2, J1, H2, H1, F2, F1, E2";--HEX0
attribute chip_pin of HEX1 : signal is "E1, H6, H5, H4, G3, D2, D1";--HEX1
attribute chip_pin of HEX2 : signal is "G5, G6, C2, C1, E3, E4, D3 ";--HEX2
attribute chip_pin of HEX3 : signal is "F4, D5, D6, J4, L8, F3, D4";--HEX3
attribute chip_pin of JP10 : signal is "A13, B13, A14, B14, A15, B15, A16, B16"; --z��cze JP1
--deklaracja sygna��w sterowania wej�ciowych dekodera HEX -> 7segment
signal sigHEX3, sigHEX2, sigHEX1, sigHEX0: std_logic_vector(3 downto 0);
type HEXit is array(3 downto 0) of std_logic_vector(3 downto 0);
signal sigHEXai: HEXit;
type HEXot is array(3 downto 0) of std_logic_vector(0 to 6);
signal sigHEXao: HEXot;
-----------------------------------------
-- DODANIE TESTOWANEGO KOMPONENTU
-----------------------------------------
component automat
port(
clk, clrn : in std_logic;
sclr : in std_logic;
x1, x2 : in std_logic;
c : out std_logic;
me : out std_logic_vector(1 downto 0);
mo1, mo0: out std_logic;
ST : out std_logic_vector(2 downto 0)
);
end component;

begin
------------------------------------------
-- Domyślne przypisania sygnałów
------------------------------------------

------------------------------------------
-- KONKRETYZACJA/PRZYTOCZENIE KOMPONENTU
------------------------------------------
test_inst_de1:
automat
port map(
--sygnaly z przycisków SW[9],...,SW[0] i KEY[3],...,0 płytki DE1
clk => KEY(0) , --sygnaďż˝ zegaral KEY[0]
clrn => KEY(1), -- zerowanie asynchr.
sclr => SW(0), --SW[0]
x1   => SW(8), --SW[8]
x2	=> SW(9), --SW[9]
c   => LEDR(0),
me => LEDR(2 downto 1),
mo1   => LEDR(3), mo0   => LEDR(4),
ST => LEDR(7 downto 5)
);

LEDR(9 downto 8) <= "00";
LEDG <= (others => '0');
sigHEX0 <= (others => '0');
sigHEX1 <= (others => '0');
sigHEX2 <= (others => '0');
sigHEX3 <= (others => '0');
------------------------------------------
-- Kod obslugi wyswietlaczy siedmosegmentowych
------------------------------------------
sigHEXai(0) <= sigHEX0;
sigHEXai(1) <= sigHEX1;
sigHEXai(2) <= sigHEX2;
sigHEXai(3) <= sigHEX3;
HEX0 <= not sigHEXao(0);
HEX1 <= not sigHEXao(1);
HEX2 <= not sigHEXao(2);
HEX3 <= not sigHEXao(3);
gen_i1:
for I IN 0 to 3 GENERATE
with sigHEXai(I) select
sigHEXao(I) <= "1111110" when "0000",
	 "0110000" when "0001",
	 "1101101" when "0010",
	 "1111001" when "0011",
	 "0110011" when "0100",
	 "1011011" when "0101",
	 "1011111" when "0110",
	 "1110000" when "0111",
	 "1111111" when "1000",
	 "1111011" when "1001",
	 "1110111" when "1010",
	 "0011111" when "1011",
	 "1001110" when "1100",
	 "0111101" when "1101",
	 "1001111" when "1110",
	 "1000111" when "1111",
	 "-------" when others;
END GENERATE;
end arch;