sas

MAKEFILE

BUILD_DIR = build

TARGET = lab1

SOURCES_S = \
startup_code.s

SOURCES_C = \
Src/main.c

LINKER_SCRIPT = linker_script.ld

PREFIX = C:\Users\Sladjan\Desktop\Tools\GnuMcu_Toolchain\GNU MCU Eclipse\ARM Embedded GCC\8.3.1-1.1\bin

CC = $(PREFIX)/arm-none-eabi-gcc.exe -c
AS = $(PREFIX)/arm-none-eabi-as.exe
LD = $(PREFIX)/arm-none-eabi-ld.exe
OBJCOPY = $(PREFIX)/arm-none-eabi-objcopy.exe

MCU = -mcpu=cortex-m3 -mthumb

OBJECTS = $(addprefix $(BUILD_DIR)/, $(SOURCES_S:.s=.o))
vpath %.s $(sort $(dir $(SOURCES_S)))

OBJECTS += $(addprefix $(BUILD_DIR)/, $(notdir $(SOURCES_C:.c=.o)))
vpath %.c $(sort $(dir $(SOURCES_C)))

all : $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex

$(BUILD_DIR)/$(TARGET).elf : $(OBJECTS) makefile
	$(LD) -T $(LINKER_SCRIPT) -o $(@) $(OBJECTS)

$(BUILD_DIR)/$(TARGET).hex : $(BUILD_DIR)/$(TARGET).elf | $(BUILD_DIR)
	$(OBJCOPY) --output-target ihex $(<) $(@)

$(BUILD_DIR)/%.o : %.s makefile | $(BUILD_DIR)
	$(AS) $(MCU) -o $(@) $(<)

$(BUILD_DIR)/%.o : %.c makefile | $(BUILD_DIR)
	$(CC) $(MCU) -o $(@) $(<)

$(BUILD_DIR) :
	mkdir $(@)

clean :
	rm -rf $(BUILD_DIR)

LINKER_SCRIPT

_msp_stack_pointer = 0x20002800;

MEMORY
{
	FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 32K
	SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 10K
}

SECTIONS
{
	.output_vector_table :
	{
		*(.vector_table)
	} > FLASH

	.output_text :
	{
		*(.text)
		*(.text*)
	} > FLASH

	.output_data :
	{
		_vma_data_start = .;
		*(.data)
		*(.data*)
		_vma_data_end = .;
	} > SRAM AT > FLASH

	_lma_data_start = LOADADDR(.output_data);

	.output_bss :
	{
		*(.bss)
		*(.bss*)
	} > SRAM
}

STARTUP_CODE_S

.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb

.extern _msp_stack_pointer

.weak exti_1_handler
.thumb_set exti_1_handler, default_handler

.weak tim1_update_handler
.thumb_set tim1_update_handler, default_handler

.section .vector_table, "a"
.word _msp_stack_pointer
.word reset_handler
.rept 21
	.word default_handler
.endr
.word exti_1_handler
.rept 17
	.word default_handler
.endr
.word tim1_update_handler
.rept 42
	.word default_handler
.endr

.extern main

.extern _vma_data_start
.extern _vma_data_end
.extern _lma_data_start

.section .text.reset_handler
.type reset_handler, %function
reset_handler:
	ldr r0, = _lma_data_start
	ldr r1, = _vma_data_start
	ldr r2, = _vma_data_end
	cmp r1, r2
	beq branch_to_main
copy_loop:
	ldr r3, [r0], #4
	str r3, [r1], #4
	cmp r1, r2
	blo copy_loop
branch_to_main:
	b main
infinite_loop_1:
	b infinite_loop_1

.section .text.default_handler
.type default_handler, %function
default_handler:
infinite_loop_2:
	b infinite_loop_2
MAIN_C

#include <stdint.h>

#define RCC_APB2ENR (*((uint32_t *) (0x40021000 + 0x18)))
#define EXTI_IMR (*((uint32_t *) (0x40010400 + 0x00)))
#define EXTI_RTSR (*((uint32_t *) (0x40010400 + 0x08)))
#define EXTI_PR (*((uint32_t *) (0x40010400 + 0x14)))
#define NVIC_ISER0 (*((uint32_t *) (0xE000E100 + 0x00)))
#define GPIOC_CRL (*((uint32_t *) (0x40011000  + 0x00)))
#define GPIOC_CRH (*((uint32_t *) (0x40011000  + 0x04)))
#define GPIOC_ODR (*((uint32_t *) (0x40011000  + 0x0C)))
#define GPIOA_CRL (*((uint32_t *) (0x40010800  + 0x00)))
#define GPIOA_CRH (*((uint32_t *) (0x40010800  + 0x04)))
#define GPIOA_ODR (*((uint32_t *) (0x40010800  + 0x0C)))
#define AFIO_EXTICR1 (*((uint32_t *) (0x40010000  + 0x08)))
#define TIM1_DIER (*((uint32_t *) (0x40012C00  + 0x0C)))
#define TIM1_SR (*((uint32_t *) (0x40012C00  + 0x10)))
#define TIM1_PSC (*((uint32_t *) (0x40012C00  + 0x28)))
#define TIM1_ARR (*((uint32_t *) (0x40012C00  + 0x2C)))
#define TIM1_CR1 (*((uint32_t *) (0x40012C00  + 0x00)))

void init_RCC()
{
	RCC_APB2ENR |= (0x01 << 11) | (0x01 << 4) | (0x01 << 2);
}

void init_EXTI()
{
	EXTI_IMR |= 0x01 << 1;
	EXTI_RTSR |= 0x01 << 1;
}

void init_NVIC()
{
	NVIC_ISER0 = (0x01 << 25) | (0x01 << 7);
}

void init_GPIOC()
{
	uint32_t gpioc_crl_value = GPIOC_CRL;
	for(int i = 0; i < 8; i++)
	{
		gpioc_crl_value &= ~(0x0F << (4 * i));
		gpioc_crl_value |= 0x02 << (4 * i) | 0x00 << (2 + 4 * i);
	}
	GPIOC_CRL = gpioc_crl_value;
	uint32_t gpioc_crh_value = GPIOC_CRH;
	for(int i = 0; i < 4; i++)
	{
		gpioc_crh_value &= ~(0x0F << (4 * i));
		gpioc_crh_value |= 0x02 << (4 * i) | 0x00 << (2 + 4 * i);
	}
	GPIOC_CRH = gpioc_crh_value;
	GPIOC_ODR = 0x00;
}

void init_GPIOA()
{
	uint32_t gpioa_crl_value = GPIOA_CRL;
	gpioa_crl_value &= ~(0x0F << (4 * 1));
	gpioa_crl_value |= 0x00 << (4 * 1) | 0x02 << (2 + 4 * 1);
	gpioa_crl_value &= ~(0x0F << (4 * 2));
	gpioa_crl_value |= 0x02 << (4 * 2) | 0x00 << (2 + 4 * 2);
	GPIOA_CRL = gpioa_crl_value;
	GPIOA_ODR = 0x00;
	AFIO_EXTICR1 |= 0x00 << (4 * 1);
}

void init_TIM1()
{
	TIM1_DIER |= 0x01;
	TIM1_SR = 0;
	TIM1_PSC = 7999;
	TIM1_ARR = 2;
	TIM1_CR1 |= 0x01;
}

uint8_t encoding[] = { 0x3F, 0x06, 0x5B, 0x4F, 0x66, 0x6D, 0x7D, 0x07, 0x7F, 0x6F };
uint8_t digits[] = { 0, 0, 0, 0};
uint8_t current_digit = 0;
uint8_t sec = 0, min = 0;
uint8_t interrupt_count = 0;
uint8_t interrupt_dioda_count = 0;

void process_tim1_update_interrupt()
{
	if(++interrupt_dioda_count == 50)
	{
		interrupt_dioda_count = 0;
		GPIOA_ODR ^= 0x04;
	}

	if(++interrupt_count == 100)
	{
		interrupt_count = 0;
		if(++sec == 60)
		{
			sec = 0;
			if(++min == 60)
			{
				min = 0;
			}
		}
		digits[0] = min / 10;
		digits[1] = min % 10;
		digits[2] = sec / 10;
		digits[3] = sec % 10;
	}
	GPIOC_ODR |= 0x0F << 8;
	GPIOC_ODR &= ~0xFF;
	GPIOC_ODR |= encoding[digits[current_digit]];
	GPIOC_ODR &= ~(0x01 << (current_digit + 8));
	current_digit = (current_digit + 1) % 4;
}

void exti_1_handler()
{
	if((EXTI_PR & 0x02) != 0)
	{
		EXTI_PR = 0x02;
		sec = -1;
		min = 0;
	}
}

void tim1_update_handler()
{
	if((TIM1_SR & 0x01) != 0)
	{
		TIM1_SR = 0;
		process_tim1_update_interrupt();
	}
}

int main()
{
	init_RCC();
	init_EXTI();
	init_NVIC();
	init_GPIOC();
	init_GPIOA();
	init_TIM1();
	while(1) {}
}